Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Set pm_display_cfg in non-dc mode
those display informations are needed by powerplay.
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rex Zhu
and committed by
Alex Deucher
d91ea496
b3892e2b
+37
-15
+20
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+20
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
···
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pr_cont("\n");
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}
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+
void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)
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{
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struct drm_device *ddev = adev->ddev;
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struct drm_crtc *crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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+
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adev->pm.dpm.new_active_crtcs = 0;
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adev->pm.dpm.new_active_crtc_count = 0;
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if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
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list_for_each_entry(crtc,
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&ddev->mode_config.crtc_list, head) {
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amdgpu_crtc = to_amdgpu_crtc(crtc);
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if (amdgpu_crtc->enabled) {
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adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
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adev->pm.dpm.new_active_crtc_count++;
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}
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}
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}
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}
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+
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u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
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{
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
···
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struct amdgpu_ps *rps);
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u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
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u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
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+
void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
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bool amdgpu_is_uvd_state(u32 class, u32 class2);
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void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
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u32 *p, u32 *u);
+16
-15
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+16
-15
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
···
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void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
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{
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-
struct drm_device *ddev = adev->ddev;
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struct drm_crtc *crtc;
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-
struct amdgpu_crtc *amdgpu_crtc;
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int i = 0;
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if (!adev->pm.dpm_enabled)
···
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amdgpu_fence_wait_empty(ring);
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}
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if (!amdgpu_device_has_dc_support(adev)) {
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mutex_lock(&adev->pm.mutex);
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amdgpu_dpm_get_active_displays(adev);
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adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
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adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
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adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
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/* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
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if (adev->pm.pm_display_cfg.vrefresh > 120)
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adev->pm.pm_display_cfg.min_vblank_time = 0;
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if (adev->powerplay.pp_funcs->display_configuration_change)
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adev->powerplay.pp_funcs->display_configuration_change(
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adev->powerplay.pp_handle,
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&adev->pm.pm_display_cfg);
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mutex_unlock(&adev->pm.mutex);
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}
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+
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if (adev->powerplay.pp_funcs->dispatch_tasks) {
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amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
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} else {
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.new_active_crtcs = 0;
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adev->pm.dpm.new_active_crtc_count = 0;
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if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
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list_for_each_entry(crtc,
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&ddev->mode_config.crtc_list, head) {
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amdgpu_crtc = to_amdgpu_crtc(crtc);
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if (amdgpu_crtc->enabled) {
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adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
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adev->pm.dpm.new_active_crtc_count++;
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}
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}
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}
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/* update battery/ac status */
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if (power_supply_is_system_supplied() > 0)
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adev->pm.dpm.ac_power = true;