drm/amdgpu: Convert init_mem_ranges into common helpers

+186

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

··· 1491 1491 else 1492 1492 return amdgpu_gmc_get_memory_partition(adev, NULL); 1493 1493 } 1494 + 1495 + static bool amdgpu_gmc_validate_partition_info(struct amdgpu_device *adev) 1496 + { 1497 + enum amdgpu_memory_partition mode; 1498 + u32 supp_modes; 1499 + bool valid; 1500 + 1501 + mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1502 + 1503 + /* Mode detected by hardware not present in supported modes */ 1504 + if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1505 + !(BIT(mode - 1) & supp_modes)) 1506 + return false; 1507 + 1508 + switch (mode) { 1509 + case UNKNOWN_MEMORY_PARTITION_MODE: 1510 + case AMDGPU_NPS1_PARTITION_MODE: 1511 + valid = (adev->gmc.num_mem_partitions == 1); 1512 + break; 1513 + case AMDGPU_NPS2_PARTITION_MODE: 1514 + valid = (adev->gmc.num_mem_partitions == 2); 1515 + break; 1516 + case AMDGPU_NPS4_PARTITION_MODE: 1517 + valid = (adev->gmc.num_mem_partitions == 3 || 1518 + adev->gmc.num_mem_partitions == 4); 1519 + break; 1520 + case AMDGPU_NPS8_PARTITION_MODE: 1521 + valid = (adev->gmc.num_mem_partitions == 8); 1522 + break; 1523 + default: 1524 + valid = false; 1525 + } 1526 + 1527 + return valid; 1528 + } 1529 + 1530 + static bool amdgpu_gmc_is_node_present(int *node_ids, int num_ids, int nid) 1531 + { 1532 + int i; 1533 + 1534 + /* Check if node with id 'nid' is present in 'node_ids' array */ 1535 + for (i = 0; i < num_ids; ++i) 1536 + if (node_ids[i] == nid) 1537 + return true; 1538 + 1539 + return false; 1540 + } 1541 + 1542 + static void 1543 + amdgpu_gmc_init_acpi_mem_ranges(struct amdgpu_device *adev, 1544 + struct amdgpu_mem_partition_info *mem_ranges) 1545 + { 1546 + struct amdgpu_numa_info numa_info; 1547 + int node_ids[AMDGPU_MAX_MEM_RANGES]; 1548 + int num_ranges = 0, ret; 1549 + int num_xcc, xcc_id; 1550 + uint32_t xcc_mask; 1551 + 1552 + num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1553 + xcc_mask = (1U << num_xcc) - 1; 1554 + 1555 + for_each_inst(xcc_id, xcc_mask) { 1556 + ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1557 + if (ret) 1558 + continue; 1559 + 1560 + if (numa_info.nid == NUMA_NO_NODE) { 1561 + mem_ranges[0].size = numa_info.size; 1562 + mem_ranges[0].numa.node = numa_info.nid; 1563 + num_ranges = 1; 1564 + break; 1565 + } 1566 + 1567 + if (amdgpu_gmc_is_node_present(node_ids, num_ranges, 1568 + numa_info.nid)) 1569 + continue; 1570 + 1571 + node_ids[num_ranges] = numa_info.nid; 1572 + mem_ranges[num_ranges].numa.node = numa_info.nid; 1573 + mem_ranges[num_ranges].size = numa_info.size; 1574 + ++num_ranges; 1575 + } 1576 + 1577 + adev->gmc.num_mem_partitions = num_ranges; 1578 + } 1579 + 1580 + void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 1581 + struct amdgpu_mem_partition_info *mem_ranges) 1582 + { 1583 + enum amdgpu_memory_partition mode; 1584 + u32 start_addr = 0, size; 1585 + int i, r, l; 1586 + 1587 + mode = amdgpu_gmc_query_memory_partition(adev); 1588 + 1589 + switch (mode) { 1590 + case UNKNOWN_MEMORY_PARTITION_MODE: 1591 + adev->gmc.num_mem_partitions = 0; 1592 + break; 1593 + case AMDGPU_NPS1_PARTITION_MODE: 1594 + adev->gmc.num_mem_partitions = 1; 1595 + break; 1596 + case AMDGPU_NPS2_PARTITION_MODE: 1597 + adev->gmc.num_mem_partitions = 2; 1598 + break; 1599 + case AMDGPU_NPS4_PARTITION_MODE: 1600 + if (adev->flags & AMD_IS_APU) 1601 + adev->gmc.num_mem_partitions = 3; 1602 + else 1603 + adev->gmc.num_mem_partitions = 4; 1604 + break; 1605 + case AMDGPU_NPS8_PARTITION_MODE: 1606 + adev->gmc.num_mem_partitions = 8; 1607 + break; 1608 + default: 1609 + adev->gmc.num_mem_partitions = 1; 1610 + break; 1611 + } 1612 + 1613 + /* Use NPS range info, if populated */ 1614 + r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1615 + &adev->gmc.num_mem_partitions); 1616 + if (!r) { 1617 + l = 0; 1618 + for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1619 + if (mem_ranges[i].range.lpfn > 1620 + mem_ranges[i - 1].range.lpfn) 1621 + l = i; 1622 + } 1623 + 1624 + } else { 1625 + if (!adev->gmc.num_mem_partitions) { 1626 + dev_warn(adev->dev, 1627 + "Not able to detect NPS mode, fall back to NPS1\n"); 1628 + adev->gmc.num_mem_partitions = 1; 1629 + } 1630 + /* Fallback to sw based calculation */ 1631 + size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 1632 + size /= adev->gmc.num_mem_partitions; 1633 + 1634 + for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1635 + mem_ranges[i].range.fpfn = start_addr; 1636 + mem_ranges[i].size = 1637 + ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1638 + mem_ranges[i].range.lpfn = start_addr + size - 1; 1639 + start_addr += size; 1640 + } 1641 + 1642 + l = adev->gmc.num_mem_partitions - 1; 1643 + } 1644 + 1645 + /* Adjust the last one */ 1646 + mem_ranges[l].range.lpfn = 1647 + (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1648 + mem_ranges[l].size = 1649 + adev->gmc.real_vram_size - 1650 + ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 1651 + } 1652 + 1653 + int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev) 1654 + { 1655 + bool valid; 1656 + 1657 + adev->gmc.mem_partitions = kcalloc(AMDGPU_MAX_MEM_RANGES, 1658 + sizeof(struct amdgpu_mem_partition_info), 1659 + GFP_KERNEL); 1660 + if (!adev->gmc.mem_partitions) 1661 + return -ENOMEM; 1662 + 1663 + if (adev->gmc.is_app_apu) 1664 + amdgpu_gmc_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1665 + else 1666 + amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1667 + 1668 + if (amdgpu_sriov_vf(adev)) 1669 + valid = true; 1670 + else 1671 + valid = amdgpu_gmc_validate_partition_info(adev); 1672 + if (!valid) { 1673 + /* TODO: handle invalid case */ 1674 + dev_warn(adev->dev, 1675 + "Mem ranges not matching with hardware config\n"); 1676 + } 1677 + 1678 + return 0; 1679 + }

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

··· 464 464 amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes); 465 465 enum amdgpu_memory_partition 466 466 amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); 467 + int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); 468 + void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 469 + struct amdgpu_mem_partition_info *mem_ranges); 467 470 #endif

+2 -184

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

··· 1838 1838 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1839 1839 } 1840 1840 1841 - static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1842 - { 1843 - enum amdgpu_memory_partition mode; 1844 - u32 supp_modes; 1845 - bool valid; 1846 - 1847 - mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1848 - 1849 - /* Mode detected by hardware not present in supported modes */ 1850 - if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1851 - !(BIT(mode - 1) & supp_modes)) 1852 - return false; 1853 - 1854 - switch (mode) { 1855 - case UNKNOWN_MEMORY_PARTITION_MODE: 1856 - case AMDGPU_NPS1_PARTITION_MODE: 1857 - valid = (adev->gmc.num_mem_partitions == 1); 1858 - break; 1859 - case AMDGPU_NPS2_PARTITION_MODE: 1860 - valid = (adev->gmc.num_mem_partitions == 2); 1861 - break; 1862 - case AMDGPU_NPS4_PARTITION_MODE: 1863 - valid = (adev->gmc.num_mem_partitions == 3 || 1864 - adev->gmc.num_mem_partitions == 4); 1865 - break; 1866 - default: 1867 - valid = false; 1868 - } 1869 - 1870 - return valid; 1871 - } 1872 - 1873 - static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1874 - { 1875 - int i; 1876 - 1877 - /* Check if node with id 'nid' is present in 'node_ids' array */ 1878 - for (i = 0; i < num_ids; ++i) 1879 - if (node_ids[i] == nid) 1880 - return true; 1881 - 1882 - return false; 1883 - } 1884 - 1885 - static void 1886 - gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1887 - struct amdgpu_mem_partition_info *mem_ranges) 1888 - { 1889 - struct amdgpu_numa_info numa_info; 1890 - int node_ids[AMDGPU_MAX_MEM_RANGES]; 1891 - int num_ranges = 0, ret; 1892 - int num_xcc, xcc_id; 1893 - uint32_t xcc_mask; 1894 - 1895 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1896 - xcc_mask = (1U << num_xcc) - 1; 1897 - 1898 - for_each_inst(xcc_id, xcc_mask) { 1899 - ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1900 - if (ret) 1901 - continue; 1902 - 1903 - if (numa_info.nid == NUMA_NO_NODE) { 1904 - mem_ranges[0].size = numa_info.size; 1905 - mem_ranges[0].numa.node = numa_info.nid; 1906 - num_ranges = 1; 1907 - break; 1908 - } 1909 - 1910 - if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1911 - numa_info.nid)) 1912 - continue; 1913 - 1914 - node_ids[num_ranges] = numa_info.nid; 1915 - mem_ranges[num_ranges].numa.node = numa_info.nid; 1916 - mem_ranges[num_ranges].size = numa_info.size; 1917 - ++num_ranges; 1918 - } 1919 - 1920 - adev->gmc.num_mem_partitions = num_ranges; 1921 - } 1922 - 1923 - static void 1924 - gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1925 - struct amdgpu_mem_partition_info *mem_ranges) 1926 - { 1927 - enum amdgpu_memory_partition mode; 1928 - u32 start_addr = 0, size; 1929 - int i, r, l; 1930 - 1931 - mode = amdgpu_gmc_query_memory_partition(adev); 1932 - 1933 - switch (mode) { 1934 - case UNKNOWN_MEMORY_PARTITION_MODE: 1935 - adev->gmc.num_mem_partitions = 0; 1936 - break; 1937 - case AMDGPU_NPS1_PARTITION_MODE: 1938 - adev->gmc.num_mem_partitions = 1; 1939 - break; 1940 - case AMDGPU_NPS2_PARTITION_MODE: 1941 - adev->gmc.num_mem_partitions = 2; 1942 - break; 1943 - case AMDGPU_NPS4_PARTITION_MODE: 1944 - if (adev->flags & AMD_IS_APU) 1945 - adev->gmc.num_mem_partitions = 3; 1946 - else 1947 - adev->gmc.num_mem_partitions = 4; 1948 - break; 1949 - default: 1950 - adev->gmc.num_mem_partitions = 1; 1951 - break; 1952 - } 1953 - 1954 - /* Use NPS range info, if populated */ 1955 - r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1956 - &adev->gmc.num_mem_partitions); 1957 - if (!r) { 1958 - l = 0; 1959 - for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1960 - if (mem_ranges[i].range.lpfn > 1961 - mem_ranges[i - 1].range.lpfn) 1962 - l = i; 1963 - } 1964 - 1965 - } else { 1966 - if (!adev->gmc.num_mem_partitions) { 1967 - dev_err(adev->dev, 1968 - "Not able to detect NPS mode, fall back to NPS1"); 1969 - adev->gmc.num_mem_partitions = 1; 1970 - } 1971 - /* Fallback to sw based calculation */ 1972 - size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 1973 - size /= adev->gmc.num_mem_partitions; 1974 - 1975 - for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1976 - mem_ranges[i].range.fpfn = start_addr; 1977 - mem_ranges[i].size = 1978 - ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1979 - mem_ranges[i].range.lpfn = start_addr + size - 1; 1980 - start_addr += size; 1981 - } 1982 - 1983 - l = adev->gmc.num_mem_partitions - 1; 1984 - } 1985 - 1986 - /* Adjust the last one */ 1987 - mem_ranges[l].range.lpfn = 1988 - (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1989 - mem_ranges[l].size = 1990 - adev->gmc.real_vram_size - 1991 - ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 1992 - } 1993 - 1994 - static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1995 - { 1996 - bool valid; 1997 - 1998 - adev->gmc.mem_partitions = kcalloc(AMDGPU_MAX_MEM_RANGES, 1999 - sizeof(struct amdgpu_mem_partition_info), 2000 - GFP_KERNEL); 2001 - if (!adev->gmc.mem_partitions) 2002 - return -ENOMEM; 2003 - 2004 - /* TODO : Get the range from PSP/Discovery for dGPU */ 2005 - if (adev->gmc.is_app_apu) 2006 - gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 2007 - else 2008 - gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2009 - 2010 - if (amdgpu_sriov_vf(adev)) 2011 - valid = true; 2012 - else 2013 - valid = gmc_v9_0_validate_partition_info(adev); 2014 - if (!valid) { 2015 - /* TODO: handle invalid case */ 2016 - dev_WARN(adev->dev, 2017 - "Mem ranges not matching with hardware config"); 2018 - } 2019 - 2020 - return 0; 2021 - } 2022 - 2023 1841 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 2024 1842 { 2025 1843 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; ··· 2010 2192 amdgpu_gmc_get_vbios_allocations(adev); 2011 2193 2012 2194 if (amdgpu_is_multi_aid(adev)) { 2013 - r = gmc_v9_0_init_mem_ranges(adev); 2195 + r = amdgpu_gmc_init_mem_ranges(adev); 2014 2196 if (r) 2015 2197 return r; 2016 2198 } ··· 2292 2474 * information again. 2293 2475 */ 2294 2476 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2295 - gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2477 + amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2296 2478 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2297 2479 } 2298 2480

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