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spi: add multi_lane_mode field to struct spi_transfer

Add a new multi_lane_mode field to struct spi_transfer to allow
peripherals that support multiple SPI lanes to be used with a single
SPI controller.

This requires both the peripheral and the controller to have multiple
serializers connected to separate data lanes. It could also be used with
a single controller and multiple peripherals that are functioning as a
single logical device (similar to parallel memories).

Acked-by: Nuno Sá <nuno.sa@analog.com>
Acked-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-4-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

David Lechner and committed by
Mark Brown 5621a7bc 002d561f

+8
+8
include/linux/spi/spi.h
··· 981 981 * (SPI_NBITS_SINGLE) is used. 982 982 * @rx_nbits: number of bits used for reading. If 0 the default 983 983 * (SPI_NBITS_SINGLE) is used. 984 + * @multi_lane_mode: How to serialize data on multiple lanes. One of the 985 + * SPI_MULTI_LANE_MODE_* values. 984 986 * @len: size of rx and tx buffers (in bytes) 985 987 * @speed_hz: Select a speed other than the device default for this 986 988 * transfer. If 0 the default (from @spi_device) is used. ··· 1119 1117 unsigned cs_change:1; 1120 1118 unsigned tx_nbits:4; 1121 1119 unsigned rx_nbits:4; 1120 + 1121 + #define SPI_MULTI_LANE_MODE_SINGLE 0 /* only use single lane */ 1122 + #define SPI_MULTI_LANE_MODE_STRIPE 1 /* one data word per lane */ 1123 + #define SPI_MULTI_LANE_MODE_MIRROR 2 /* same word sent on all lanes */ 1124 + unsigned multi_lane_mode: 2; 1125 + 1122 1126 unsigned timestamped:1; 1123 1127 bool dtr_mode; 1124 1128 #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */