Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'bnxt_en-driver-update'
Michael Chan says:
====================
bnxt_en: Driver update
This patchset contains these updates to the driver:
1. New ethtool coredump type for FW to include cached context for live dump.
2. Support ENABLE_ROCE devlink generic parameter.
3. Support capability change flag from FW.
4. FW interface update.
5. Support .set_module_eeprom_by_page().
====================
Link: https://patch.msgid.link/20250310183129.3154117-1-michael.chan@broadcom.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+279
-66
+2
Documentation/networking/devlink/bnxt.rst
+2
Documentation/networking/devlink/bnxt.rst
+6
-2
drivers/net/ethernet/broadcom/bnxt/bnxt.c
+6
-2
drivers/net/ethernet/broadcom/bnxt/bnxt.c
···
12309
12309
struct hwrm_func_drv_if_change_input *req;
12310
12310
bool fw_reset = !bp->irq_tbl;
12311
12311
bool resc_reinit = false;
12312
+
bool caps_change = false;
12312
12313
int rc, retry = 0;
12313
12314
u32 flags = 0;
12314
12315
···
12365
12364
set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
12366
12365
return -ENODEV;
12367
12366
}
12368
-
if (resc_reinit || fw_reset) {
12369
-
if (fw_reset) {
12367
+
if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE)
12368
+
caps_change = true;
12369
+
12370
+
if (resc_reinit || fw_reset || caps_change) {
12371
+
if (fw_reset || caps_change) {
12370
12372
set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
12371
12373
if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
12372
12374
bnxt_ulp_irq_stop(bp);
+1
drivers/net/ethernet/broadcom/bnxt/bnxt.h
+1
drivers/net/ethernet/broadcom/bnxt/bnxt.h
+6
-3
drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.c
+6
-3
drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.c
···
159
159
return rc;
160
160
}
161
161
162
-
static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
163
-
u16 segment_id)
162
+
static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 dump_type,
163
+
u16 component_id, u16 segment_id)
164
164
{
165
165
struct hwrm_dbg_coredump_initiate_input *req;
166
166
int rc;
···
172
172
hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
173
173
req->component_id = cpu_to_le16(component_id);
174
174
req->segment_id = cpu_to_le16(segment_id);
175
+
if (dump_type == BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE)
176
+
req->seg_flags = DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE;
175
177
176
178
return hwrm_req_send(bp, req);
177
179
}
···
452
450
453
451
start = jiffies;
454
452
455
-
rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
453
+
rc = bnxt_hwrm_dbg_coredump_initiate(bp, dump_type, comp_id,
454
+
seg_id);
456
455
if (rc) {
457
456
netdev_err(bp->dev,
458
457
"Failed to initiate coredump for seg = %d\n",
+65
-30
drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c
+65
-30
drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c
···
679
679
NVM_OFF_MSIX_VEC_PER_PF_MAX, BNXT_NVM_SHARED_CFG, 10, 4},
680
680
{DEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN,
681
681
NVM_OFF_MSIX_VEC_PER_PF_MIN, BNXT_NVM_SHARED_CFG, 7, 4},
682
+
{DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, NVM_OFF_SUPPORT_RDMA,
683
+
BNXT_NVM_FUNC_CFG, 1, 1},
682
684
{BNXT_DEVLINK_PARAM_ID_GRE_VER_CHECK, NVM_OFF_DIS_GRE_VER_CHECK,
683
685
BNXT_NVM_SHARED_CFG, 1, 1},
684
686
};
···
1025
1023
1026
1024
}
1027
1025
1028
-
static int bnxt_hwrm_nvm_req(struct bnxt *bp, u32 param_id, void *msg,
1029
-
union devlink_param_value *val)
1026
+
static int __bnxt_hwrm_nvm_req(struct bnxt *bp,
1027
+
const struct bnxt_dl_nvm_param *nvm, void *msg,
1028
+
union devlink_param_value *val)
1030
1029
{
1031
1030
struct hwrm_nvm_get_variable_input *req = msg;
1032
-
struct bnxt_dl_nvm_param nvm_param;
1033
1031
struct hwrm_err_output *resp;
1034
1032
union bnxt_nvm_data *data;
1035
1033
dma_addr_t data_dma_addr;
1036
-
int idx = 0, rc, i;
1034
+
int idx = 0, rc;
1037
1035
1038
-
/* Get/Set NVM CFG parameter is supported only on PFs */
1039
-
if (BNXT_VF(bp)) {
1040
-
hwrm_req_drop(bp, req);
1041
-
return -EPERM;
1042
-
}
1043
-
1044
-
for (i = 0; i < ARRAY_SIZE(nvm_params); i++) {
1045
-
if (nvm_params[i].id == param_id) {
1046
-
nvm_param = nvm_params[i];
1047
-
break;
1048
-
}
1049
-
}
1050
-
1051
-
if (i == ARRAY_SIZE(nvm_params)) {
1052
-
hwrm_req_drop(bp, req);
1053
-
return -EOPNOTSUPP;
1054
-
}
1055
-
1056
-
if (nvm_param.dir_type == BNXT_NVM_PORT_CFG)
1036
+
if (nvm->dir_type == BNXT_NVM_PORT_CFG)
1057
1037
idx = bp->pf.port_id;
1058
-
else if (nvm_param.dir_type == BNXT_NVM_FUNC_CFG)
1038
+
else if (nvm->dir_type == BNXT_NVM_FUNC_CFG)
1059
1039
idx = bp->pf.fw_fid - BNXT_FIRST_PF_FID;
1060
1040
1061
1041
data = hwrm_req_dma_slice(bp, req, sizeof(*data), &data_dma_addr);
···
1048
1064
}
1049
1065
1050
1066
req->dest_data_addr = cpu_to_le64(data_dma_addr);
1051
-
req->data_len = cpu_to_le16(nvm_param.nvm_num_bits);
1052
-
req->option_num = cpu_to_le16(nvm_param.offset);
1067
+
req->data_len = cpu_to_le16(nvm->nvm_num_bits);
1068
+
req->option_num = cpu_to_le16(nvm->offset);
1053
1069
req->index_0 = cpu_to_le16(idx);
1054
1070
if (idx)
1055
1071
req->dimensions = cpu_to_le16(1);
1056
1072
1057
1073
resp = hwrm_req_hold(bp, req);
1058
1074
if (req->req_type == cpu_to_le16(HWRM_NVM_SET_VARIABLE)) {
1059
-
bnxt_copy_to_nvm_data(data, val, nvm_param.nvm_num_bits,
1060
-
nvm_param.dl_num_bytes);
1075
+
bnxt_copy_to_nvm_data(data, val, nvm->nvm_num_bits,
1076
+
nvm->dl_num_bytes);
1061
1077
rc = hwrm_req_send(bp, msg);
1062
1078
} else {
1063
1079
rc = hwrm_req_send_silent(bp, msg);
1064
1080
if (!rc) {
1065
1081
bnxt_copy_from_nvm_data(val, data,
1066
-
nvm_param.nvm_num_bits,
1067
-
nvm_param.dl_num_bytes);
1082
+
nvm->nvm_num_bits,
1083
+
nvm->dl_num_bytes);
1068
1084
} else {
1069
1085
if (resp->cmd_err ==
1070
1086
NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST)
···
1075
1091
if (rc == -EACCES)
1076
1092
netdev_err(bp->dev, "PF does not have admin privileges to modify NVM config\n");
1077
1093
return rc;
1094
+
}
1095
+
1096
+
static int bnxt_hwrm_nvm_req(struct bnxt *bp, u32 param_id, void *msg,
1097
+
union devlink_param_value *val)
1098
+
{
1099
+
struct hwrm_nvm_get_variable_input *req = msg;
1100
+
const struct bnxt_dl_nvm_param *nvm_param;
1101
+
int i;
1102
+
1103
+
/* Get/Set NVM CFG parameter is supported only on PFs */
1104
+
if (BNXT_VF(bp)) {
1105
+
hwrm_req_drop(bp, req);
1106
+
return -EPERM;
1107
+
}
1108
+
1109
+
for (i = 0; i < ARRAY_SIZE(nvm_params); i++) {
1110
+
nvm_param = &nvm_params[i];
1111
+
if (nvm_param->id == param_id)
1112
+
return __bnxt_hwrm_nvm_req(bp, nvm_param, msg, val);
1113
+
}
1114
+
return -EOPNOTSUPP;
1078
1115
}
1079
1116
1080
1117
static int bnxt_dl_nvm_param_get(struct devlink *dl, u32 id,
···
1132
1127
ctx->val.vbool = !ctx->val.vbool;
1133
1128
1134
1129
return bnxt_hwrm_nvm_req(bp, id, req, &ctx->val);
1130
+
}
1131
+
1132
+
static int bnxt_dl_roce_validate(struct devlink *dl, u32 id,
1133
+
union devlink_param_value val,
1134
+
struct netlink_ext_ack *extack)
1135
+
{
1136
+
const struct bnxt_dl_nvm_param nvm_roce_cap = {0, NVM_OFF_RDMA_CAPABLE,
1137
+
BNXT_NVM_SHARED_CFG, 1, 1};
1138
+
struct bnxt *bp = bnxt_get_bp_from_dl(dl);
1139
+
struct hwrm_nvm_get_variable_input *req;
1140
+
union devlink_param_value roce_cap;
1141
+
int rc;
1142
+
1143
+
rc = hwrm_req_init(bp, req, HWRM_NVM_GET_VARIABLE);
1144
+
if (rc)
1145
+
return rc;
1146
+
1147
+
if (__bnxt_hwrm_nvm_req(bp, &nvm_roce_cap, req, &roce_cap)) {
1148
+
NL_SET_ERR_MSG_MOD(extack, "Unable to verify if device is RDMA Capable");
1149
+
return -EINVAL;
1150
+
}
1151
+
if (!roce_cap.vbool) {
1152
+
NL_SET_ERR_MSG_MOD(extack, "Device does not support RDMA");
1153
+
return -EINVAL;
1154
+
}
1155
+
return 0;
1135
1156
}
1136
1157
1137
1158
static int bnxt_dl_msix_validate(struct devlink *dl, u32 id,
···
1224
1193
BIT(DEVLINK_PARAM_CMODE_PERMANENT),
1225
1194
bnxt_dl_nvm_param_get, bnxt_dl_nvm_param_set,
1226
1195
bnxt_dl_msix_validate),
1196
+
DEVLINK_PARAM_GENERIC(ENABLE_ROCE,
1197
+
BIT(DEVLINK_PARAM_CMODE_PERMANENT),
1198
+
bnxt_dl_nvm_param_get, bnxt_dl_nvm_param_set,
1199
+
bnxt_dl_roce_validate),
1227
1200
DEVLINK_PARAM_DRIVER(BNXT_DEVLINK_PARAM_ID_GRE_VER_CHECK,
1228
1201
"gre_ver_check", DEVLINK_PARAM_TYPE_BOOL,
1229
1202
BIT(DEVLINK_PARAM_CMODE_PERMANENT),
+2
drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.h
+2
drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.h
···
41
41
#define NVM_OFF_MSIX_VEC_PER_PF_MAX 108
42
42
#define NVM_OFF_MSIX_VEC_PER_PF_MIN 114
43
43
#define NVM_OFF_IGNORE_ARI 164
44
+
#define NVM_OFF_RDMA_CAPABLE 161
44
45
#define NVM_OFF_DIS_GRE_VER_CHECK 171
45
46
#define NVM_OFF_ENABLE_SRIOV 401
47
+
#define NVM_OFF_SUPPORT_RDMA 506
46
48
#define NVM_OFF_NVM_CFG_VER 602
47
49
48
50
#define BNXT_NVM_CFG_VER_BITS 8
+78
-7
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
+78
-7
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
···
4541
4541
return -EINVAL;
4542
4542
}
4543
4543
4544
-
static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4545
-
const struct ethtool_module_eeprom *page_data,
4546
-
struct netlink_ext_ack *extack)
4544
+
static int
4545
+
bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp,
4546
+
const struct ethtool_module_eeprom *page_data,
4547
+
struct netlink_ext_ack *extack)
4547
4548
{
4548
-
struct bnxt *bp = netdev_priv(dev);
4549
4549
int rc;
4550
4550
4551
4551
if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
4552
4552
NL_SET_ERR_MSG_MOD(extack,
4553
-
"Module read not permitted on untrusted VF");
4553
+
"Module read/write not permitted on untrusted VF");
4554
4554
return -EPERM;
4555
4555
}
4556
4556
···
4567
4567
NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
4568
4568
return -EINVAL;
4569
4569
}
4570
+
return 0;
4571
+
}
4572
+
4573
+
static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4574
+
const struct ethtool_module_eeprom *page_data,
4575
+
struct netlink_ext_ack *extack)
4576
+
{
4577
+
struct bnxt *bp = netdev_priv(dev);
4578
+
int rc;
4579
+
4580
+
rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack);
4581
+
if (rc)
4582
+
return rc;
4570
4583
4571
4584
rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
4572
4585
page_data->page, page_data->bank,
···
4588
4575
page_data->data);
4589
4576
if (rc) {
4590
4577
NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
4578
+
return rc;
4579
+
}
4580
+
return page_data->length;
4581
+
}
4582
+
4583
+
static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp,
4584
+
const struct ethtool_module_eeprom *page)
4585
+
{
4586
+
struct hwrm_port_phy_i2c_write_input *req;
4587
+
int bytes_written = 0;
4588
+
int rc;
4589
+
4590
+
rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE);
4591
+
if (rc)
4592
+
return rc;
4593
+
4594
+
hwrm_req_hold(bp, req);
4595
+
req->i2c_slave_addr = page->i2c_address << 1;
4596
+
req->page_number = cpu_to_le16(page->page);
4597
+
req->bank_number = page->bank;
4598
+
req->port_id = cpu_to_le16(bp->pf.port_id);
4599
+
req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET |
4600
+
PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER);
4601
+
4602
+
while (bytes_written < page->length) {
4603
+
u16 xfer_size;
4604
+
4605
+
xfer_size = min_t(u16, page->length - bytes_written,
4606
+
BNXT_MAX_PHY_I2C_RESP_SIZE);
4607
+
req->page_offset = cpu_to_le16(page->offset + bytes_written);
4608
+
req->data_length = xfer_size;
4609
+
memcpy(req->data, page->data + bytes_written, xfer_size);
4610
+
rc = hwrm_req_send(bp, req);
4611
+
if (rc)
4612
+
break;
4613
+
bytes_written += xfer_size;
4614
+
}
4615
+
4616
+
hwrm_req_drop(bp, req);
4617
+
return rc;
4618
+
}
4619
+
4620
+
static int bnxt_set_module_eeprom_by_page(struct net_device *dev,
4621
+
const struct ethtool_module_eeprom *page_data,
4622
+
struct netlink_ext_ack *extack)
4623
+
{
4624
+
struct bnxt *bp = netdev_priv(dev);
4625
+
int rc;
4626
+
4627
+
rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack);
4628
+
if (rc)
4629
+
return rc;
4630
+
4631
+
rc = bnxt_write_sfp_module_eeprom_info(bp, page_data);
4632
+
if (rc) {
4633
+
NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed");
4591
4634
return rc;
4592
4635
}
4593
4636
return page_data->length;
···
5146
5077
{
5147
5078
struct bnxt *bp = netdev_priv(dev);
5148
5079
5149
-
if (dump->flag > BNXT_DUMP_DRIVER) {
5150
-
netdev_info(dev, "Supports only Live(0), Crash(1), Driver(2) dumps.\n");
5080
+
if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) {
5081
+
netdev_info(dev,
5082
+
"Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n");
5151
5083
return -EINVAL;
5152
5084
}
5153
5085
···
5511
5441
.get_module_info = bnxt_get_module_info,
5512
5442
.get_module_eeprom = bnxt_get_module_eeprom,
5513
5443
.get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
5444
+
.set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page,
5514
5445
.nway_reset = bnxt_nway_reset,
5515
5446
.set_phys_id = bnxt_set_phys_id,
5516
5447
.self_test = bnxt_self_test,
+119
-24
drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
+119
-24
drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
···
2
2
*
3
3
* Copyright (c) 2014-2016 Broadcom Corporation
4
4
* Copyright (c) 2014-2018 Broadcom Limited
5
-
* Copyright (c) 2018-2024 Broadcom Inc.
5
+
* Copyright (c) 2018-2025 Broadcom Inc.
6
6
*
7
7
* This program is free software; you can redistribute it and/or modify
8
8
* it under the terms of the GNU General Public License as published by
···
438
438
#define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL
439
439
#define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL
440
440
#define HWRM_MFG_TESTS 0x21bUL
441
+
#define HWRM_MFG_WRITE_CERT_NVM 0x21cUL
441
442
#define HWRM_PORT_POE_CFG 0x230UL
442
443
#define HWRM_PORT_POE_QCFG 0x231UL
443
444
#define HWRM_UDCC_QCAPS 0x258UL
···
515
514
#define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL
516
515
#define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL
517
516
#define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL
517
+
#define HWRM_TFC_TCAM_PRI_UPDATE 0x39dUL
518
+
#define HWRM_TFC_HOT_UPGRADE_PROCESS 0x3a0UL
518
519
#define HWRM_SV 0x400UL
519
520
#define HWRM_DBG_SERDES_TEST 0xff0eUL
520
521
#define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL
···
632
629
#define HWRM_VERSION_MAJOR 1
633
630
#define HWRM_VERSION_MINOR 10
634
631
#define HWRM_VERSION_UPDATE 3
635
-
#define HWRM_VERSION_RSVD 85
636
-
#define HWRM_VERSION_STR "1.10.3.85"
632
+
#define HWRM_VERSION_RSVD 97
633
+
#define HWRM_VERSION_STR "1.10.3.97"
637
634
638
635
/* hwrm_ver_get_input (size:192b/24B) */
639
636
struct hwrm_ver_get_input {
···
1908
1905
__le32 roce_vf_max_srq;
1909
1906
__le32 roce_vf_max_gid;
1910
1907
__le32 flags_ext3;
1911
-
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
1912
-
#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
1913
-
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
1908
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
1909
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
1910
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
1911
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED 0x8UL
1912
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_BIDI_OPT_SUPPORTED 0x10UL
1913
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED 0x20UL
1914
1914
__le16 max_roce_vfs;
1915
-
u8 unused_3[5];
1915
+
__le16 max_crypto_rx_flow_filters;
1916
+
u8 unused_3[3];
1916
1917
u8 valid;
1917
1918
};
1918
1919
···
1931
1924
u8 unused_0[6];
1932
1925
};
1933
1926
1934
-
/* hwrm_func_qcfg_output (size:1280b/160B) */
1927
+
/* hwrm_func_qcfg_output (size:1344b/168B) */
1935
1928
struct hwrm_func_qcfg_output {
1936
1929
__le16 error_code;
1937
1930
__le16 req_type;
···
2094
2087
__le16 host_mtu;
2095
2088
__le16 flags2;
2096
2089
#define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL
2097
-
u8 unused_4[2];
2090
+
__le16 stag_vid;
2098
2091
u8 port_kdnet_mode;
2099
2092
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL
2100
2093
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL
2101
2094
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED
2102
2095
u8 kdnet_pcie_function;
2103
2096
__le16 port_kdnet_fid;
2104
-
u8 unused_5[2];
2097
+
u8 unused_5;
2098
+
u8 roce_bidi_opt_mode;
2099
+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DISABLED 0x1UL
2100
+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DEDICATED 0x2UL
2101
+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_SHARED 0x4UL
2105
2102
__le32 num_ktls_tx_key_ctxs;
2106
2103
__le32 num_ktls_rx_key_ctxs;
2107
2104
u8 lag_id;
···
2123
2112
__le16 xid_partition_cfg;
2124
2113
#define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL
2125
2114
#define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL
2126
-
u8 unused_7;
2115
+
__le16 mirror_vnic_id;
2116
+
u8 unused_7[7];
2127
2117
u8 valid;
2128
2118
};
2129
2119
···
3977
3965
__le32 region_num_entries;
3978
3966
u8 tsid;
3979
3967
u8 lkup_static_bkt_cnt_exp[2];
3980
-
u8 rsvd;
3968
+
u8 locked;
3981
3969
__le32 rsvd2[2];
3982
3970
};
3983
3971
···
5495
5483
u8 valid;
5496
5484
};
5497
5485
5486
+
/* hwrm_port_phy_i2c_write_input (size:832b/104B) */
5487
+
struct hwrm_port_phy_i2c_write_input {
5488
+
__le16 req_type;
5489
+
__le16 cmpl_ring;
5490
+
__le16 seq_id;
5491
+
__le16 target_id;
5492
+
__le64 resp_addr;
5493
+
__le32 flags;
5494
+
__le32 enables;
5495
+
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET 0x1UL
5496
+
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER 0x2UL
5497
+
__le16 port_id;
5498
+
u8 i2c_slave_addr;
5499
+
u8 bank_number;
5500
+
__le16 page_number;
5501
+
__le16 page_offset;
5502
+
u8 data_length;
5503
+
u8 unused_1[7];
5504
+
__le32 data[16];
5505
+
};
5506
+
5507
+
/* hwrm_port_phy_i2c_write_output (size:128b/16B) */
5508
+
struct hwrm_port_phy_i2c_write_output {
5509
+
__le16 error_code;
5510
+
__le16 req_type;
5511
+
__le16 seq_id;
5512
+
__le16 resp_len;
5513
+
u8 unused_0[7];
5514
+
u8 valid;
5515
+
};
5516
+
5498
5517
/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
5499
5518
struct hwrm_port_phy_i2c_read_input {
5500
5519
__le16 req_type;
···
6653
6610
__le32 flags;
6654
6611
#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
6655
6612
#define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL
6613
+
#define VNIC_ALLOC_REQ_FLAGS_VNIC_ID_VALID 0x4UL
6656
6614
__le16 virtio_net_fid;
6657
-
u8 unused_0[2];
6615
+
__le16 vnic_id;
6658
6616
};
6659
6617
6660
6618
/* hwrm_vnic_alloc_output (size:128b/16B) */
···
6754
6710
#define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
6755
6711
#define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
6756
6712
#define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL
6713
+
#define VNIC_CFG_REQ_ENABLES_RAW_QP_ID 0x400UL
6757
6714
__le16 vnic_id;
6758
6715
__le16 dflt_ring_grp;
6759
6716
__le16 rss_rule;
···
6774
6729
#define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL
6775
6730
#define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL
6776
6731
#define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED
6777
-
u8 unused0[4];
6732
+
__le32 raw_qp_id;
6778
6733
};
6779
6734
6780
6735
/* hwrm_vnic_cfg_output (size:128b/16B) */
···
7127
7082
u8 valid;
7128
7083
};
7129
7084
7085
+
/* hwrm_vnic_plcmodes_cfg_cmd_err (size:64b/8B) */
7086
+
struct hwrm_vnic_plcmodes_cfg_cmd_err {
7087
+
u8 code;
7088
+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
7089
+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 0x1UL
7090
+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_LAST VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD
7091
+
u8 unused_0[7];
7092
+
};
7093
+
7130
7094
/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
7131
7095
struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
7132
7096
__le16 req_type;
···
7185
7131
__le16 target_id;
7186
7132
__le64 resp_addr;
7187
7133
__le32 enables;
7188
-
#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
7189
-
#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
7190
-
#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
7191
-
#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
7192
-
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
7193
-
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
7194
-
#define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
7195
-
#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
7196
-
#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL
7134
+
#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
7135
+
#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
7136
+
#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
7137
+
#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
7138
+
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
7139
+
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
7140
+
#define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
7141
+
#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
7142
+
#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL
7143
+
#define RING_ALLOC_REQ_ENABLES_RX_RATE_PROFILE_VALID 0x1000UL
7197
7144
u8 ring_type;
7198
7145
#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
7199
7146
#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
···
7281
7226
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
7282
7227
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
7283
7228
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
7284
-
u8 unused_4[2];
7229
+
u8 rx_rate_profile_sel;
7230
+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_DEFAULT 0x0UL
7231
+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 0x1UL
7232
+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_LAST RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE
7233
+
u8 unused_4;
7285
7234
__le64 cq_handle;
7286
7235
};
7287
7236
···
9181
9122
__le64 pcie_recovery_histogram;
9182
9123
};
9183
9124
9125
+
/* pcie_ctx_hw_stats_v2 (size:4096b/512B) */
9126
+
struct pcie_ctx_hw_stats_v2 {
9127
+
__le64 pcie_pl_signal_integrity;
9128
+
__le64 pcie_dl_signal_integrity;
9129
+
__le64 pcie_tl_signal_integrity;
9130
+
__le64 pcie_link_integrity;
9131
+
__le64 pcie_tx_traffic_rate;
9132
+
__le64 pcie_rx_traffic_rate;
9133
+
__le64 pcie_tx_dllp_statistics;
9134
+
__le64 pcie_rx_dllp_statistics;
9135
+
__le64 pcie_equalization_time;
9136
+
__le32 pcie_ltssm_histogram[4];
9137
+
__le64 pcie_recovery_histogram;
9138
+
__le32 pcie_tl_credit_nph_histogram[8];
9139
+
__le32 pcie_tl_credit_ph_histogram[8];
9140
+
__le32 pcie_tl_credit_pd_histogram[8];
9141
+
__le32 pcie_cmpl_latest_times[4];
9142
+
__le32 pcie_cmpl_longest_time;
9143
+
__le32 pcie_cmpl_shortest_time;
9144
+
__le32 unused_0[2];
9145
+
__le32 pcie_cmpl_latest_headers[4][4];
9146
+
__le32 pcie_cmpl_longest_headers[4][4];
9147
+
__le32 pcie_cmpl_shortest_headers[4][4];
9148
+
__le32 pcie_wr_latency_histogram[12];
9149
+
__le32 pcie_wr_latency_all_normal_count;
9150
+
__le32 unused_1;
9151
+
__le64 pcie_posted_packet_count;
9152
+
__le64 pcie_non_posted_packet_count;
9153
+
__le64 pcie_other_packet_count;
9154
+
__le64 pcie_blocked_packet_count;
9155
+
__le64 pcie_cmpl_packet_count;
9156
+
};
9157
+
9184
9158
/* hwrm_stat_generic_qstats_input (size:256b/32B) */
9185
9159
struct hwrm_stat_generic_qstats_input {
9186
9160
__le16 req_type;
···
9409
9317
#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND
9410
9318
__le16 len;
9411
9319
u8 version;
9320
+
#define STRUCT_HDR_VERSION_0 0x0UL
9321
+
#define STRUCT_HDR_VERSION_1 0x1UL
9322
+
#define STRUCT_HDR_VERSION_LAST STRUCT_HDR_VERSION_1
9412
9323
u8 count;
9413
9324
__le16 subtype;
9414
9325
__le16 next_offset;