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linux
clk: samsung: exynos850: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-10-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+24
-11
+24
-11
drivers/clk/samsung/clk-exynos850.c
+24
-11
drivers/clk/samsung/clk-exynos850.c
···
17
17
#include "clk.h"
18
18
#include "clk-exynos-arm64.h"
19
19
20
+
/* NOTE: Must be equal to the last clock ID increased by one */
21
+
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
22
+
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
23
+
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
24
+
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
25
+
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
26
+
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
27
+
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
28
+
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
29
+
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
30
+
#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
31
+
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
32
+
20
33
/* ---- CMU_TOP ------------------------------------------------------------- */
21
34
22
35
/* Register Offset definitions for CMU_TOP (0x120e0000) */
···
499
486
.nr_div_clks = ARRAY_SIZE(top_div_clks),
500
487
.gate_clks = top_gate_clks,
501
488
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
502
-
.nr_clk_ids = TOP_NR_CLK,
489
+
.nr_clk_ids = CLKS_NR_TOP,
503
490
.clk_regs = top_clk_regs,
504
491
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
505
492
};
···
639
626
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
640
627
.fixed_clks = apm_fixed_clks,
641
628
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
642
-
.nr_clk_ids = APM_NR_CLK,
629
+
.nr_clk_ids = CLKS_NR_APM,
643
630
.clk_regs = apm_clk_regs,
644
631
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
645
632
.clk_name = "dout_clkcmu_apm_bus",
···
922
909
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
923
910
.fixed_clks = aud_fixed_clks,
924
911
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
925
-
.nr_clk_ids = AUD_NR_CLK,
912
+
.nr_clk_ids = CLKS_NR_AUD,
926
913
.clk_regs = aud_clk_regs,
927
914
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
928
915
.clk_name = "dout_aud",
···
1025
1012
.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
1026
1013
.fixed_clks = cmgp_fixed_clks,
1027
1014
.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
1028
-
.nr_clk_ids = CMGP_NR_CLK,
1015
+
.nr_clk_ids = CLKS_NR_CMGP,
1029
1016
.clk_regs = cmgp_clk_regs,
1030
1017
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
1031
1018
.clk_name = "gout_clkcmu_cmgp_bus",
···
1121
1108
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
1122
1109
.gate_clks = g3d_gate_clks,
1123
1110
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1124
-
.nr_clk_ids = G3D_NR_CLK,
1111
+
.nr_clk_ids = CLKS_NR_G3D,
1125
1112
.clk_regs = g3d_clk_regs,
1126
1113
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
1127
1114
.clk_name = "dout_g3d_switch",
···
1223
1210
.nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
1224
1211
.gate_clks = hsi_gate_clks,
1225
1212
.nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
1226
-
.nr_clk_ids = HSI_NR_CLK,
1213
+
.nr_clk_ids = CLKS_NR_HSI,
1227
1214
.clk_regs = hsi_clk_regs,
1228
1215
.nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
1229
1216
.clk_name = "dout_hsi_bus",
···
1355
1342
.nr_div_clks = ARRAY_SIZE(is_div_clks),
1356
1343
.gate_clks = is_gate_clks,
1357
1344
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
1358
-
.nr_clk_ids = IS_NR_CLK,
1345
+
.nr_clk_ids = CLKS_NR_IS,
1359
1346
.clk_regs = is_clk_regs,
1360
1347
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
1361
1348
.clk_name = "dout_is_bus",
···
1464
1451
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
1465
1452
.gate_clks = mfcmscl_gate_clks,
1466
1453
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1467
-
.nr_clk_ids = MFCMSCL_NR_CLK,
1454
+
.nr_clk_ids = CLKS_NR_MFCMSCL,
1468
1455
.clk_regs = mfcmscl_clk_regs,
1469
1456
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
1470
1457
.clk_name = "dout_mfcmscl_mfc",
···
1639
1626
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
1640
1627
.gate_clks = peri_gate_clks,
1641
1628
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
1642
-
.nr_clk_ids = PERI_NR_CLK,
1629
+
.nr_clk_ids = CLKS_NR_PERI,
1643
1630
.clk_regs = peri_clk_regs,
1644
1631
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
1645
1632
.clk_name = "dout_peri_bus",
···
1746
1733
.nr_div_clks = ARRAY_SIZE(core_div_clks),
1747
1734
.gate_clks = core_gate_clks,
1748
1735
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1749
-
.nr_clk_ids = CORE_NR_CLK,
1736
+
.nr_clk_ids = CLKS_NR_CORE,
1750
1737
.clk_regs = core_clk_regs,
1751
1738
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
1752
1739
.clk_name = "dout_core_bus",
···
1820
1807
.nr_div_clks = ARRAY_SIZE(dpu_div_clks),
1821
1808
.gate_clks = dpu_gate_clks,
1822
1809
.nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
1823
-
.nr_clk_ids = DPU_NR_CLK,
1810
+
.nr_clk_ids = CLKS_NR_DPU,
1824
1811
.clk_regs = dpu_clk_regs,
1825
1812
.nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
1826
1813
.clk_name = "dout_dpu",