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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
clk: samsung: exynos7885: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+10
-4
+10
-4
drivers/clk/samsung/clk-exynos7885.c
+10
-4
drivers/clk/samsung/clk-exynos7885.c
···
17
17
#include "clk.h"
18
18
#include "clk-exynos-arm64.h"
19
19
20
+
/* NOTE: Must be equal to the last clock ID increased by one */
21
+
#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
22
+
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
23
+
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
24
+
#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
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+
20
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/* ---- CMU_TOP ------------------------------------------------------------- */
21
27
22
28
/* Register Offset definitions for CMU_TOP (0x12060000) */
···
340
334
.nr_div_clks = ARRAY_SIZE(top_div_clks),
341
335
.gate_clks = top_gate_clks,
342
336
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
343
-
.nr_clk_ids = TOP_NR_CLK,
337
+
.nr_clk_ids = CLKS_NR_TOP,
344
338
.clk_regs = top_clk_regs,
345
339
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
346
340
};
···
559
553
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
560
554
.gate_clks = peri_gate_clks,
561
555
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
562
-
.nr_clk_ids = PERI_NR_CLK,
556
+
.nr_clk_ids = CLKS_NR_PERI,
563
557
.clk_regs = peri_clk_regs,
564
558
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
565
559
.clk_name = "dout_peri_bus",
···
668
662
.nr_div_clks = ARRAY_SIZE(core_div_clks),
669
663
.gate_clks = core_gate_clks,
670
664
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
671
-
.nr_clk_ids = CORE_NR_CLK,
665
+
.nr_clk_ids = CLKS_NR_CORE,
672
666
.clk_regs = core_clk_regs,
673
667
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
674
668
.clk_name = "dout_core_bus",
···
750
744
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
751
745
.gate_clks = fsys_gate_clks,
752
746
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
753
-
.nr_clk_ids = FSYS_NR_CLK,
747
+
.nr_clk_ids = CLKS_NR_FSYS,
754
748
.clk_regs = fsys_clk_regs,
755
749
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
756
750
.clk_name = "dout_fsys_bus",