Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: mediatek: mt8195: add MDP3 nodes
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
authored by
Moudy Ho
and committed by
AngeloGioacchino Del Regno
5710462a
52f4a10f
+392
+392
arch/arm64/boot/dts/mediatek/mt8195.dtsi
+392
arch/arm64/boot/dts/mediatek/mt8195.dtsi
···
1961
1961
#clock-cells = <1>;
1962
1962
};
1963
1963
1964
+
dma-controller@14001000 {
1965
+
compatible = "mediatek,mt8195-mdp3-rdma";
1966
+
reg = <0 0x14001000 0 0x1000>;
1967
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
1968
+
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
1969
+
<CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
1970
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1971
+
iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
1972
+
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
1973
+
mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
1974
+
<&gce1 13 CMDQ_THR_PRIO_1>,
1975
+
<&gce1 14 CMDQ_THR_PRIO_1>,
1976
+
<&gce1 21 CMDQ_THR_PRIO_1>,
1977
+
<&gce1 22 CMDQ_THR_PRIO_1>;
1978
+
#dma-cells = <1>;
1979
+
};
1980
+
1981
+
display@14002000 {
1982
+
compatible = "mediatek,mt8195-mdp3-fg";
1983
+
reg = <0 0x14002000 0 0x1000>;
1984
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
1985
+
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
1986
+
};
1987
+
1988
+
display@14003000 {
1989
+
compatible = "mediatek,mt8195-mdp3-stitch";
1990
+
reg = <0 0x14003000 0 0x1000>;
1991
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
1992
+
clocks = <&vppsys0 CLK_VPP0_STITCH>;
1993
+
};
1994
+
1995
+
display@14004000 {
1996
+
compatible = "mediatek,mt8195-mdp3-hdr";
1997
+
reg = <0 0x14004000 0 0x1000>;
1998
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
1999
+
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2000
+
};
2001
+
2002
+
display@14005000 {
2003
+
compatible = "mediatek,mt8195-mdp3-aal";
2004
+
reg = <0 0x14005000 0 0x1000>;
2005
+
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
2006
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2007
+
clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2008
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2009
+
};
2010
+
2011
+
display@14006000 {
2012
+
compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2013
+
reg = <0 0x14006000 0 0x1000>;
2014
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2015
+
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2016
+
<CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
2017
+
clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2018
+
};
2019
+
2020
+
display@14007000 {
2021
+
compatible = "mediatek,mt8195-mdp3-tdshp";
2022
+
reg = <0 0x14007000 0 0x1000>;
2023
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2024
+
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2025
+
};
2026
+
2027
+
display@14008000 {
2028
+
compatible = "mediatek,mt8195-mdp3-color";
2029
+
reg = <0 0x14008000 0 0x1000>;
2030
+
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2031
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2032
+
clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2033
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2034
+
};
2035
+
2036
+
display@14009000 {
2037
+
compatible = "mediatek,mt8195-mdp3-ovl";
2038
+
reg = <0 0x14009000 0 0x1000>;
2039
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2040
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2041
+
clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2042
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2043
+
iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
2044
+
};
2045
+
2046
+
display@1400a000 {
2047
+
compatible = "mediatek,mt8195-mdp3-padding";
2048
+
reg = <0 0x1400a000 0 0x1000>;
2049
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2050
+
clocks = <&vppsys0 CLK_VPP0_PADDING>;
2051
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2052
+
};
2053
+
2054
+
display@1400b000 {
2055
+
compatible = "mediatek,mt8195-mdp3-tcc";
2056
+
reg = <0 0x1400b000 0 0x1000>;
2057
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2058
+
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2059
+
};
2060
+
2061
+
dma-controller@1400c000 {
2062
+
compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2063
+
reg = <0 0x1400c000 0 0x1000>;
2064
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2065
+
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2066
+
<CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
2067
+
clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2068
+
iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
2069
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2070
+
#dma-cells = <1>;
2071
+
};
2072
+
1964
2073
mutex@1400f000 {
1965
2074
compatible = "mediatek,mt8195-vpp-mutex";
1966
2075
reg = <0 0x1400f000 0 0x1000>;
···
2215
2106
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2216
2107
clock-names = "apb", "smi", "gals";
2217
2108
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2109
+
};
2110
+
2111
+
display@14f06000 {
2112
+
compatible = "mediatek,mt8195-mdp3-split";
2113
+
reg = <0 0x14f06000 0 0x1000>;
2114
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2115
+
clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
2116
+
<&vppsys1 CLK_VPP1_HDMI_META>,
2117
+
<&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
2118
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2119
+
};
2120
+
2121
+
display@14f07000 {
2122
+
compatible = "mediatek,mt8195-mdp3-tcc";
2123
+
reg = <0 0x14f07000 0 0x1000>;
2124
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2125
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
2126
+
};
2127
+
2128
+
dma-controller@14f08000 {
2129
+
compatible = "mediatek,mt8195-mdp3-rdma";
2130
+
reg = <0 0x14f08000 0 0x1000>;
2131
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2132
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2133
+
<CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
2134
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
2135
+
iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
2136
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2137
+
#dma-cells = <1>;
2138
+
};
2139
+
2140
+
dma-controller@14f09000 {
2141
+
compatible = "mediatek,mt8195-mdp3-rdma";
2142
+
reg = <0 0x14f09000 0 0x1000>;
2143
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2144
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2145
+
<CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
2146
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
2147
+
iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
2148
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2149
+
#dma-cells = <1>;
2150
+
};
2151
+
2152
+
dma-controller@14f0a000 {
2153
+
compatible = "mediatek,mt8195-mdp3-rdma";
2154
+
reg = <0 0x14f0a000 0 0x1000>;
2155
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2156
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2157
+
<CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
2158
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
2159
+
iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
2160
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2161
+
#dma-cells = <1>;
2162
+
};
2163
+
2164
+
display@14f0b000 {
2165
+
compatible = "mediatek,mt8195-mdp3-fg";
2166
+
reg = <0 0x14f0b000 0 0x1000>;
2167
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2168
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
2169
+
};
2170
+
2171
+
display@14f0c000 {
2172
+
compatible = "mediatek,mt8195-mdp3-fg";
2173
+
reg = <0 0x14f0c000 0 0x1000>;
2174
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2175
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
2176
+
};
2177
+
2178
+
display@14f0d000 {
2179
+
compatible = "mediatek,mt8195-mdp3-fg";
2180
+
reg = <0 0x14f0d000 0 0x1000>;
2181
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2182
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
2183
+
};
2184
+
2185
+
display@14f0e000 {
2186
+
compatible = "mediatek,mt8195-mdp3-hdr";
2187
+
reg = <0 0x14f0e000 0 0x1000>;
2188
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2189
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
2190
+
};
2191
+
2192
+
display@14f0f000 {
2193
+
compatible = "mediatek,mt8195-mdp3-hdr";
2194
+
reg = <0 0x14f0f000 0 0x1000>;
2195
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2196
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
2197
+
};
2198
+
2199
+
display@14f10000 {
2200
+
compatible = "mediatek,mt8195-mdp3-hdr";
2201
+
reg = <0 0x14f10000 0 0x1000>;
2202
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2203
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
2204
+
};
2205
+
2206
+
display@14f11000 {
2207
+
compatible = "mediatek,mt8195-mdp3-aal";
2208
+
reg = <0 0x14f11000 0 0x1000>;
2209
+
interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
2210
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2211
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
2212
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2213
+
};
2214
+
2215
+
display@14f12000 {
2216
+
compatible = "mediatek,mt8195-mdp3-aal";
2217
+
reg = <0 0x14f12000 0 0x1000>;
2218
+
interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
2219
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2220
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
2221
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2222
+
};
2223
+
2224
+
display@14f13000 {
2225
+
compatible = "mediatek,mt8195-mdp3-aal";
2226
+
reg = <0 0x14f13000 0 0x1000>;
2227
+
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
2228
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2229
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
2230
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2231
+
};
2232
+
2233
+
display@14f14000 {
2234
+
compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2235
+
reg = <0 0x14f14000 0 0x1000>;
2236
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2237
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2238
+
<CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
2239
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
2240
+
};
2241
+
2242
+
display@14f15000 {
2243
+
compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2244
+
reg = <0 0x14f15000 0 0x1000>;
2245
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2246
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2247
+
<CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
2248
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
2249
+
};
2250
+
2251
+
display@14f16000 {
2252
+
compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2253
+
reg = <0 0x14f16000 0 0x1000>;
2254
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2255
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2256
+
<CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
2257
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
2258
+
};
2259
+
2260
+
display@14f17000 {
2261
+
compatible = "mediatek,mt8195-mdp3-tdshp";
2262
+
reg = <0 0x14f17000 0 0x1000>;
2263
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2264
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
2265
+
};
2266
+
2267
+
display@14f18000 {
2268
+
compatible = "mediatek,mt8195-mdp3-tdshp";
2269
+
reg = <0 0x14f18000 0 0x1000>;
2270
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2271
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
2272
+
};
2273
+
2274
+
display@14f19000 {
2275
+
compatible = "mediatek,mt8195-mdp3-tdshp";
2276
+
reg = <0 0x14f19000 0 0x1000>;
2277
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2278
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
2279
+
};
2280
+
2281
+
display@14f1a000 {
2282
+
compatible = "mediatek,mt8195-mdp3-merge";
2283
+
reg = <0 0x14f1a000 0 0x1000>;
2284
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2285
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
2286
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2287
+
};
2288
+
2289
+
display@14f1b000 {
2290
+
compatible = "mediatek,mt8195-mdp3-merge";
2291
+
reg = <0 0x14f1b000 0 0x1000>;
2292
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2293
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
2294
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2295
+
};
2296
+
2297
+
display@14f1c000 {
2298
+
compatible = "mediatek,mt8195-mdp3-color";
2299
+
reg = <0 0x14f1c000 0 0x1000>;
2300
+
interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
2301
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2302
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
2303
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2304
+
};
2305
+
2306
+
display@14f1d000 {
2307
+
compatible = "mediatek,mt8195-mdp3-color";
2308
+
reg = <0 0x14f1d000 0 0x1000>;
2309
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2310
+
interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
2311
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
2312
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2313
+
};
2314
+
2315
+
display@14f1e000 {
2316
+
compatible = "mediatek,mt8195-mdp3-color";
2317
+
reg = <0 0x14f1e000 0 0x1000>;
2318
+
interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
2319
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2320
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
2321
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2322
+
};
2323
+
2324
+
display@14f1f000 {
2325
+
compatible = "mediatek,mt8195-mdp3-ovl";
2326
+
reg = <0 0x14f1f000 0 0x1000>;
2327
+
interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
2328
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2329
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
2330
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2331
+
iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
2332
+
};
2333
+
2334
+
display@14f20000 {
2335
+
compatible = "mediatek,mt8195-mdp3-padding";
2336
+
reg = <0 0x14f20000 0 0x1000>;
2337
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2338
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
2339
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2340
+
};
2341
+
2342
+
display@14f21000 {
2343
+
compatible = "mediatek,mt8195-mdp3-padding";
2344
+
reg = <0 0x14f21000 0 0x1000>;
2345
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2346
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
2347
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2348
+
};
2349
+
2350
+
display@14f22000 {
2351
+
compatible = "mediatek,mt8195-mdp3-padding";
2352
+
reg = <0 0x14f22000 0 0x1000>;
2353
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2354
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
2355
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2356
+
};
2357
+
2358
+
dma-controller@14f23000 {
2359
+
compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2360
+
reg = <0 0x14f23000 0 0x1000>;
2361
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2362
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2363
+
<CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
2364
+
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
2365
+
iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
2366
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2367
+
#dma-cells = <1>;
2368
+
};
2369
+
2370
+
dma-controller@14f24000 {
2371
+
compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2372
+
reg = <0 0x14f24000 0 0x1000>;
2373
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2374
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2375
+
<CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
2376
+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
2377
+
iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
2378
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2379
+
#dma-cells = <1>;
2380
+
};
2381
+
2382
+
dma-controller@14f25000 {
2383
+
compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2384
+
reg = <0 0x14f25000 0 0x1000>;
2385
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2386
+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2387
+
<CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
2388
+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
2389
+
iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
2390
+
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2391
+
#dma-cells = <1>;
2218
2392
};
2219
2393
2220
2394
imgsys: clock-controller@15000000 {