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drm/i915/display: Add function to configure event for dc balance

Configure pipe dmc event for dc balance enable/disable.

--v2:
- Keeping function and removing unnecessary comments. (Jani, Nikula)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-18-mitulkumar.ajitkumar.golani@intel.com

authored by

Mitul Golani and committed by
Ankit Nautiyal 5786499a 192bc98c

+12
+8
drivers/gpu/drm/i915/display/intel_dmc.c
··· 859 859 dmc_id, num_handlers, event_id); 860 860 } 861 861 862 + void intel_dmc_configure_dc_balance_event(struct intel_display *display, 863 + enum pipe pipe, bool enable) 864 + { 865 + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 866 + 867 + dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); 868 + } 869 + 862 870 /** 863 871 * intel_dmc_block_pkgc() - block PKG C-state 864 872 * @display: display instance
+2
drivers/gpu/drm/i915/display/intel_dmc.h
··· 25 25 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state); 26 26 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 27 27 bool block); 28 + void intel_dmc_configure_dc_balance_event(struct intel_display *display, 29 + enum pipe pipe, bool enable); 28 30 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 29 31 enum pipe pipe, bool enable); 30 32 void intel_dmc_fini(struct intel_display *display);
+2
drivers/gpu/drm/i915/display/intel_vrr.c
··· 823 823 crtc_state->vrr.dc_balance.slope); 824 824 intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 825 825 crtc_state->vrr.dc_balance.vblank_target); 826 + intel_dmc_configure_dc_balance_event(display, pipe, true); 826 827 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 827 828 ADAPTIVE_SYNC_COUNTER_EN); 828 829 intel_pipedmc_dcb_enable(NULL, crtc); ··· 841 840 return; 842 841 843 842 intel_pipedmc_dcb_disable(NULL, crtc); 843 + intel_dmc_configure_dc_balance_event(display, pipe, false); 844 844 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); 845 845 intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); 846 846 intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);