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dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers

Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581
PCIe-PHY binding. This change is not introducing any backward compatibility
issue since the EN7581 dts is not upstream yet.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Lorenzo Bianconi and committed by
Vinod Koul 5854d0aa e245c725

+13 -2
+13 -2
Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
··· 21 21 - description: PCIE analog base address 22 22 - description: PCIE lane0 base address 23 23 - description: PCIE lane1 base address 24 + - description: PCIE lane0 detection time base address 25 + - description: PCIE lane1 detection time base address 26 + - description: PCIE Rx AEQ base address 24 27 25 28 reg-names: 26 29 items: 27 30 - const: csr-2l 28 31 - const: pma0 29 32 - const: pma1 33 + - const: p0-xr-dtime 34 + - const: p1-xr-dtime 35 + - const: rx-aeq 30 36 31 37 "#phy-cells": 32 38 const: 0 ··· 58 52 #phy-cells = <0>; 59 53 reg = <0x0 0x1fa5a000 0x0 0xfff>, 60 54 <0x0 0x1fa5b000 0x0 0xfff>, 61 - <0x0 0x1fa5c000 0x0 0xfff>; 62 - reg-names = "csr-2l", "pma0", "pma1"; 55 + <0x0 0x1fa5c000 0x0 0xfff>, 56 + <0x0 0x1fc10044 0x0 0x4>, 57 + <0x0 0x1fc30044 0x0 0x4>, 58 + <0x0 0x1fc15030 0x0 0x104>; 59 + reg-names = "csr-2l", "pma0", "pma1", 60 + "p0-xr-dtime", "p1-xr-dtime", 61 + "rx-aeq"; 63 62 }; 64 63 };