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clk: qcom: clk-rcg2: Update logic to calculate D value for RCG

The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.

Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org

authored by

Taniya Das and committed by
Bjorn Andersson 58922910 89f0f1a4

+11 -2
+11 -2
drivers/clk/qcom/clk-rcg2.c
··· 264 264 265 265 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 266 266 { 267 - u32 cfg, mask; 267 + u32 cfg, mask, d_val, not2d_val, n_minus_m; 268 268 struct clk_hw *hw = &rcg->clkr.hw; 269 269 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); 270 270 ··· 283 283 if (ret) 284 284 return ret; 285 285 286 + /* Calculate 2d value */ 287 + d_val = f->n; 288 + 289 + n_minus_m = f->n - f->m; 290 + n_minus_m *= 2; 291 + 292 + d_val = clamp_t(u32, d_val, f->m, n_minus_m); 293 + not2d_val = ~d_val & mask; 294 + 286 295 ret = regmap_update_bits(rcg->clkr.regmap, 287 - RCG_D_OFFSET(rcg), mask, ~f->n); 296 + RCG_D_OFFSET(rcg), mask, not2d_val); 288 297 if (ret) 289 298 return ret; 290 299 }