Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: smd: Add missing MSM8998 RPM clocks
Add missing RPM-provided clocks on msm8998 and reorder the definitions
where needed.
Tested-by: Jami Kettunen <jami.kettunen@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: Caleb Connolly <caleb@connolly.tech>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226214126.21209-3-konrad.dybcio@somainline.org
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
89f0f1a4
f804360b
+27
-13
+27
-13
drivers/clk/qcom/clk-smd-rpm.c
+27
-13
drivers/clk/qcom/clk-smd-rpm.c
···
816
816
.num_clks = ARRAY_SIZE(qcs404_clks),
817
817
};
818
818
819
-
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
820
-
3, 19200000);
819
+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
820
+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
821
821
DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
822
822
QCOM_SMD_RPM_AGGR_CLK, 1);
823
823
DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
824
824
QCOM_SMD_RPM_AGGR_CLK, 2);
825
825
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
826
826
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
827
+
827
828
static struct clk_smd_rpm *msm8998_clks[] = {
829
+
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
830
+
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
828
831
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
829
832
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
830
833
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
···
840
837
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
841
838
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
842
839
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
840
+
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
841
+
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
842
+
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
843
+
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
843
844
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
844
845
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
845
846
[RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
846
847
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
847
848
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
848
849
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
850
+
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
851
+
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
852
+
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
853
+
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
854
+
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
855
+
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
849
856
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
850
857
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
851
858
[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
···
868
855
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
869
856
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
870
857
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
871
-
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
872
-
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
858
+
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
859
+
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
873
860
[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
874
861
[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
862
+
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
863
+
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
864
+
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
865
+
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
875
866
[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
876
867
[RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
877
868
};
···
884
867
.clks = msm8998_clks,
885
868
.num_clks = ARRAY_SIZE(msm8998_clks),
886
869
};
887
-
888
-
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
889
-
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
890
870
891
871
static struct clk_smd_rpm *sdm660_clks[] = {
892
872
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
···
914
900
[RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
915
901
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
916
902
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
917
-
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
918
-
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
903
+
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
904
+
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
919
905
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
920
906
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
921
907
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
922
908
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
923
909
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
924
910
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
925
-
[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
926
-
[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
911
+
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
912
+
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
927
913
};
928
914
929
915
static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
···
1025
1011
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
1026
1012
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
1027
1013
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
1028
-
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
1029
-
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
1014
+
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
1015
+
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
1030
1016
[RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1031
1017
[RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1032
1018
[RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,