Merge tag 'v6.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

+15

Documentation/devicetree/bindings/arm/rockchip.yaml

··· 196 196 - const: firefly,rk3566-roc-pc 197 197 - const: rockchip,rk3566 198 198 199 + - description: Firefly Station P2 200 + items: 201 + - const: firefly,rk3568-roc-pc 202 + - const: rockchip,rk3568 203 + 199 204 - description: FriendlyElec NanoPi R2 series boards 200 205 items: 201 206 - enum: ··· 226 221 - friendlyarm,nanopi-r5c 227 222 - friendlyarm,nanopi-r5s 228 223 - const: rockchip,rk3568 224 + 225 + - description: FriendlyElec NanoPC T6 226 + items: 227 + - const: friendlyarm,nanopc-t6 228 + - const: rockchip,rk3588 229 229 230 230 - description: GeekBuying GeekBox 231 231 items: ··· 702 692 - description: Radxa ROCK 4C+ 703 693 items: 704 694 - const: radxa,rock-4c-plus 695 + - const: rockchip,rk3399 696 + 697 + - description: Radxa ROCK 4SE 698 + items: 699 + - const: radxa,rock-4se 705 700 - const: rockchip,rk3399 706 701 707 702 - description: Radxa ROCK Pi E

+3

Documentation/devicetree/bindings/eeprom/at24.yaml

··· 102 102 # These are special cases that don't conform to the above pattern. 103 103 # Each requires a standard at24 model as fallback. 104 104 - items: 105 + - const: belling,bl24c16a 106 + - const: atmel,24c16 107 + - items: 105 108 - enum: 106 109 - rohm,br24g01 107 110 - rohm,br24t01

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 190 190 description: Compass Electronics Group, LLC 191 191 "^beagle,.*": 192 192 description: BeagleBoard.org Foundation 193 + "^belling,.*": 194 + description: Shanghai Belling Co., Ltd. 193 195 "^bhf,.*": 194 196 description: Beckhoff Automation GmbH & Co. KG 195 197 "^bitmain,.*":

+3

arch/arm64/boot/dts/rockchip/Makefile

··· 58 58 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb 59 59 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb 60 60 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb 61 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4se.dtb 61 62 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb 62 63 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb 63 64 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb ··· 95 94 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb 96 95 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb 97 96 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb 97 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb 98 98 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb 99 99 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb 100 100 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb 101 101 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb 102 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb 102 103 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb 103 104 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb 104 105 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb

+1 -1

arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi

··· 26 26 }; 27 27 28 28 &vcc3v3_btreg { 29 - enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; 29 + enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; 30 30 };

+1 -1

arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts

··· 39 39 }; 40 40 41 41 &vcc3v3_btreg { 42 - enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; 42 + enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; 43 43 };

+1 -1

arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi

··· 250 250 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 251 251 252 252 enable-active-high; 253 - enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 253 + enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; 254 254 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 255 255 states = <1800000 0x1>, 256 256 <3000000 0x0>;

+65

arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com> 4 + * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com> 5 + */ 6 + 7 + /dts-v1/; 8 + #include "rk3399-rock-pi-4.dtsi" 9 + #include "rk3399-t-opp.dtsi" 10 + 11 + / { 12 + model = "Radxa ROCK 4SE"; 13 + compatible = "radxa,rock-4se", "rockchip,rk3399"; 14 + 15 + aliases { 16 + mmc2 = &sdio0; 17 + }; 18 + }; 19 + 20 + &pinctrl { 21 + usb2 { 22 + vcc5v0_host_en: vcc5v0-host-en { 23 + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 24 + }; 25 + }; 26 + }; 27 + 28 + &sdio0 { 29 + status = "okay"; 30 + 31 + brcmf: wifi@1 { 32 + compatible = "brcm,bcm4329-fmac"; 33 + reg = <1>; 34 + interrupt-parent = <&gpio0>; 35 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; 36 + interrupt-names = "host-wake"; 37 + pinctrl-names = "default"; 38 + pinctrl-0 = <&wifi_host_wake_l>; 39 + }; 40 + }; 41 + 42 + &uart0 { 43 + status = "okay"; 44 + 45 + bluetooth { 46 + compatible = "brcm,bcm4345c5"; 47 + clocks = <&rk808 1>; 48 + clock-names = "lpo"; 49 + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; 50 + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 51 + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; 52 + max-speed = <1500000>; 53 + pinctrl-names = "default"; 54 + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; 55 + vbat-supply = <&vcc3v3_sys>; 56 + vddio-supply = <&vcc_1v8>; 57 + }; 58 + }; 59 + 60 + &vcc5v0_host { 61 + enable-active-high; 62 + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; 63 + pinctrl-names = "default"; 64 + pinctrl-0 = <&vcc5v0_host_en>; 65 + };

-1

arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi

··· 9 9 #include <dt-bindings/leds/common.h> 10 10 #include <dt-bindings/pwm/pwm.h> 11 11 #include "rk3399.dtsi" 12 - #include "rk3399-opp.dtsi" 13 12 14 13 / { 15 14 aliases {

+11

arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts

··· 6 6 7 7 /dts-v1/; 8 8 #include "rk3399-rock-pi-4.dtsi" 9 + #include "rk3399-opp.dtsi" 9 10 10 11 / { 11 12 model = "Radxa ROCK Pi 4A"; 12 13 compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; 14 + }; 15 + 16 + &spi1 { 17 + status = "okay"; 18 + 19 + flash@0 { 20 + compatible = "jedec,spi-nor"; 21 + reg = <0>; 22 + spi-max-frequency = <10000000>; 23 + }; 13 24 };

+11

arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts

··· 6 6 7 7 /dts-v1/; 8 8 #include "rk3399-rock-pi-4.dtsi" 9 + #include "rk3399-opp.dtsi" 9 10 10 11 / { 11 12 model = "Radxa ROCK Pi 4B"; ··· 28 27 interrupt-names = "host-wake"; 29 28 pinctrl-names = "default"; 30 29 pinctrl-0 = <&wifi_host_wake_l>; 30 + }; 31 + }; 32 + 33 + &spi1 { 34 + status = "okay"; 35 + 36 + flash@0 { 37 + compatible = "jedec,spi-nor"; 38 + reg = <0>; 39 + spi-max-frequency = <10000000>; 31 40 }; 32 41 }; 33 42

+11

arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts

··· 7 7 8 8 /dts-v1/; 9 9 #include "rk3399-rock-pi-4.dtsi" 10 + #include "rk3399-opp.dtsi" 10 11 11 12 / { 12 13 model = "Radxa ROCK Pi 4C"; ··· 41 40 42 41 &sound { 43 42 hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; 43 + }; 44 + 45 + &spi1 { 46 + status = "okay"; 47 + 48 + flash@0 { 49 + compatible = "jedec,spi-nor"; 50 + reg = <0>; 51 + spi-max-frequency = <10000000>; 52 + }; 44 53 }; 45 54 46 55 &uart0 {

+27

arch/arm64/boot/dts/rockchip/rk3399.dtsi

··· 265 265 }; 266 266 }; 267 267 268 + pcie0_ep: pcie-ep@f8000000 { 269 + compatible = "rockchip,rk3399-pcie-ep"; 270 + reg = <0x0 0xfd000000 0x0 0x1000000>, 271 + <0x0 0xfa000000 0x0 0x2000000>; 272 + reg-names = "apb-base", "mem-base"; 273 + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 274 + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 275 + clock-names = "aclk", "aclk-perf", 276 + "hclk", "pm"; 277 + max-functions = /bits/ 8 <8>; 278 + num-lanes = <4>; 279 + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 280 + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 281 + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 282 + <&cru SRST_A_PCIE>; 283 + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 284 + "pm", "pclk", "aclk"; 285 + phys = <&pcie_phy 0>, <&pcie_phy 1>, 286 + <&pcie_phy 2>, <&pcie_phy 3>; 287 + phy-names = "pcie-phy-0", "pcie-phy-1", 288 + "pcie-phy-2", "pcie-phy-3"; 289 + rockchip,max-outbound-regions = <32>; 290 + pinctrl-names = "default"; 291 + pinctrl-0 = <&pcie_clkreqnb_cpm>; 292 + status = "disabled"; 293 + }; 294 + 268 295 gmac: ethernet@fe300000 { 269 296 compatible = "rockchip,rk3399-gmac"; 270 297 reg = <0x0 0xfe300000 0x0 0x10000>;

+16 -8

arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts

··· 47 47 vin-supply = <&vcc5v0_sys>; 48 48 }; 49 49 50 + /* actually fed by vcc5v0_sys, dependent 51 + * on pi6c clock generator 52 + */ 50 53 vcc3v3_minipcie: vcc3v3-minipcie-regulator { 51 54 compatible = "regulator-fixed"; 52 55 enable-active-high; ··· 57 54 pinctrl-names = "default"; 58 55 pinctrl-0 = <&minipcie_enable_h>; 59 56 regulator-name = "vcc3v3_minipcie"; 60 - regulator-min-microvolt = <5000000>; 61 - regulator-max-microvolt = <5000000>; 62 - vin-supply = <&vcc5v0_sys>; 57 + regulator-min-microvolt = <3300000>; 58 + regulator-max-microvolt = <3300000>; 59 + vin-supply = <&vcc3v3_pi6c_05>; 63 60 }; 64 61 65 62 vcc3v3_ngff: vcc3v3-ngff-regulator { ··· 74 71 vin-supply = <&vcc5v0_sys>; 75 72 }; 76 73 77 - /* actually fed by vcc5v0_sys, dependent 78 - * on pi6c clock generator 79 - */ 80 74 vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { 81 75 compatible = "regulator-fixed"; 82 76 enable-active-high; ··· 83 83 regulator-name = "vcc3v3_pcie30x1"; 84 84 regulator-min-microvolt = <3300000>; 85 85 regulator-max-microvolt = <3300000>; 86 - vin-supply = <&vcc3v3_pi6c_05>; 86 + vin-supply = <&vcc5v0_sys>; 87 87 }; 88 88 89 89 vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { ··· 97 97 regulator-max-microvolt = <3300000>; 98 98 vin-supply = <&vcc5v0_sys>; 99 99 }; 100 + }; 101 + 102 + &combphy1 { 103 + phy-supply = <&vcc3v3_pcie30x1>; 100 104 }; 101 105 102 106 &pcie2x1 { ··· 121 117 pinctrl-names = "default"; 122 118 pinctrl-0 = <&pcie30x1m0_pins>; 123 119 reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; 124 - vpcie3v3-supply = <&vcc3v3_pcie30x1>; 120 + vpcie3v3-supply = <&vcc3v3_minipcie>; 125 121 status = "okay"; 126 122 }; 127 123 ··· 179 175 &pwm12 { 180 176 pinctrl-names = "default"; 181 177 pinctrl-0 = <&pwm12m1_pins>; 178 + status = "okay"; 179 + }; 180 + 181 + &sata1 { 182 182 status = "okay"; 183 183 }; 184 184

+643

arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include <dt-bindings/gpio/gpio.h> 9 + #include <dt-bindings/pinctrl/rockchip.h> 10 + #include <dt-bindings/soc/rockchip,vop2.h> 11 + #include "rk3568.dtsi" 12 + 13 + / { 14 + model = "Firefly Station P2"; 15 + compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568"; 16 + 17 + aliases { 18 + ethernet0 = &gmac0; 19 + ethernet1 = &gmac1; 20 + mmc0 = &sdmmc0; 21 + mmc1 = &sdhci; 22 + }; 23 + 24 + chosen: chosen { 25 + stdout-path = "serial2:1500000n8"; 26 + }; 27 + 28 + dc_12v: dc-12v-regulator { 29 + compatible = "regulator-fixed"; 30 + regulator-name = "dc_12v"; 31 + regulator-always-on; 32 + regulator-boot-on; 33 + regulator-min-microvolt = <12000000>; 34 + regulator-max-microvolt = <12000000>; 35 + }; 36 + 37 + gmac0_clkin: external-gmac0-clock { 38 + compatible = "fixed-clock"; 39 + clock-frequency = <125000000>; 40 + clock-output-names = "gmac0_clkin"; 41 + #clock-cells = <0>; 42 + }; 43 + 44 + gmac1_clkin: external-gmac1-clock { 45 + compatible = "fixed-clock"; 46 + clock-frequency = <125000000>; 47 + clock-output-names = "gmac1_clkin"; 48 + #clock-cells = <0>; 49 + }; 50 + 51 + leds { 52 + compatible = "gpio-leds"; 53 + 54 + led-user { 55 + label = "user-led"; 56 + default-state = "on"; 57 + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 58 + linux,default-trigger = "heartbeat"; 59 + pinctrl-names = "default"; 60 + pinctrl-0 = <&user_led_enable_h>; 61 + retain-state-suspended; 62 + }; 63 + }; 64 + 65 + hdmi-con { 66 + compatible = "hdmi-connector"; 67 + type = "a"; 68 + 69 + port { 70 + hdmi_con_in: endpoint { 71 + remote-endpoint = <&hdmi_out_con>; 72 + }; 73 + }; 74 + }; 75 + 76 + pcie30_avdd0v9: pcie30-avdd0v9-regulator { 77 + compatible = "regulator-fixed"; 78 + regulator-name = "pcie30_avdd0v9"; 79 + regulator-always-on; 80 + regulator-boot-on; 81 + regulator-min-microvolt = <900000>; 82 + regulator-max-microvolt = <900000>; 83 + vin-supply = <&vcc3v3_sys>; 84 + }; 85 + 86 + pcie30_avdd1v8: pcie30-avdd1v8-regulator { 87 + compatible = "regulator-fixed"; 88 + regulator-name = "pcie30_avdd1v8"; 89 + regulator-always-on; 90 + regulator-boot-on; 91 + regulator-min-microvolt = <1800000>; 92 + regulator-max-microvolt = <1800000>; 93 + vin-supply = <&vcc3v3_sys>; 94 + }; 95 + 96 + vcc3v3_sys: vcc3v3-sys-regulator { 97 + compatible = "regulator-fixed"; 98 + regulator-name = "vcc3v3_sys"; 99 + regulator-always-on; 100 + regulator-boot-on; 101 + regulator-min-microvolt = <3300000>; 102 + regulator-max-microvolt = <3300000>; 103 + vin-supply = <&dc_12v>; 104 + }; 105 + 106 + vcc3v3_pcie: vcc3v3-pcie-regulator { 107 + compatible = "regulator-fixed"; 108 + regulator-name = "vcc3v3_pcie"; 109 + enable-active-high; 110 + regulator-min-microvolt = <3300000>; 111 + regulator-max-microvolt = <3300000>; 112 + pinctrl-names = "default"; 113 + pinctrl-0 = <&vcc3v3_pcie_en_pin>; 114 + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 115 + startup-delay-us = <5000>; 116 + vin-supply = <&vcc5v0_sys>; 117 + }; 118 + 119 + vcc5v0_sys: vcc5v0-sys-regulator { 120 + compatible = "regulator-fixed"; 121 + regulator-name = "vcc5v0_sys"; 122 + regulator-always-on; 123 + regulator-boot-on; 124 + regulator-min-microvolt = <5000000>; 125 + regulator-max-microvolt = <5000000>; 126 + vin-supply = <&dc_12v>; 127 + }; 128 + 129 + vcc5v0_usb: vcc5v0-usb-regulator { 130 + compatible = "regulator-fixed"; 131 + regulator-name = "vcc5v0_usb"; 132 + regulator-always-on; 133 + regulator-boot-on; 134 + regulator-min-microvolt = <5000000>; 135 + regulator-max-microvolt = <5000000>; 136 + vin-supply = <&vcc5v0_sys>; 137 + }; 138 + 139 + vcc5v0_host: vcc5v0-host-regulator { 140 + compatible = "regulator-fixed"; 141 + regulator-name = "vcc5v0_host"; 142 + enable-active-high; 143 + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 144 + pinctrl-names = "default"; 145 + pinctrl-0 = <&vcc5v0_host_en>; 146 + regulator-always-on; 147 + vin-supply = <&vcc5v0_usb>; 148 + }; 149 + 150 + vcc5v0_otg: vcc5v0-otg-regulator { 151 + compatible = "regulator-fixed"; 152 + regulator-name = "vcc5v0_otg"; 153 + enable-active-high; 154 + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 155 + pinctrl-names = "default"; 156 + pinctrl-0 = <&vcc5v0_otg_en>; 157 + vin-supply = <&vcc5v0_usb>; 158 + }; 159 + }; 160 + 161 + &combphy0 { 162 + /* used for USB3 */ 163 + status = "okay"; 164 + }; 165 + 166 + &combphy1 { 167 + /* used for USB3 */ 168 + status = "okay"; 169 + }; 170 + 171 + &combphy2 { 172 + /* used for SATA */ 173 + status = "okay"; 174 + }; 175 + 176 + &gmac0 { 177 + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 178 + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; 179 + clock_in_out = "input"; 180 + pinctrl-names = "default"; 181 + pinctrl-0 = <&gmac0_miim 182 + &gmac0_tx_bus2 183 + &gmac0_rx_bus2 184 + &gmac0_rgmii_clk 185 + &gmac0_rgmii_bus 186 + &gmac0_clkinout>; 187 + phy-handle = <&rgmii_phy0>; 188 + phy-mode = "rgmii"; 189 + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 190 + snps,reset-active-low; 191 + /* Reset time is 20ms, 100ms for rtl8211f */ 192 + snps,reset-delays-us = <0 20000 100000>; 193 + tx_delay = <0x3c>; 194 + rx_delay = <0x2f>; 195 + status = "okay"; 196 + }; 197 + 198 + &gmac1 { 199 + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 200 + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; 201 + clock_in_out = "input"; 202 + pinctrl-names = "default"; 203 + pinctrl-0 = <&gmac1m1_miim 204 + &gmac1m1_tx_bus2 205 + &gmac1m1_rx_bus2 206 + &gmac1m1_rgmii_clk 207 + &gmac1m1_rgmii_bus 208 + &gmac1m1_clkinout>; 209 + phy-handle = <&rgmii_phy1>; 210 + phy-mode = "rgmii"; 211 + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 212 + snps,reset-active-low; 213 + /* Reset time is 20ms, 100ms for rtl8211f */ 214 + snps,reset-delays-us = <0 20000 100000>; 215 + tx_delay = <0x4f>; 216 + rx_delay = <0x26>; 217 + status = "okay"; 218 + }; 219 + 220 + &gpu { 221 + mali-supply = <&vdd_gpu>; 222 + status = "okay"; 223 + }; 224 + 225 + &hdmi { 226 + avdd-0v9-supply = <&vdda0v9_image>; 227 + avdd-1v8-supply = <&vcca1v8_image>; 228 + status = "okay"; 229 + }; 230 + 231 + &hdmi_in { 232 + hdmi_in_vp0: endpoint { 233 + remote-endpoint = <&vp0_out_hdmi>; 234 + }; 235 + }; 236 + 237 + &hdmi_out { 238 + hdmi_out_con: endpoint { 239 + remote-endpoint = <&hdmi_con_in>; 240 + }; 241 + }; 242 + 243 + &hdmi_sound { 244 + status = "okay"; 245 + }; 246 + 247 + &i2c0 { 248 + status = "okay"; 249 + 250 + rk809: pmic@20 { 251 + compatible = "rockchip,rk809"; 252 + reg = <0x20>; 253 + interrupt-parent = <&gpio0>; 254 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 255 + #clock-cells = <1>; 256 + pinctrl-names = "default"; 257 + pinctrl-0 = <&pmic_int>; 258 + rockchip,system-power-controller; 259 + vcc1-supply = <&vcc3v3_sys>; 260 + vcc2-supply = <&vcc3v3_sys>; 261 + vcc3-supply = <&vcc3v3_sys>; 262 + vcc4-supply = <&vcc3v3_sys>; 263 + vcc5-supply = <&vcc3v3_sys>; 264 + vcc6-supply = <&vcc3v3_sys>; 265 + vcc7-supply = <&vcc3v3_sys>; 266 + vcc8-supply = <&vcc3v3_sys>; 267 + vcc9-supply = <&vcc3v3_sys>; 268 + wakeup-source; 269 + 270 + regulators { 271 + vdd_logic: DCDC_REG1 { 272 + regulator-name = "vdd_logic"; 273 + regulator-always-on; 274 + regulator-boot-on; 275 + regulator-init-microvolt = <900000>; 276 + regulator-initial-mode = <0x2>; 277 + regulator-min-microvolt = <500000>; 278 + regulator-max-microvolt = <1350000>; 279 + regulator-ramp-delay = <6001>; 280 + 281 + regulator-state-mem { 282 + regulator-off-in-suspend; 283 + }; 284 + }; 285 + 286 + vdd_gpu: DCDC_REG2 { 287 + regulator-name = "vdd_gpu"; 288 + regulator-init-microvolt = <900000>; 289 + regulator-initial-mode = <0x2>; 290 + regulator-min-microvolt = <500000>; 291 + regulator-max-microvolt = <1350000>; 292 + regulator-ramp-delay = <6001>; 293 + 294 + regulator-state-mem { 295 + regulator-off-in-suspend; 296 + }; 297 + }; 298 + 299 + vcc_ddr: DCDC_REG3 { 300 + regulator-name = "vcc_ddr"; 301 + regulator-always-on; 302 + regulator-boot-on; 303 + regulator-initial-mode = <0x2>; 304 + 305 + regulator-state-mem { 306 + regulator-on-in-suspend; 307 + }; 308 + }; 309 + 310 + vdd_npu: DCDC_REG4 { 311 + regulator-name = "vdd_npu"; 312 + regulator-init-microvolt = <900000>; 313 + regulator-initial-mode = <0x2>; 314 + regulator-min-microvolt = <500000>; 315 + regulator-max-microvolt = <1350000>; 316 + regulator-ramp-delay = <6001>; 317 + 318 + regulator-state-mem { 319 + regulator-off-in-suspend; 320 + }; 321 + }; 322 + 323 + vcc_1v8: DCDC_REG5 { 324 + regulator-name = "vcc_1v8"; 325 + regulator-always-on; 326 + regulator-boot-on; 327 + regulator-min-microvolt = <1800000>; 328 + regulator-max-microvolt = <1800000>; 329 + 330 + regulator-state-mem { 331 + regulator-off-in-suspend; 332 + }; 333 + }; 334 + 335 + vdda0v9_image: LDO_REG1 { 336 + regulator-name = "vdda0v9_image"; 337 + regulator-min-microvolt = <900000>; 338 + regulator-max-microvolt = <900000>; 339 + 340 + regulator-state-mem { 341 + regulator-off-in-suspend; 342 + }; 343 + }; 344 + 345 + vdda_0v9: LDO_REG2 { 346 + regulator-name = "vdda_0v9"; 347 + regulator-always-on; 348 + regulator-boot-on; 349 + regulator-min-microvolt = <900000>; 350 + regulator-max-microvolt = <900000>; 351 + 352 + regulator-state-mem { 353 + regulator-off-in-suspend; 354 + }; 355 + }; 356 + 357 + vdda0v9_pmu: LDO_REG3 { 358 + regulator-name = "vdda0v9_pmu"; 359 + regulator-always-on; 360 + regulator-boot-on; 361 + regulator-min-microvolt = <900000>; 362 + regulator-max-microvolt = <900000>; 363 + 364 + regulator-state-mem { 365 + regulator-on-in-suspend; 366 + regulator-suspend-microvolt = <900000>; 367 + }; 368 + }; 369 + 370 + vccio_acodec: LDO_REG4 { 371 + regulator-name = "vccio_acodec"; 372 + regulator-min-microvolt = <3300000>; 373 + regulator-max-microvolt = <3300000>; 374 + 375 + regulator-state-mem { 376 + regulator-off-in-suspend; 377 + }; 378 + }; 379 + 380 + vccio_sd: LDO_REG5 { 381 + regulator-name = "vccio_sd"; 382 + regulator-min-microvolt = <1800000>; 383 + regulator-max-microvolt = <3300000>; 384 + 385 + regulator-state-mem { 386 + regulator-off-in-suspend; 387 + }; 388 + }; 389 + 390 + vcc3v3_pmu: LDO_REG6 { 391 + regulator-name = "vcc3v3_pmu"; 392 + regulator-always-on; 393 + regulator-boot-on; 394 + regulator-min-microvolt = <3300000>; 395 + regulator-max-microvolt = <3300000>; 396 + 397 + regulator-state-mem { 398 + regulator-on-in-suspend; 399 + regulator-suspend-microvolt = <3300000>; 400 + }; 401 + }; 402 + 403 + vcca_1v8: LDO_REG7 { 404 + regulator-name = "vcca_1v8"; 405 + regulator-always-on; 406 + regulator-boot-on; 407 + regulator-min-microvolt = <1800000>; 408 + regulator-max-microvolt = <1800000>; 409 + 410 + regulator-state-mem { 411 + regulator-off-in-suspend; 412 + }; 413 + }; 414 + 415 + vcca1v8_pmu: LDO_REG8 { 416 + regulator-name = "vcca1v8_pmu"; 417 + regulator-always-on; 418 + regulator-boot-on; 419 + regulator-min-microvolt = <1800000>; 420 + regulator-max-microvolt = <1800000>; 421 + 422 + regulator-state-mem { 423 + regulator-on-in-suspend; 424 + regulator-suspend-microvolt = <1800000>; 425 + }; 426 + }; 427 + 428 + vcca1v8_image: LDO_REG9 { 429 + regulator-name = "vcca1v8_image"; 430 + regulator-min-microvolt = <1800000>; 431 + regulator-max-microvolt = <1800000>; 432 + 433 + regulator-state-mem { 434 + regulator-off-in-suspend; 435 + }; 436 + }; 437 + 438 + vcc_3v3: SWITCH_REG1 { 439 + regulator-name = "vcc_3v3"; 440 + regulator-always-on; 441 + regulator-boot-on; 442 + 443 + regulator-state-mem { 444 + regulator-off-in-suspend; 445 + }; 446 + }; 447 + 448 + vcc3v3_sd: SWITCH_REG2 { 449 + regulator-name = "vcc3v3_sd"; 450 + regulator-always-on; 451 + regulator-boot-on; 452 + 453 + regulator-state-mem { 454 + regulator-off-in-suspend; 455 + }; 456 + }; 457 + }; 458 + }; 459 + }; 460 + 461 + &i2s0_8ch { 462 + status = "okay"; 463 + }; 464 + 465 + &mdio0 { 466 + rgmii_phy0: phy@0 { 467 + compatible = "ethernet-phy-ieee802.3-c22"; 468 + reg = <0x0>; 469 + }; 470 + }; 471 + 472 + &mdio1 { 473 + rgmii_phy1: phy@0 { 474 + compatible = "ethernet-phy-ieee802.3-c22"; 475 + reg = <0x0>; 476 + }; 477 + }; 478 + 479 + &pcie30phy { 480 + status = "okay"; 481 + }; 482 + 483 + &pcie3x2 { 484 + pinctrl-names = "default"; 485 + pinctrl-0 = <&pcie_reset_pin>; 486 + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 487 + vpcie3v3-supply = <&vcc3v3_pcie>; 488 + status = "okay"; 489 + }; 490 + 491 + &pinctrl { 492 + leds { 493 + user_led_enable_h: user-led-enable-h { 494 + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 495 + }; 496 + }; 497 + 498 + usb { 499 + vcc5v0_host_en: vcc5v0-host-en { 500 + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 501 + }; 502 + 503 + vcc5v0_otg_en: vcc5v0-otg-en { 504 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 505 + }; 506 + }; 507 + 508 + pcie { 509 + pcie_reset_pin: pcie-reset-pin { 510 + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 511 + }; 512 + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { 513 + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 514 + }; 515 + }; 516 + 517 + pmic { 518 + pmic_int: pmic-int { 519 + rockchip,pins = 520 + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 521 + }; 522 + }; 523 + }; 524 + 525 + &pmu_io_domains { 526 + pmuio1-supply = <&vcc3v3_pmu>; 527 + pmuio2-supply = <&vcc3v3_pmu>; 528 + vccio1-supply = <&vccio_acodec>; 529 + vccio2-supply = <&vcc_1v8>; 530 + vccio3-supply = <&vccio_sd>; 531 + vccio4-supply = <&vcc_1v8>; 532 + vccio5-supply = <&vcc_3v3>; 533 + vccio6-supply = <&vcc_1v8>; 534 + vccio7-supply = <&vcc_3v3>; 535 + status = "okay"; 536 + }; 537 + 538 + &saradc { 539 + vref-supply = <&vcca_1v8>; 540 + status = "okay"; 541 + }; 542 + 543 + &sata2 { 544 + status = "okay"; 545 + }; 546 + 547 + &sdhci { 548 + bus-width = <8>; 549 + max-frequency = <200000000>; 550 + non-removable; 551 + pinctrl-names = "default"; 552 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 553 + status = "okay"; 554 + }; 555 + 556 + &sdmmc0 { 557 + bus-width = <4>; 558 + cap-sd-highspeed; 559 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 560 + disable-wp; 561 + pinctrl-names = "default"; 562 + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 563 + sd-uhs-sdr104; 564 + vmmc-supply = <&vcc3v3_sd>; 565 + vqmmc-supply = <&vccio_sd>; 566 + status = "okay"; 567 + }; 568 + 569 + &tsadc { 570 + status = "okay"; 571 + }; 572 + 573 + &uart2 { 574 + status = "okay"; 575 + }; 576 + 577 + &usb2phy0_host { 578 + phy-supply = <&vcc5v0_host>; 579 + status = "okay"; 580 + }; 581 + 582 + &usb2phy0 { 583 + status = "okay"; 584 + }; 585 + 586 + &usb2phy1 { 587 + status = "okay"; 588 + }; 589 + 590 + &usb2phy0_otg { 591 + status = "okay"; 592 + }; 593 + 594 + &usb2phy1_host { 595 + phy-supply = <&vcc5v0_host>; 596 + status = "okay"; 597 + }; 598 + 599 + &usb2phy1_otg { 600 + phy-supply = <&vcc5v0_host>; 601 + status = "okay"; 602 + }; 603 + 604 + &usb_host0_ehci { 605 + status = "okay"; 606 + }; 607 + 608 + &usb_host0_ohci { 609 + status = "okay"; 610 + }; 611 + 612 + &usb_host1_ehci { 613 + status = "okay"; 614 + }; 615 + 616 + &usb_host1_ohci { 617 + status = "okay"; 618 + }; 619 + 620 + &usb_host0_xhci { 621 + status = "okay"; 622 + }; 623 + 624 + &usb_host1_xhci { 625 + status = "okay"; 626 + }; 627 + 628 + &vp0 { 629 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 630 + reg = <ROCKCHIP_VOP2_EP_HDMI0>; 631 + remote-endpoint = <&hdmi_in_vp0>; 632 + }; 633 + }; 634 + 635 + &vop { 636 + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 637 + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 638 + status = "okay"; 639 + }; 640 + 641 + &vop_mmu { 642 + status = "okay"; 643 + };

-1

arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi

··· 25 25 no-sdio; 26 26 no-sd; 27 27 non-removable; 28 - max-frequency = <200000000>; 29 28 mmc-hs400-1_8v; 30 29 mmc-hs400-enhanced-strobe; 31 30 status = "okay";

+66

arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts

··· 21 21 }; 22 22 }; 23 23 24 + &combphy0_ps { 25 + status = "okay"; 26 + }; 27 + 28 + &i2c6 { 29 + status = "okay"; 30 + 31 + hym8563: rtc@51 { 32 + compatible = "haoyu,hym8563"; 33 + reg = <0x51>; 34 + interrupt-parent = <&gpio0>; 35 + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 36 + #clock-cells = <0>; 37 + clock-output-names = "hym8563"; 38 + pinctrl-names = "default"; 39 + pinctrl-0 = <&hym8563_int>; 40 + wakeup-source; 41 + }; 42 + }; 43 + 44 + &pinctrl { 45 + hym8563 { 46 + hym8563_int: hym8563-int { 47 + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 48 + }; 49 + }; 50 + }; 51 + 52 + /* FAN */ 53 + &pwm2 { 54 + pinctrl-0 = <&pwm2m1_pins>; 55 + pinctrl-names = "default"; 56 + status = "okay"; 57 + }; 58 + 59 + &sata0 { 60 + status = "okay"; 61 + }; 62 + 63 + &sdmmc { 64 + bus-width = <4>; 65 + cap-mmc-highspeed; 66 + cap-sd-highspeed; 67 + disable-wp; 68 + no-sdio; 69 + no-mmc; 70 + sd-uhs-sdr104; 71 + vmmc-supply = <&vcc_3v3_s3>; 72 + vqmmc-supply = <&vccio_sd_s0>; 73 + status = "okay"; 74 + }; 75 + 24 76 &uart2 { 25 77 pinctrl-0 = <&uart2m0_xfer>; 78 + status = "okay"; 79 + }; 80 + 81 + /* RS232 */ 82 + &uart6 { 83 + pinctrl-0 = <&uart6m0_xfer>; 84 + pinctrl-names = "default"; 85 + status = "okay"; 86 + }; 87 + 88 + /* RS485 */ 89 + &uart7 { 90 + pinctrl-0 = <&uart7m2_xfer>; 91 + pinctrl-names = "default"; 26 92 status = "okay"; 27 93 };

+358 -1

arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi

··· 18 18 regulator-min-microvolt = <12000000>; 19 19 regulator-max-microvolt = <12000000>; 20 20 }; 21 + 22 + vcc5v0_sys: vcc5v0-sys-regulator { 23 + compatible = "regulator-fixed"; 24 + regulator-name = "vcc5v0_sys"; 25 + regulator-always-on; 26 + regulator-boot-on; 27 + regulator-min-microvolt = <5000000>; 28 + regulator-max-microvolt = <5000000>; 29 + vin-supply = <&vcc12v_dcin>; 30 + }; 31 + 32 + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { 33 + compatible = "regulator-fixed"; 34 + regulator-name = "vcc_1v1_nldo_s3"; 35 + regulator-always-on; 36 + regulator-boot-on; 37 + regulator-min-microvolt = <1100000>; 38 + regulator-max-microvolt = <1100000>; 39 + vin-supply = <&vcc5v0_sys>; 40 + }; 41 + }; 42 + 43 + &cpu_l0 { 44 + cpu-supply = <&vdd_cpu_lit_s0>; 45 + }; 46 + 47 + &cpu_l1 { 48 + cpu-supply = <&vdd_cpu_lit_s0>; 49 + }; 50 + 51 + &cpu_l2 { 52 + cpu-supply = <&vdd_cpu_lit_s0>; 53 + }; 54 + 55 + &cpu_l3 { 56 + cpu-supply = <&vdd_cpu_lit_s0>; 21 57 }; 22 58 23 59 &sdhci { ··· 61 25 no-sdio; 62 26 no-sd; 63 27 non-removable; 64 - max-frequency = <200000000>; 65 28 mmc-hs400-1_8v; 66 29 mmc-hs400-enhanced-strobe; 67 30 status = "okay"; 31 + }; 32 + 33 + &spi2 { 34 + status = "okay"; 35 + assigned-clocks = <&cru CLK_SPI2>; 36 + assigned-clock-rates = <200000000>; 37 + num-cs = <1>; 38 + pinctrl-names = "default"; 39 + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 40 + 41 + pmic@0 { 42 + compatible = "rockchip,rk806"; 43 + spi-max-frequency = <1000000>; 44 + reg = <0x0>; 45 + interrupt-parent = <&gpio0>; 46 + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; 47 + pinctrl-names = "default"; 48 + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 49 + <&rk806_dvs2_null>, <&rk806_dvs3_null>; 50 + 51 + vcc1-supply = <&vcc5v0_sys>; 52 + vcc2-supply = <&vcc5v0_sys>; 53 + vcc3-supply = <&vcc5v0_sys>; 54 + vcc4-supply = <&vcc5v0_sys>; 55 + vcc5-supply = <&vcc5v0_sys>; 56 + vcc6-supply = <&vcc5v0_sys>; 57 + vcc7-supply = <&vcc5v0_sys>; 58 + vcc8-supply = <&vcc5v0_sys>; 59 + vcc9-supply = <&vcc5v0_sys>; 60 + vcc10-supply = <&vcc5v0_sys>; 61 + vcc11-supply = <&vcc_2v0_pldo_s3>; 62 + vcc12-supply = <&vcc5v0_sys>; 63 + vcc13-supply = <&vcc_1v1_nldo_s3>; 64 + vcc14-supply = <&vcc_1v1_nldo_s3>; 65 + vcca-supply = <&vcc5v0_sys>; 66 + 67 + gpio-controller; 68 + #gpio-cells = <2>; 69 + 70 + rk806_dvs1_null: dvs1-null-pins { 71 + pins = "gpio_pwrctrl2"; 72 + function = "pin_fun0"; 73 + }; 74 + 75 + rk806_dvs2_null: dvs2-null-pins { 76 + pins = "gpio_pwrctrl2"; 77 + function = "pin_fun0"; 78 + }; 79 + 80 + rk806_dvs3_null: dvs3-null-pins { 81 + pins = "gpio_pwrctrl3"; 82 + function = "pin_fun0"; 83 + }; 84 + 85 + regulators { 86 + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { 87 + regulator-name = "vdd_gpu_s0"; 88 + regulator-boot-on; 89 + regulator-min-microvolt = <550000>; 90 + regulator-max-microvolt = <950000>; 91 + regulator-ramp-delay = <12500>; 92 + regulator-enable-ramp-delay = <400>; 93 + 94 + regulator-state-mem { 95 + regulator-off-in-suspend; 96 + }; 97 + }; 98 + 99 + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { 100 + regulator-name = "vdd_cpu_lit_s0"; 101 + regulator-always-on; 102 + regulator-boot-on; 103 + regulator-min-microvolt = <550000>; 104 + regulator-max-microvolt = <950000>; 105 + regulator-ramp-delay = <12500>; 106 + 107 + regulator-state-mem { 108 + regulator-off-in-suspend; 109 + }; 110 + }; 111 + 112 + vdd_log_s0: dcdc-reg3 { 113 + regulator-name = "vdd_log_s0"; 114 + regulator-always-on; 115 + regulator-boot-on; 116 + regulator-min-microvolt = <675000>; 117 + regulator-max-microvolt = <750000>; 118 + regulator-ramp-delay = <12500>; 119 + 120 + regulator-state-mem { 121 + regulator-off-in-suspend; 122 + regulator-suspend-microvolt = <750000>; 123 + }; 124 + }; 125 + 126 + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { 127 + regulator-name = "vdd_vdenc_s0"; 128 + regulator-always-on; 129 + regulator-boot-on; 130 + regulator-min-microvolt = <550000>; 131 + regulator-max-microvolt = <950000>; 132 + regulator-init-microvolt = <750000>; 133 + regulator-ramp-delay = <12500>; 134 + 135 + regulator-state-mem { 136 + regulator-off-in-suspend; 137 + }; 138 + }; 139 + 140 + vdd_ddr_s0: dcdc-reg5 { 141 + regulator-name = "vdd_ddr_s0"; 142 + regulator-always-on; 143 + regulator-boot-on; 144 + regulator-min-microvolt = <675000>; 145 + regulator-max-microvolt = <900000>; 146 + regulator-ramp-delay = <12500>; 147 + 148 + regulator-state-mem { 149 + regulator-off-in-suspend; 150 + regulator-suspend-microvolt = <850000>; 151 + }; 152 + }; 153 + 154 + vdd2_ddr_s3: dcdc-reg6 { 155 + regulator-name = "vdd2_ddr_s3"; 156 + regulator-always-on; 157 + regulator-boot-on; 158 + 159 + regulator-state-mem { 160 + regulator-on-in-suspend; 161 + }; 162 + }; 163 + 164 + vcc_2v0_pldo_s3: dcdc-reg7 { 165 + regulator-name = "vdd_2v0_pldo_s3"; 166 + regulator-always-on; 167 + regulator-boot-on; 168 + regulator-min-microvolt = <2000000>; 169 + regulator-max-microvolt = <2000000>; 170 + regulator-ramp-delay = <12500>; 171 + 172 + regulator-state-mem { 173 + regulator-on-in-suspend; 174 + regulator-suspend-microvolt = <2000000>; 175 + }; 176 + }; 177 + 178 + vcc_3v3_s3: dcdc-reg8 { 179 + regulator-name = "vcc_3v3_s3"; 180 + regulator-always-on; 181 + regulator-boot-on; 182 + regulator-min-microvolt = <3300000>; 183 + regulator-max-microvolt = <3300000>; 184 + 185 + regulator-state-mem { 186 + regulator-on-in-suspend; 187 + regulator-suspend-microvolt = <3300000>; 188 + }; 189 + }; 190 + 191 + vddq_ddr_s0: dcdc-reg9 { 192 + regulator-name = "vddq_ddr_s0"; 193 + regulator-always-on; 194 + regulator-boot-on; 195 + 196 + regulator-state-mem { 197 + regulator-off-in-suspend; 198 + }; 199 + }; 200 + 201 + vcc_1v8_s3: dcdc-reg10 { 202 + regulator-name = "vcc_1v8_s3"; 203 + regulator-always-on; 204 + regulator-boot-on; 205 + regulator-min-microvolt = <1800000>; 206 + regulator-max-microvolt = <1800000>; 207 + 208 + regulator-state-mem { 209 + regulator-on-in-suspend; 210 + regulator-suspend-microvolt = <1800000>; 211 + }; 212 + }; 213 + 214 + avcc_1v8_s0: pldo-reg1 { 215 + regulator-name = "avcc_1v8_s0"; 216 + regulator-always-on; 217 + regulator-boot-on; 218 + regulator-min-microvolt = <1800000>; 219 + regulator-max-microvolt = <1800000>; 220 + 221 + regulator-state-mem { 222 + regulator-off-in-suspend; 223 + }; 224 + }; 225 + 226 + vcc_1v8_s0: pldo-reg2 { 227 + regulator-name = "vcc_1v8_s0"; 228 + regulator-always-on; 229 + regulator-boot-on; 230 + regulator-min-microvolt = <1800000>; 231 + regulator-max-microvolt = <1800000>; 232 + 233 + regulator-state-mem { 234 + regulator-off-in-suspend; 235 + regulator-suspend-microvolt = <1800000>; 236 + }; 237 + }; 238 + 239 + avdd_1v2_s0: pldo-reg3 { 240 + regulator-name = "avdd_1v2_s0"; 241 + regulator-always-on; 242 + regulator-boot-on; 243 + regulator-min-microvolt = <1200000>; 244 + regulator-max-microvolt = <1200000>; 245 + 246 + regulator-state-mem { 247 + regulator-off-in-suspend; 248 + }; 249 + }; 250 + 251 + vcc_3v3_s0: pldo-reg4 { 252 + regulator-name = "vcc_3v3_s0"; 253 + regulator-always-on; 254 + regulator-boot-on; 255 + regulator-min-microvolt = <3300000>; 256 + regulator-max-microvolt = <3300000>; 257 + regulator-ramp-delay = <12500>; 258 + 259 + regulator-state-mem { 260 + regulator-off-in-suspend; 261 + }; 262 + }; 263 + 264 + vccio_sd_s0: pldo-reg5 { 265 + regulator-name = "vccio_sd_s0"; 266 + regulator-always-on; 267 + regulator-boot-on; 268 + regulator-min-microvolt = <1800000>; 269 + regulator-max-microvolt = <3300000>; 270 + regulator-ramp-delay = <12500>; 271 + 272 + regulator-state-mem { 273 + regulator-off-in-suspend; 274 + }; 275 + }; 276 + 277 + pldo6_s3: pldo-reg6 { 278 + regulator-name = "pldo6_s3"; 279 + regulator-always-on; 280 + regulator-boot-on; 281 + regulator-min-microvolt = <1800000>; 282 + regulator-max-microvolt = <1800000>; 283 + 284 + regulator-state-mem { 285 + regulator-on-in-suspend; 286 + regulator-suspend-microvolt = <1800000>; 287 + }; 288 + }; 289 + 290 + vdd_0v75_s3: nldo-reg1 { 291 + regulator-name = "vdd_0v75_s3"; 292 + regulator-always-on; 293 + regulator-boot-on; 294 + regulator-min-microvolt = <750000>; 295 + regulator-max-microvolt = <750000>; 296 + 297 + regulator-state-mem { 298 + regulator-on-in-suspend; 299 + regulator-suspend-microvolt = <750000>; 300 + }; 301 + }; 302 + 303 + vdd_ddr_pll_s0: nldo-reg2 { 304 + regulator-name = "vdd_ddr_pll_s0"; 305 + regulator-always-on; 306 + regulator-boot-on; 307 + regulator-min-microvolt = <850000>; 308 + regulator-max-microvolt = <850000>; 309 + 310 + regulator-state-mem { 311 + regulator-off-in-suspend; 312 + regulator-suspend-microvolt = <850000>; 313 + }; 314 + }; 315 + 316 + avdd_0v75_s0: nldo-reg3 { 317 + regulator-name = "avdd_0v75_s0"; 318 + regulator-always-on; 319 + regulator-boot-on; 320 + regulator-min-microvolt = <750000>; 321 + regulator-max-microvolt = <750000>; 322 + 323 + regulator-state-mem { 324 + regulator-off-in-suspend; 325 + }; 326 + }; 327 + 328 + vdd_0v85_s0: nldo-reg4 { 329 + regulator-name = "vdd_0v85_s0"; 330 + regulator-always-on; 331 + regulator-boot-on; 332 + regulator-min-microvolt = <850000>; 333 + regulator-max-microvolt = <850000>; 334 + 335 + regulator-state-mem { 336 + regulator-off-in-suspend; 337 + }; 338 + }; 339 + 340 + vdd_0v75_s0: nldo-reg5 { 341 + regulator-name = "vdd_0v75_s0"; 342 + regulator-always-on; 343 + regulator-boot-on; 344 + regulator-min-microvolt = <750000>; 345 + regulator-max-microvolt = <750000>; 346 + 347 + regulator-state-mem { 348 + regulator-off-in-suspend; 349 + }; 350 + }; 351 + }; 352 + }; 68 353 };

+82 -1

arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts

··· 38 38 regulator-max-microvolt = <12000000>; 39 39 }; 40 40 41 + vcc5v0_host: vcc5v0-host-regulator { 42 + compatible = "regulator-fixed"; 43 + regulator-name = "vcc5v0_host"; 44 + regulator-boot-on; 45 + regulator-always-on; 46 + regulator-min-microvolt = <5000000>; 47 + regulator-max-microvolt = <5000000>; 48 + enable-active-high; 49 + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 50 + pinctrl-names = "default"; 51 + pinctrl-0 = <&vcc5v0_host_en>; 52 + vin-supply = <&vcc5v0_usb>; 53 + }; 54 + 41 55 vcc5v0_sys: vcc5v0-sys-regulator { 42 56 compatible = "regulator-fixed"; 43 57 regulator-name = "vcc5v0_sys"; ··· 61 47 regulator-max-microvolt = <5000000>; 62 48 vin-supply = <&vcc12v_dcin>; 63 49 }; 50 + 51 + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { 52 + compatible = "regulator-fixed"; 53 + regulator-name = "vcc5v0_usbdcin"; 54 + regulator-always-on; 55 + regulator-boot-on; 56 + regulator-min-microvolt = <5000000>; 57 + regulator-max-microvolt = <5000000>; 58 + vin-supply = <&vcc12v_dcin>; 59 + }; 60 + 61 + vcc5v0_usb: vcc5v0-usb-regulator { 62 + compatible = "regulator-fixed"; 63 + regulator-name = "vcc5v0_usb"; 64 + regulator-always-on; 65 + regulator-boot-on; 66 + regulator-min-microvolt = <5000000>; 67 + regulator-max-microvolt = <5000000>; 68 + vin-supply = <&vcc5v0_usbdcin>; 69 + }; 70 + }; 71 + 72 + &combphy0_ps { 73 + status = "okay"; 64 74 }; 65 75 66 76 &cpu_b0 { ··· 176 138 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 177 139 }; 178 140 }; 141 + 142 + usb { 143 + vcc5v0_host_en: vcc5v0-host-en { 144 + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 145 + }; 146 + }; 179 147 }; 180 148 181 149 &pwm2 { ··· 193 149 no-sdio; 194 150 no-sd; 195 151 non-removable; 196 - max-frequency = <200000000>; 197 152 mmc-hs400-1_8v; 198 153 mmc-hs400-enhanced-strobe; 199 154 status = "okay"; ··· 803 760 }; 804 761 }; 805 762 763 + &sata0 { 764 + status = "okay"; 765 + }; 766 + 767 + &u2phy2 { 768 + status = "okay"; 769 + }; 770 + 771 + &u2phy2_host { 772 + phy-supply = <&vcc5v0_host>; 773 + status = "okay"; 774 + }; 775 + 776 + &u2phy3 { 777 + status = "okay"; 778 + }; 779 + 780 + &u2phy3_host { 781 + phy-supply = <&vcc5v0_host>; 782 + status = "okay"; 783 + }; 784 + 806 785 &uart2 { 807 786 pinctrl-0 = <&uart2m0_xfer>; 787 + status = "okay"; 788 + }; 789 + 790 + &usb_host0_ehci { 791 + status = "okay"; 792 + }; 793 + 794 + &usb_host0_ohci { 795 + status = "okay"; 796 + }; 797 + 798 + &usb_host1_ehci { 799 + status = "okay"; 800 + }; 801 + 802 + &usb_host1_ohci { 808 803 status = "okay"; 809 804 };

+888

arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 + * Copyright (c) 2023 Thomas McKahan 5 + * 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/pinctrl/rockchip.h> 12 + #include <dt-bindings/usb/pd.h> 13 + #include "rk3588.dtsi" 14 + 15 + / { 16 + model = "FriendlyElec NanoPC-T6"; 17 + compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; 18 + 19 + aliases { 20 + mmc0 = &sdhci; 21 + mmc1 = &sdmmc; 22 + serial2 = &uart2; 23 + }; 24 + 25 + chosen { 26 + stdout-path = "serial2:1500000n8"; 27 + }; 28 + 29 + leds { 30 + compatible = "gpio-leds"; 31 + 32 + sys_led: led-0 { 33 + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 34 + label = "system-led"; 35 + linux,default-trigger = "heartbeat"; 36 + pinctrl-names = "default"; 37 + pinctrl-0 = <&sys_led_pin>; 38 + }; 39 + 40 + usr_led: led-1 { 41 + gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 42 + label = "user-led"; 43 + pinctrl-names = "default"; 44 + pinctrl-0 = <&usr_led_pin>; 45 + }; 46 + }; 47 + 48 + sound { 49 + compatible = "simple-audio-card"; 50 + pinctrl-names = "default"; 51 + pinctrl-0 = <&hp_det>; 52 + 53 + simple-audio-card,name = "realtek,rt5616-codec"; 54 + simple-audio-card,format = "i2s"; 55 + simple-audio-card,mclk-fs = <256>; 56 + 57 + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; 58 + simple-audio-card,hp-pin-name = "Headphones"; 59 + 60 + simple-audio-card,widgets = 61 + "Headphone", "Headphones", 62 + "Microphone", "Microphone Jack"; 63 + simple-audio-card,routing = 64 + "Headphones", "HPOL", 65 + "Headphones", "HPOR", 66 + "MIC1", "Microphone Jack", 67 + "Microphone Jack", "micbias1"; 68 + 69 + simple-audio-card,cpu { 70 + sound-dai = <&i2s0_8ch>; 71 + }; 72 + simple-audio-card,codec { 73 + sound-dai = <&rt5616>; 74 + }; 75 + }; 76 + 77 + vcc12v_dcin: vcc12v-dcin-regulator { 78 + compatible = "regulator-fixed"; 79 + regulator-name = "vcc12v_dcin"; 80 + regulator-always-on; 81 + regulator-boot-on; 82 + regulator-min-microvolt = <12000000>; 83 + regulator-max-microvolt = <12000000>; 84 + }; 85 + 86 + /* vcc5v0_sys powers peripherals */ 87 + vcc5v0_sys: vcc5v0-sys-regulator { 88 + compatible = "regulator-fixed"; 89 + regulator-name = "vcc5v0_sys"; 90 + regulator-always-on; 91 + regulator-boot-on; 92 + regulator-min-microvolt = <5000000>; 93 + regulator-max-microvolt = <5000000>; 94 + vin-supply = <&vcc12v_dcin>; 95 + }; 96 + 97 + /* vcc4v0_sys powers the RK806, RK860's */ 98 + vcc4v0_sys: vcc4v0-sys-regulator { 99 + compatible = "regulator-fixed"; 100 + regulator-name = "vcc4v0_sys"; 101 + regulator-always-on; 102 + regulator-boot-on; 103 + regulator-min-microvolt = <4000000>; 104 + regulator-max-microvolt = <4000000>; 105 + vin-supply = <&vcc12v_dcin>; 106 + }; 107 + 108 + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { 109 + compatible = "regulator-fixed"; 110 + regulator-name = "vcc-1v1-nldo-s3"; 111 + regulator-always-on; 112 + regulator-boot-on; 113 + regulator-min-microvolt = <1100000>; 114 + regulator-max-microvolt = <1100000>; 115 + vin-supply = <&vcc4v0_sys>; 116 + }; 117 + 118 + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { 119 + compatible = "regulator-fixed"; 120 + regulator-name = "vcc_3v3_pcie20"; 121 + regulator-always-on; 122 + regulator-boot-on; 123 + regulator-min-microvolt = <3300000>; 124 + regulator-max-microvolt = <3300000>; 125 + vin-supply = <&vcc_3v3_s3>; 126 + }; 127 + 128 + vbus5v0_typec: vbus5v0-typec-regulator { 129 + compatible = "regulator-fixed"; 130 + enable-active-high; 131 + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 132 + pinctrl-names = "default"; 133 + pinctrl-0 = <&typec5v_pwren>; 134 + regulator-name = "vbus5v0_typec"; 135 + regulator-min-microvolt = <5000000>; 136 + regulator-max-microvolt = <5000000>; 137 + vin-supply = <&vcc5v0_sys>; 138 + }; 139 + 140 + vcc3v3_pcie30: vcc3v3-pcie30-regulator { 141 + compatible = "regulator-fixed"; 142 + enable-active-high; 143 + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 144 + pinctrl-names = "default"; 145 + pinctrl-0 = <&pcie_m2_0_pwren>; 146 + regulator-name = "vcc3v3_pcie30"; 147 + regulator-min-microvolt = <3300000>; 148 + regulator-max-microvolt = <3300000>; 149 + vin-supply = <&vcc5v0_sys>; 150 + }; 151 + }; 152 + 153 + &combphy0_ps { 154 + status = "okay"; 155 + }; 156 + 157 + &combphy1_ps { 158 + status = "okay"; 159 + }; 160 + 161 + &combphy2_psu { 162 + status = "okay"; 163 + }; 164 + 165 + &cpu_l0 { 166 + cpu-supply = <&vdd_cpu_lit_s0>; 167 + }; 168 + 169 + &cpu_l1 { 170 + cpu-supply = <&vdd_cpu_lit_s0>; 171 + }; 172 + 173 + &cpu_l2 { 174 + cpu-supply = <&vdd_cpu_lit_s0>; 175 + }; 176 + 177 + &cpu_l3 { 178 + cpu-supply = <&vdd_cpu_lit_s0>; 179 + }; 180 + 181 + &cpu_b0{ 182 + cpu-supply = <&vdd_cpu_big0_s0>; 183 + }; 184 + 185 + &cpu_b1{ 186 + cpu-supply = <&vdd_cpu_big0_s0>; 187 + }; 188 + 189 + &cpu_b2{ 190 + cpu-supply = <&vdd_cpu_big1_s0>; 191 + }; 192 + 193 + &cpu_b3{ 194 + cpu-supply = <&vdd_cpu_big1_s0>; 195 + }; 196 + 197 + &gpio0 { 198 + gpio-line-names = /* GPIO0 A0-A7 */ 199 + "", "", "", "", 200 + "", "", "", "", 201 + /* GPIO0 B0-B7 */ 202 + "", "", "", "", 203 + "", "", "", "", 204 + /* GPIO0 C0-C7 */ 205 + "", "", "", "", 206 + "HEADER_10", "HEADER_08", "HEADER_32", "", 207 + /* GPIO0 D0-D7 */ 208 + "", "", "", "", 209 + "", "", "", ""; 210 + }; 211 + 212 + &gpio1 { 213 + gpio-line-names = /* GPIO1 A0-A7 */ 214 + "HEADER_27", "HEADER_28", "", "", 215 + "", "", "", "HEADER_15", 216 + /* GPIO1 B0-B7 */ 217 + "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", 218 + "HEADER_24", "HEADER_22", "", "", 219 + /* GPIO1 C0-C7 */ 220 + "", "", "", "", 221 + "", "", "", "", 222 + /* GPIO1 D0-D7 */ 223 + "", "", "", "", 224 + "", "", "HEADER_05", "HEADER_03"; 225 + }; 226 + 227 + &gpio2 { 228 + gpio-line-names = /* GPIO2 A0-A7 */ 229 + "", "", "", "", 230 + "", "", "", "", 231 + /* GPIO2 B0-B7 */ 232 + "", "", "", "", 233 + "", "", "", "", 234 + /* GPIO2 C0-C7 */ 235 + "", "CSI1_11", "CSI1_12", "", 236 + "", "", "", "", 237 + /* GPIO2 D0-D7 */ 238 + "", "", "", "", 239 + "", "", "", ""; 240 + }; 241 + 242 + &gpio3 { 243 + gpio-line-names = /* GPIO3 A0-A7 */ 244 + "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", 245 + "HEADER_37", "", "DSI0_12", "", 246 + /* GPIO3 B0-B7 */ 247 + "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", 248 + "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", 249 + /* GPIO3 C0-C7 */ 250 + "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", 251 + "", "", "", "", 252 + /* GPIO3 D0-D7 */ 253 + "", "", "", "", 254 + "", "DSI1_10", "", ""; 255 + }; 256 + 257 + &gpio4 { 258 + gpio-line-names = /* GPIO4 A0-A7 */ 259 + "DSI1_08", "DSI1_14", "", "DSI1_12", 260 + "", "", "", "", 261 + /* GPIO4 B0-B7 */ 262 + "", "", "", "", 263 + "", "", "", "", 264 + /* GPIO4 C0-C7 */ 265 + "", "", "", "", 266 + "CSI0_11", "CSI0_12", "", "", 267 + /* GPIO4 D0-D7 */ 268 + "", "", "", "", 269 + "", "", "", ""; 270 + }; 271 + 272 + &i2c0 { 273 + pinctrl-names = "default"; 274 + pinctrl-0 = <&i2c0m2_xfer>; 275 + status = "okay"; 276 + 277 + vdd_cpu_big0_s0: regulator@42 { 278 + compatible = "rockchip,rk8602"; 279 + reg = <0x42>; 280 + fcs,suspend-voltage-selector = <1>; 281 + regulator-name = "vdd_cpu_big0_s0"; 282 + regulator-always-on; 283 + regulator-boot-on; 284 + regulator-min-microvolt = <550000>; 285 + regulator-max-microvolt = <1050000>; 286 + regulator-ramp-delay = <2300>; 287 + vin-supply = <&vcc4v0_sys>; 288 + 289 + regulator-state-mem { 290 + regulator-off-in-suspend; 291 + }; 292 + }; 293 + 294 + vdd_cpu_big1_s0: regulator@43 { 295 + compatible = "rockchip,rk8603", "rockchip,rk8602"; 296 + reg = <0x43>; 297 + fcs,suspend-voltage-selector = <1>; 298 + regulator-name = "vdd_cpu_big1_s0"; 299 + regulator-always-on; 300 + regulator-boot-on; 301 + regulator-min-microvolt = <550000>; 302 + regulator-max-microvolt = <1050000>; 303 + regulator-ramp-delay = <2300>; 304 + vin-supply = <&vcc4v0_sys>; 305 + 306 + regulator-state-mem { 307 + regulator-off-in-suspend; 308 + }; 309 + }; 310 + }; 311 + 312 + &i2c2 { 313 + status = "okay"; 314 + 315 + vdd_npu_s0: regulator@42 { 316 + compatible = "rockchip,rk8602"; 317 + reg = <0x42>; 318 + rockchip,suspend-voltage-selector = <1>; 319 + regulator-name = "vdd_npu_s0"; 320 + regulator-always-on; 321 + regulator-boot-on; 322 + regulator-min-microvolt = <550000>; 323 + regulator-max-microvolt = <950000>; 324 + regulator-ramp-delay = <2300>; 325 + vin-supply = <&vcc4v0_sys>; 326 + 327 + regulator-state-mem { 328 + regulator-off-in-suspend; 329 + }; 330 + }; 331 + }; 332 + 333 + &i2c6 { 334 + clock-frequency = <200000>; 335 + status = "okay"; 336 + 337 + fusb302: typec-portc@22 { 338 + compatible = "fcs,fusb302"; 339 + reg = <0x22>; 340 + interrupt-parent = <&gpio0>; 341 + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; 342 + pinctrl-0 = <&usbc0_int>; 343 + pinctrl-names = "default"; 344 + vbus-supply = <&vbus5v0_typec>; 345 + 346 + connector { 347 + compatible = "usb-c-connector"; 348 + data-role = "dual"; 349 + label = "USB-C"; 350 + power-role = "dual"; 351 + try-power-role = "sink"; 352 + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; 353 + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 354 + op-sink-microwatt = <1000000>; 355 + }; 356 + }; 357 + 358 + hym8563: rtc@51 { 359 + compatible = "haoyu,hym8563"; 360 + reg = <0x51>; 361 + #clock-cells = <0>; 362 + clock-output-names = "hym8563"; 363 + pinctrl-names = "default"; 364 + pinctrl-0 = <&hym8563_int>; 365 + interrupt-parent = <&gpio0>; 366 + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 367 + wakeup-source; 368 + }; 369 + }; 370 + 371 + &i2c7 { 372 + clock-frequency = <200000>; 373 + status = "okay"; 374 + 375 + rt5616: codec@1b { 376 + compatible = "realtek,rt5616"; 377 + reg = <0x1b>; 378 + clocks = <&cru I2S0_8CH_MCLKOUT>; 379 + clock-names = "mclk"; 380 + #sound-dai-cells = <0>; 381 + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; 382 + assigned-clock-rates = <12288000>; 383 + 384 + port { 385 + rt5616_p0_0: endpoint { 386 + remote-endpoint = <&i2s0_8ch_p0_0>; 387 + }; 388 + }; 389 + }; 390 + 391 + /* connected with MIPI-CSI1 */ 392 + }; 393 + 394 + &i2c8 { 395 + pinctrl-0 = <&i2c8m2_xfer>; 396 + }; 397 + 398 + &i2s0_8ch { 399 + pinctrl-names = "default"; 400 + pinctrl-0 = <&i2s0_lrck 401 + &i2s0_mclk 402 + &i2s0_sclk 403 + &i2s0_sdi0 404 + &i2s0_sdo0>; 405 + status = "okay"; 406 + 407 + i2s0_8ch_p0: port { 408 + i2s0_8ch_p0_0: endpoint { 409 + dai-format = "i2s"; 410 + mclk-fs = <256>; 411 + remote-endpoint = <&rt5616_p0_0>; 412 + }; 413 + }; 414 + }; 415 + 416 + &pcie2x1l0 { 417 + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; 418 + vpcie3v3-supply = <&vcc_3v3_pcie20>; 419 + pinctrl-names = "default"; 420 + pinctrl-0 = <&pcie2_0_rst>; 421 + status = "okay"; 422 + }; 423 + 424 + &pcie2x1l2 { 425 + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; 426 + vpcie3v3-supply = <&vcc_3v3_pcie20>; 427 + pinctrl-names = "default"; 428 + pinctrl-0 = <&pcie2_2_rst>; 429 + status = "okay"; 430 + }; 431 + 432 + &pcie30phy { 433 + status = "okay"; 434 + }; 435 + 436 + &pcie3x4 { 437 + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 438 + vpcie3v3-supply = <&vcc3v3_pcie30>; 439 + status = "okay"; 440 + }; 441 + 442 + &pinctrl { 443 + gpio-leds { 444 + sys_led_pin: sys-led-pin { 445 + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 446 + }; 447 + 448 + usr_led_pin: usr-led-pin { 449 + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 450 + }; 451 + }; 452 + 453 + headphone { 454 + hp_det: hp-det { 455 + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 456 + }; 457 + }; 458 + 459 + hym8563 { 460 + hym8563_int: hym8563-int { 461 + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 462 + }; 463 + }; 464 + 465 + pcie { 466 + pcie2_0_rst: pcie2-0-rst { 467 + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 468 + }; 469 + 470 + pcie2_2_rst: pcie2-2-rst { 471 + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 472 + }; 473 + 474 + pcie_m2_0_pwren: pcie-m20-pwren { 475 + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 476 + }; 477 + }; 478 + 479 + usb { 480 + typec5v_pwren: typec5v-pwren { 481 + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 482 + }; 483 + 484 + usbc0_int: usbc0-int { 485 + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 486 + }; 487 + }; 488 + }; 489 + 490 + &pwm1 { 491 + pinctrl-0 = <&pwm1m1_pins>; 492 + status = "okay"; 493 + }; 494 + 495 + &saradc { 496 + vref-supply = <&avcc_1v8_s0>; 497 + status = "okay"; 498 + }; 499 + 500 + &sdhci { 501 + bus-width = <8>; 502 + no-sdio; 503 + no-sd; 504 + non-removable; 505 + max-frequency = <200000000>; 506 + mmc-hs400-1_8v; 507 + mmc-hs400-enhanced-strobe; 508 + status = "okay"; 509 + }; 510 + 511 + &sdmmc { 512 + max-frequency = <200000000>; 513 + no-sdio; 514 + no-mmc; 515 + bus-width = <4>; 516 + cap-mmc-highspeed; 517 + cap-sd-highspeed; 518 + disable-wp; 519 + sd-uhs-sdr104; 520 + vmmc-supply = <&vcc_3v3_s3>; 521 + vqmmc-supply = <&vccio_sd_s0>; 522 + status = "okay"; 523 + }; 524 + 525 + &spi2 { 526 + status = "okay"; 527 + assigned-clocks = <&cru CLK_SPI2>; 528 + assigned-clock-rates = <200000000>; 529 + pinctrl-names = "default"; 530 + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 531 + num-cs = <1>; 532 + 533 + pmic@0 { 534 + compatible = "rockchip,rk806"; 535 + spi-max-frequency = <1000000>; 536 + reg = <0x0>; 537 + 538 + interrupt-parent = <&gpio0>; 539 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 540 + 541 + pinctrl-names = "default"; 542 + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 543 + <&rk806_dvs2_null>, <&rk806_dvs3_null>; 544 + 545 + vcc1-supply = <&vcc4v0_sys>; 546 + vcc2-supply = <&vcc4v0_sys>; 547 + vcc3-supply = <&vcc4v0_sys>; 548 + vcc4-supply = <&vcc4v0_sys>; 549 + vcc5-supply = <&vcc4v0_sys>; 550 + vcc6-supply = <&vcc4v0_sys>; 551 + vcc7-supply = <&vcc4v0_sys>; 552 + vcc8-supply = <&vcc4v0_sys>; 553 + vcc9-supply = <&vcc4v0_sys>; 554 + vcc10-supply = <&vcc4v0_sys>; 555 + vcc11-supply = <&vcc_2v0_pldo_s3>; 556 + vcc12-supply = <&vcc4v0_sys>; 557 + vcc13-supply = <&vcc_1v1_nldo_s3>; 558 + vcc14-supply = <&vcc_1v1_nldo_s3>; 559 + vcca-supply = <&vcc4v0_sys>; 560 + 561 + gpio-controller; 562 + #gpio-cells = <2>; 563 + 564 + rk806_dvs1_null: dvs1-null-pins { 565 + pins = "gpio_pwrctrl2"; 566 + function = "pin_fun0"; 567 + }; 568 + 569 + rk806_dvs2_null: dvs2-null-pins { 570 + pins = "gpio_pwrctrl2"; 571 + function = "pin_fun0"; 572 + }; 573 + 574 + rk806_dvs3_null: dvs3-null-pins { 575 + pins = "gpio_pwrctrl3"; 576 + function = "pin_fun0"; 577 + }; 578 + 579 + regulators { 580 + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { 581 + regulator-boot-on; 582 + regulator-min-microvolt = <550000>; 583 + regulator-max-microvolt = <950000>; 584 + regulator-ramp-delay = <12500>; 585 + regulator-name = "vdd_gpu_s0"; 586 + regulator-enable-ramp-delay = <400>; 587 + 588 + regulator-state-mem { 589 + regulator-off-in-suspend; 590 + }; 591 + }; 592 + 593 + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { 594 + regulator-always-on; 595 + regulator-boot-on; 596 + regulator-min-microvolt = <550000>; 597 + regulator-max-microvolt = <950000>; 598 + regulator-ramp-delay = <12500>; 599 + regulator-name = "vdd_cpu_lit_s0"; 600 + 601 + regulator-state-mem { 602 + regulator-off-in-suspend; 603 + }; 604 + }; 605 + 606 + vdd_log_s0: dcdc-reg3 { 607 + regulator-always-on; 608 + regulator-boot-on; 609 + regulator-min-microvolt = <675000>; 610 + regulator-max-microvolt = <750000>; 611 + regulator-ramp-delay = <12500>; 612 + regulator-name = "vdd_log_s0"; 613 + 614 + regulator-state-mem { 615 + regulator-off-in-suspend; 616 + regulator-suspend-microvolt = <750000>; 617 + }; 618 + }; 619 + 620 + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { 621 + regulator-always-on; 622 + regulator-boot-on; 623 + regulator-min-microvolt = <550000>; 624 + regulator-max-microvolt = <950000>; 625 + regulator-init-microvolt = <750000>; 626 + regulator-ramp-delay = <12500>; 627 + regulator-name = "vdd_vdenc_s0"; 628 + 629 + regulator-state-mem { 630 + regulator-off-in-suspend; 631 + }; 632 + }; 633 + 634 + vdd_ddr_s0: dcdc-reg5 { 635 + regulator-always-on; 636 + regulator-boot-on; 637 + regulator-min-microvolt = <675000>; 638 + regulator-max-microvolt = <900000>; 639 + regulator-ramp-delay = <12500>; 640 + regulator-name = "vdd_ddr_s0"; 641 + 642 + regulator-state-mem { 643 + regulator-off-in-suspend; 644 + regulator-suspend-microvolt = <850000>; 645 + }; 646 + }; 647 + 648 + vdd2_ddr_s3: dcdc-reg6 { 649 + regulator-always-on; 650 + regulator-boot-on; 651 + regulator-name = "vdd2_ddr_s3"; 652 + 653 + regulator-state-mem { 654 + regulator-on-in-suspend; 655 + }; 656 + }; 657 + 658 + vcc_2v0_pldo_s3: dcdc-reg7 { 659 + regulator-always-on; 660 + regulator-boot-on; 661 + regulator-min-microvolt = <2000000>; 662 + regulator-max-microvolt = <2000000>; 663 + regulator-ramp-delay = <12500>; 664 + regulator-name = "vdd_2v0_pldo_s3"; 665 + 666 + regulator-state-mem { 667 + regulator-on-in-suspend; 668 + regulator-suspend-microvolt = <2000000>; 669 + }; 670 + }; 671 + 672 + vcc_3v3_s3: dcdc-reg8 { 673 + regulator-always-on; 674 + regulator-boot-on; 675 + regulator-min-microvolt = <3300000>; 676 + regulator-max-microvolt = <3300000>; 677 + regulator-name = "vcc_3v3_s3"; 678 + 679 + regulator-state-mem { 680 + regulator-on-in-suspend; 681 + regulator-suspend-microvolt = <3300000>; 682 + }; 683 + }; 684 + 685 + vddq_ddr_s0: dcdc-reg9 { 686 + regulator-always-on; 687 + regulator-boot-on; 688 + regulator-name = "vddq_ddr_s0"; 689 + 690 + regulator-state-mem { 691 + regulator-off-in-suspend; 692 + }; 693 + }; 694 + 695 + vcc_1v8_s3: dcdc-reg10 { 696 + regulator-always-on; 697 + regulator-boot-on; 698 + regulator-min-microvolt = <1800000>; 699 + regulator-max-microvolt = <1800000>; 700 + regulator-name = "vcc_1v8_s3"; 701 + 702 + regulator-state-mem { 703 + regulator-on-in-suspend; 704 + regulator-suspend-microvolt = <1800000>; 705 + }; 706 + }; 707 + 708 + avcc_1v8_s0: pldo-reg1 { 709 + regulator-always-on; 710 + regulator-boot-on; 711 + regulator-min-microvolt = <1800000>; 712 + regulator-max-microvolt = <1800000>; 713 + regulator-name = "avcc_1v8_s0"; 714 + 715 + regulator-state-mem { 716 + regulator-off-in-suspend; 717 + }; 718 + }; 719 + 720 + vcc_1v8_s0: pldo-reg2 { 721 + regulator-always-on; 722 + regulator-boot-on; 723 + regulator-min-microvolt = <1800000>; 724 + regulator-max-microvolt = <1800000>; 725 + regulator-name = "vcc_1v8_s0"; 726 + 727 + regulator-state-mem { 728 + regulator-off-in-suspend; 729 + regulator-suspend-microvolt = <1800000>; 730 + }; 731 + }; 732 + 733 + avdd_1v2_s0: pldo-reg3 { 734 + regulator-always-on; 735 + regulator-boot-on; 736 + regulator-min-microvolt = <1200000>; 737 + regulator-max-microvolt = <1200000>; 738 + regulator-name = "avdd_1v2_s0"; 739 + 740 + regulator-state-mem { 741 + regulator-off-in-suspend; 742 + }; 743 + }; 744 + 745 + vcc_3v3_s0: pldo-reg4 { 746 + regulator-always-on; 747 + regulator-boot-on; 748 + regulator-min-microvolt = <3300000>; 749 + regulator-max-microvolt = <3300000>; 750 + regulator-ramp-delay = <12500>; 751 + regulator-name = "vcc_3v3_s0"; 752 + 753 + regulator-state-mem { 754 + regulator-off-in-suspend; 755 + }; 756 + }; 757 + 758 + vccio_sd_s0: pldo-reg5 { 759 + regulator-always-on; 760 + regulator-boot-on; 761 + regulator-min-microvolt = <1800000>; 762 + regulator-max-microvolt = <3300000>; 763 + regulator-ramp-delay = <12500>; 764 + regulator-name = "vccio_sd_s0"; 765 + 766 + regulator-state-mem { 767 + regulator-off-in-suspend; 768 + }; 769 + }; 770 + 771 + pldo6_s3: pldo-reg6 { 772 + regulator-always-on; 773 + regulator-boot-on; 774 + regulator-min-microvolt = <1800000>; 775 + regulator-max-microvolt = <1800000>; 776 + regulator-name = "pldo6_s3"; 777 + 778 + regulator-state-mem { 779 + regulator-on-in-suspend; 780 + regulator-suspend-microvolt = <1800000>; 781 + }; 782 + }; 783 + 784 + vdd_0v75_s3: nldo-reg1 { 785 + regulator-always-on; 786 + regulator-boot-on; 787 + regulator-min-microvolt = <750000>; 788 + regulator-max-microvolt = <750000>; 789 + regulator-name = "vdd_0v75_s3"; 790 + 791 + regulator-state-mem { 792 + regulator-on-in-suspend; 793 + regulator-suspend-microvolt = <750000>; 794 + }; 795 + }; 796 + 797 + vdd_ddr_pll_s0: nldo-reg2 { 798 + regulator-always-on; 799 + regulator-boot-on; 800 + regulator-min-microvolt = <850000>; 801 + regulator-max-microvolt = <850000>; 802 + regulator-name = "vdd_ddr_pll_s0"; 803 + 804 + regulator-state-mem { 805 + regulator-off-in-suspend; 806 + regulator-suspend-microvolt = <850000>; 807 + }; 808 + }; 809 + 810 + avdd_0v75_s0: nldo-reg3 { 811 + regulator-always-on; 812 + regulator-boot-on; 813 + regulator-min-microvolt = <750000>; 814 + regulator-max-microvolt = <750000>; 815 + regulator-name = "avdd_0v75_s0"; 816 + 817 + regulator-state-mem { 818 + regulator-off-in-suspend; 819 + }; 820 + }; 821 + 822 + vdd_0v85_s0: nldo-reg4 { 823 + regulator-always-on; 824 + regulator-boot-on; 825 + regulator-min-microvolt = <850000>; 826 + regulator-max-microvolt = <850000>; 827 + regulator-name = "vdd_0v85_s0"; 828 + 829 + regulator-state-mem { 830 + regulator-off-in-suspend; 831 + }; 832 + }; 833 + 834 + vdd_0v75_s0: nldo-reg5 { 835 + regulator-always-on; 836 + regulator-boot-on; 837 + regulator-min-microvolt = <750000>; 838 + regulator-max-microvolt = <750000>; 839 + regulator-name = "vdd_0v75_s0"; 840 + 841 + regulator-state-mem { 842 + regulator-off-in-suspend; 843 + }; 844 + }; 845 + }; 846 + }; 847 + }; 848 + 849 + &tsadc { 850 + status = "okay"; 851 + }; 852 + 853 + &uart2 { 854 + pinctrl-0 = <&uart2m0_xfer>; 855 + status = "okay"; 856 + }; 857 + 858 + &u2phy2_host { 859 + status = "okay"; 860 + }; 861 + 862 + &u2phy3_host { 863 + status = "okay"; 864 + }; 865 + 866 + &u2phy2 { 867 + status = "okay"; 868 + }; 869 + 870 + &u2phy3 { 871 + status = "okay"; 872 + }; 873 + 874 + &usb_host0_ehci { 875 + status = "okay"; 876 + }; 877 + 878 + &usb_host0_ohci { 879 + status = "okay"; 880 + }; 881 + 882 + &usb_host1_ehci { 883 + status = "okay"; 884 + }; 885 + 886 + &usb_host1_ohci { 887 + status = "okay"; 888 + };

+67 -11

arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts

··· 11 11 12 12 aliases { 13 13 mmc0 = &sdhci; 14 + mmc1 = &sdmmc; 14 15 serial2 = &uart2; 15 16 }; 16 17 ··· 19 18 stdout-path = "serial2:1500000n8"; 20 19 }; 21 20 22 - fan: pwm-fan { 23 - compatible = "pwm-fan"; 24 - cooling-levels = <0 95 145 195 255>; 25 - fan-supply = <&vcc5v0_sys>; 26 - pwms = <&pwm1 0 50000 0>; 27 - #cooling-cells = <2>; 28 - }; 29 - 30 - sound { 21 + analog-sound { 31 22 compatible = "audio-graph-card"; 32 - label = "Analog"; 23 + label = "rk3588-es8316"; 33 24 34 25 widgets = "Microphone", "Mic Jack", 35 26 "Headphone", "Headphones"; ··· 34 41 hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; 35 42 pinctrl-names = "default"; 36 43 pinctrl-0 = <&hp_detect>; 44 + }; 45 + 46 + fan: pwm-fan { 47 + compatible = "pwm-fan"; 48 + cooling-levels = <0 95 145 195 255>; 49 + fan-supply = <&vcc5v0_sys>; 50 + pwms = <&pwm1 0 50000 0>; 51 + #cooling-cells = <2>; 52 + }; 53 + 54 + vcc5v0_host: vcc5v0-host-regulator { 55 + compatible = "regulator-fixed"; 56 + regulator-name = "vcc5v0_host"; 57 + regulator-boot-on; 58 + regulator-always-on; 59 + regulator-min-microvolt = <5000000>; 60 + regulator-max-microvolt = <5000000>; 61 + enable-active-high; 62 + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 63 + pinctrl-names = "default"; 64 + pinctrl-0 = <&vcc5v0_host_en>; 65 + vin-supply = <&vcc5v0_sys>; 37 66 }; 38 67 39 68 vcc5v0_sys: vcc5v0-sys-regulator { ··· 216 201 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 217 202 }; 218 203 }; 204 + 205 + usb { 206 + vcc5v0_host_en: vcc5v0-host-en { 207 + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 208 + }; 209 + }; 219 210 }; 220 211 221 212 &pwm1 { ··· 238 217 no-sdio; 239 218 no-sd; 240 219 non-removable; 241 - max-frequency = <200000000>; 242 220 mmc-hs400-1_8v; 243 221 mmc-hs400-enhanced-strobe; 244 222 status = "okay"; ··· 250 230 bus-width = <4>; 251 231 cap-mmc-highspeed; 252 232 cap-sd-highspeed; 233 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 253 234 disable-wp; 254 235 sd-uhs-sdr104; 255 236 vmmc-supply = <&vcc_3v3_s3>; ··· 584 563 585 564 &uart2 { 586 565 pinctrl-0 = <&uart2m0_xfer>; 566 + status = "okay"; 567 + }; 568 + 569 + &u2phy2 { 570 + status = "okay"; 571 + }; 572 + 573 + &u2phy2_host { 574 + /* connected to USB hub, which is powered by vcc5v0_sys */ 575 + phy-supply = <&vcc5v0_sys>; 576 + status = "okay"; 577 + }; 578 + 579 + &u2phy3 { 580 + status = "okay"; 581 + }; 582 + 583 + &u2phy3_host { 584 + phy-supply = <&vcc5v0_host>; 585 + status = "okay"; 586 + }; 587 + 588 + &usb_host0_ehci { 589 + status = "okay"; 590 + }; 591 + 592 + &usb_host0_ohci { 593 + status = "okay"; 594 + }; 595 + 596 + &usb_host1_ehci { 597 + status = "okay"; 598 + }; 599 + 600 + &usb_host1_ohci { 587 601 status = "okay"; 588 602 };

+215

arch/arm64/boot/dts/rockchip/rk3588.dtsi

··· 7 7 #include "rk3588-pinctrl.dtsi" 8 8 9 9 / { 10 + pcie30_phy_grf: syscon@fd5b8000 { 11 + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 12 + reg = <0x0 0xfd5b8000 0x0 0x10000>; 13 + }; 14 + 15 + pipe_phy1_grf: syscon@fd5c0000 { 16 + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 17 + reg = <0x0 0xfd5c0000 0x0 0x100>; 18 + }; 19 + 10 20 i2s8_8ch: i2s@fddc8000 { 11 21 compatible = "rockchip,rk3588-i2s-tdm"; 12 22 reg = <0x0 0xfddc8000 0x0 0x1000>; ··· 85 75 status = "disabled"; 86 76 }; 87 77 78 + pcie3x4: pcie@fe150000 { 79 + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 80 + #address-cells = <3>; 81 + #size-cells = <2>; 82 + bus-range = <0x00 0x0f>; 83 + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 84 + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 85 + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 86 + clock-names = "aclk_mst", "aclk_slv", 87 + "aclk_dbi", "pclk", 88 + "aux", "pipe"; 89 + device_type = "pci"; 90 + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 91 + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 92 + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 93 + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 94 + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 95 + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 96 + #interrupt-cells = <1>; 97 + interrupt-map-mask = <0 0 0 7>; 98 + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 99 + <0 0 0 2 &pcie3x4_intc 1>, 100 + <0 0 0 3 &pcie3x4_intc 2>, 101 + <0 0 0 4 &pcie3x4_intc 3>; 102 + linux,pci-domain = <0>; 103 + max-link-speed = <3>; 104 + msi-map = <0x0000 &its1 0x0000 0x1000>; 105 + num-lanes = <4>; 106 + phys = <&pcie30phy>; 107 + phy-names = "pcie-phy"; 108 + power-domains = <&power RK3588_PD_PCIE>; 109 + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 110 + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 111 + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; 112 + reg = <0xa 0x40000000 0x0 0x00400000>, 113 + <0x0 0xfe150000 0x0 0x00010000>, 114 + <0x0 0xf0000000 0x0 0x00100000>; 115 + reg-names = "dbi", "apb", "config"; 116 + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 117 + reset-names = "pwr", "pipe"; 118 + status = "disabled"; 119 + 120 + pcie3x4_intc: legacy-interrupt-controller { 121 + interrupt-controller; 122 + #address-cells = <0>; 123 + #interrupt-cells = <1>; 124 + interrupt-parent = <&gic>; 125 + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 126 + }; 127 + }; 128 + 129 + pcie3x2: pcie@fe160000 { 130 + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 131 + #address-cells = <3>; 132 + #size-cells = <2>; 133 + bus-range = <0x10 0x1f>; 134 + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 135 + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 136 + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 137 + clock-names = "aclk_mst", "aclk_slv", 138 + "aclk_dbi", "pclk", 139 + "aux", "pipe"; 140 + device_type = "pci"; 141 + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 142 + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 143 + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 144 + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 145 + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 146 + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 147 + #interrupt-cells = <1>; 148 + interrupt-map-mask = <0 0 0 7>; 149 + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 150 + <0 0 0 2 &pcie3x2_intc 1>, 151 + <0 0 0 3 &pcie3x2_intc 2>, 152 + <0 0 0 4 &pcie3x2_intc 3>; 153 + linux,pci-domain = <1>; 154 + max-link-speed = <3>; 155 + msi-map = <0x1000 &its1 0x1000 0x1000>; 156 + num-lanes = <2>; 157 + phys = <&pcie30phy>; 158 + phy-names = "pcie-phy"; 159 + power-domains = <&power RK3588_PD_PCIE>; 160 + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 161 + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 162 + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; 163 + reg = <0xa 0x40400000 0x0 0x00400000>, 164 + <0x0 0xfe160000 0x0 0x00010000>, 165 + <0x0 0xf1000000 0x0 0x00100000>; 166 + reg-names = "dbi", "apb", "config"; 167 + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 168 + reset-names = "pwr", "pipe"; 169 + status = "disabled"; 170 + 171 + pcie3x2_intc: legacy-interrupt-controller { 172 + interrupt-controller; 173 + #address-cells = <0>; 174 + #interrupt-cells = <1>; 175 + interrupt-parent = <&gic>; 176 + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 177 + }; 178 + }; 179 + 180 + pcie2x1l0: pcie@fe170000 { 181 + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 182 + bus-range = <0x20 0x2f>; 183 + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 184 + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 185 + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 186 + clock-names = "aclk_mst", "aclk_slv", 187 + "aclk_dbi", "pclk", 188 + "aux", "pipe"; 189 + device_type = "pci"; 190 + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 191 + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 192 + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 193 + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 194 + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 195 + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 196 + #interrupt-cells = <1>; 197 + interrupt-map-mask = <0 0 0 7>; 198 + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 199 + <0 0 0 2 &pcie2x1l0_intc 1>, 200 + <0 0 0 3 &pcie2x1l0_intc 2>, 201 + <0 0 0 4 &pcie2x1l0_intc 3>; 202 + linux,pci-domain = <2>; 203 + max-link-speed = <2>; 204 + msi-map = <0x2000 &its0 0x2000 0x1000>; 205 + num-lanes = <1>; 206 + phys = <&combphy1_ps PHY_TYPE_PCIE>; 207 + phy-names = "pcie-phy"; 208 + power-domains = <&power RK3588_PD_PCIE>; 209 + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 210 + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 211 + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; 212 + reg = <0xa 0x40800000 0x0 0x00400000>, 213 + <0x0 0xfe170000 0x0 0x00010000>, 214 + <0x0 0xf2000000 0x0 0x00100000>; 215 + reg-names = "dbi", "apb", "config"; 216 + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 217 + reset-names = "pwr", "pipe"; 218 + #address-cells = <3>; 219 + #size-cells = <2>; 220 + status = "disabled"; 221 + 222 + pcie2x1l0_intc: legacy-interrupt-controller { 223 + interrupt-controller; 224 + #address-cells = <0>; 225 + #interrupt-cells = <1>; 226 + interrupt-parent = <&gic>; 227 + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 228 + }; 229 + }; 230 + 88 231 gmac0: ethernet@fe1b0000 { 89 232 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 90 233 reg = <0x0 0xfe1b0000 0x0 0x10000>; ··· 285 122 queue0 {}; 286 123 queue1 {}; 287 124 }; 125 + }; 126 + 127 + sata1: sata@fe220000 { 128 + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 129 + reg = <0 0xfe220000 0 0x1000>; 130 + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 131 + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 132 + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 133 + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 134 + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 135 + ports-implemented = <0x1>; 136 + #address-cells = <1>; 137 + #size-cells = <0>; 138 + status = "disabled"; 139 + 140 + sata-port@0 { 141 + reg = <0>; 142 + hba-port-cap = <HBA_PORT_FBSCP>; 143 + phys = <&combphy1_ps PHY_TYPE_SATA>; 144 + phy-names = "sata-phy"; 145 + snps,rx-ts-max = <32>; 146 + snps,tx-ts-max = <32>; 147 + }; 148 + }; 149 + 150 + combphy1_ps: phy@fee10000 { 151 + compatible = "rockchip,rk3588-naneng-combphy"; 152 + reg = <0x0 0xfee10000 0x0 0x100>; 153 + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 154 + <&cru PCLK_PHP_ROOT>; 155 + clock-names = "ref", "apb", "pipe"; 156 + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 157 + assigned-clock-rates = <100000000>; 158 + #phy-cells = <1>; 159 + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 160 + reset-names = "phy", "apb"; 161 + rockchip,pipe-grf = <&php_grf>; 162 + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 163 + status = "disabled"; 164 + }; 165 + 166 + pcie30phy: phy@fee80000 { 167 + compatible = "rockchip,rk3588-pcie3-phy"; 168 + reg = <0x0 0xfee80000 0x0 0x20000>; 169 + #phy-cells = <0>; 170 + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 171 + clock-names = "pclk"; 172 + resets = <&cru SRST_PCIE30_PHY>; 173 + reset-names = "phy"; 174 + rockchip,pipe-grf = <&php_grf>; 175 + rockchip,phy-grf = <&pcie30_phy_grf>; 176 + status = "disabled"; 288 177 }; 289 178 };

-2

arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts

··· 401 401 no-sd; 402 402 no-sdio; 403 403 non-removable; 404 - max-frequency = <200000000>; 405 404 vmmc-supply = <&vcc_3v3_s0>; 406 405 vqmmc-supply = <&vcc_1v8_s3>; 407 406 status = "okay"; ··· 428 429 cap-mmc-highspeed; 429 430 cap-sd-highspeed; 430 431 disable-wp; 431 - max-frequency = <200000000>; 432 432 no-sdio; 433 433 no-mmc; 434 434 sd-uhs-sdr104;

-1

arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts

··· 25 25 no-sdio; 26 26 no-sd; 27 27 non-removable; 28 - max-frequency = <200000000>; 29 28 mmc-hs400-1_8v; 30 29 mmc-hs400-enhanced-strobe; 31 30 status = "okay";

+664 -1

arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts

··· 3 3 /dts-v1/; 4 4 5 5 #include <dt-bindings/gpio/gpio.h> 6 + #include <dt-bindings/leds/common.h> 6 7 #include <dt-bindings/pinctrl/rockchip.h> 7 8 #include "rk3588s.dtsi" 8 9 ··· 13 12 14 13 aliases { 15 14 mmc0 = &sdhci; 15 + mmc1 = &sdmmc; 16 16 serial2 = &uart2; 17 + }; 18 + 19 + analog-sound { 20 + compatible = "audio-graph-card"; 21 + label = "rk3588-es8316"; 22 + 23 + widgets = "Microphone", "Mic Jack", 24 + "Headphone", "Headphones"; 25 + 26 + routing = "MIC2", "Mic Jack", 27 + "Headphones", "HPOL", 28 + "Headphones", "HPOR"; 29 + 30 + dais = <&i2s0_8ch_p0>; 17 31 }; 18 32 19 33 chosen { 20 34 stdout-path = "serial2:1500000n8"; 35 + }; 36 + 37 + leds { 38 + compatible = "gpio-leds"; 39 + pinctrl-names = "default"; 40 + pinctrl-0 = <&io_led>; 41 + 42 + io-led { 43 + color = <LED_COLOR_ID_BLUE>; 44 + function = LED_FUNCTION_STATUS; 45 + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 46 + linux,default-trigger = "heartbeat"; 47 + }; 48 + }; 49 + 50 + fan: pwm-fan { 51 + compatible = "pwm-fan"; 52 + cooling-levels = <0 95 145 195 255>; 53 + fan-supply = <&vcc_5v0>; 54 + pwms = <&pwm3 0 50000 0>; 55 + #cooling-cells = <2>; 56 + }; 57 + 58 + vcc12v_dcin: vcc12v-dcin-regulator { 59 + compatible = "regulator-fixed"; 60 + regulator-name = "vcc12v_dcin"; 61 + regulator-always-on; 62 + regulator-boot-on; 63 + regulator-min-microvolt = <12000000>; 64 + regulator-max-microvolt = <12000000>; 65 + }; 66 + 67 + vcc5v0_host: vcc5v0-host-regulator { 68 + compatible = "regulator-fixed"; 69 + regulator-name = "vcc5v0_host"; 70 + regulator-boot-on; 71 + regulator-always-on; 72 + regulator-min-microvolt = <5000000>; 73 + regulator-max-microvolt = <5000000>; 74 + enable-active-high; 75 + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; 76 + pinctrl-names = "default"; 77 + pinctrl-0 = <&vcc5v0_host_en>; 78 + vin-supply = <&vcc5v0_sys>; 79 + }; 80 + 81 + vcc5v0_sys: vcc5v0-sys-regulator { 82 + compatible = "regulator-fixed"; 83 + regulator-name = "vcc5v0_sys"; 84 + regulator-always-on; 85 + regulator-boot-on; 86 + regulator-min-microvolt = <5000000>; 87 + regulator-max-microvolt = <5000000>; 88 + vin-supply = <&vcc12v_dcin>; 89 + }; 90 + 91 + vcc_5v0: vcc-5v0-regulator { 92 + compatible = "regulator-fixed"; 93 + regulator-name = "vcc_5v0"; 94 + regulator-min-microvolt = <5000000>; 95 + regulator-max-microvolt = <5000000>; 96 + regulator-boot-on; 97 + regulator-always-on; 98 + enable-active-high; 99 + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; 100 + pinctrl-names = "default"; 101 + pinctrl-0 = <&vcc_5v0_en>; 102 + vin-supply = <&vcc5v0_sys>; 103 + }; 104 + 105 + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { 106 + compatible = "regulator-fixed"; 107 + regulator-name = "vcc_1v1_nldo_s3"; 108 + regulator-always-on; 109 + regulator-boot-on; 110 + regulator-min-microvolt = <1100000>; 111 + regulator-max-microvolt = <1100000>; 112 + vin-supply = <&vcc5v0_sys>; 113 + }; 114 + }; 115 + 116 + &cpu_b0 { 117 + cpu-supply = <&vdd_cpu_big0_s0>; 118 + }; 119 + 120 + &cpu_b1 { 121 + cpu-supply = <&vdd_cpu_big0_s0>; 122 + }; 123 + 124 + &cpu_b2 { 125 + cpu-supply = <&vdd_cpu_big1_s0>; 126 + }; 127 + 128 + &cpu_b3 { 129 + cpu-supply = <&vdd_cpu_big1_s0>; 130 + }; 131 + 132 + &cpu_l0 { 133 + cpu-supply = <&vdd_cpu_lit_s0>; 134 + }; 135 + 136 + &cpu_l1 { 137 + cpu-supply = <&vdd_cpu_lit_s0>; 138 + }; 139 + 140 + &cpu_l2 { 141 + cpu-supply = <&vdd_cpu_lit_s0>; 142 + }; 143 + 144 + &cpu_l3 { 145 + cpu-supply = <&vdd_cpu_lit_s0>; 146 + }; 147 + 148 + &i2c0 { 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&i2c0m2_xfer>; 151 + status = "okay"; 152 + 153 + vdd_cpu_big0_s0: regulator@42 { 154 + compatible = "rockchip,rk8602"; 155 + reg = <0x42>; 156 + fcs,suspend-voltage-selector = <1>; 157 + regulator-name = "vdd_cpu_big0_s0"; 158 + regulator-always-on; 159 + regulator-boot-on; 160 + regulator-min-microvolt = <550000>; 161 + regulator-max-microvolt = <1050000>; 162 + regulator-ramp-delay = <2300>; 163 + vin-supply = <&vcc5v0_sys>; 164 + 165 + regulator-state-mem { 166 + regulator-off-in-suspend; 167 + }; 168 + }; 169 + 170 + vdd_cpu_big1_s0: regulator@43 { 171 + compatible = "rockchip,rk8603", "rockchip,rk8602"; 172 + reg = <0x43>; 173 + fcs,suspend-voltage-selector = <1>; 174 + regulator-name = "vdd_cpu_big1_s0"; 175 + regulator-always-on; 176 + regulator-boot-on; 177 + regulator-min-microvolt = <550000>; 178 + regulator-max-microvolt = <1050000>; 179 + regulator-ramp-delay = <2300>; 180 + vin-supply = <&vcc5v0_sys>; 181 + 182 + regulator-state-mem { 183 + regulator-off-in-suspend; 184 + }; 185 + }; 186 + }; 187 + 188 + &i2c2 { 189 + status = "okay"; 190 + 191 + vdd_npu_s0: regulator@42 { 192 + compatible = "rockchip,rk8602"; 193 + reg = <0x42>; 194 + fcs,suspend-voltage-selector = <1>; 195 + regulator-name = "vdd_npu_s0"; 196 + regulator-always-on; 197 + regulator-boot-on; 198 + regulator-min-microvolt = <550000>; 199 + regulator-max-microvolt = <950000>; 200 + regulator-ramp-delay = <2300>; 201 + vin-supply = <&vcc5v0_sys>; 202 + 203 + regulator-state-mem { 204 + regulator-off-in-suspend; 205 + }; 206 + }; 207 + 208 + eeprom: eeprom@50 { 209 + compatible = "belling,bl24c16a", "atmel,24c16"; 210 + reg = <0x50>; 211 + pagesize = <16>; 212 + }; 213 + }; 214 + 215 + &i2c3 { 216 + status = "okay"; 217 + }; 218 + 219 + &i2c5 { 220 + status = "okay"; 221 + pinctrl-names = "default"; 222 + pinctrl-0 = <&i2c5m2_xfer>; 223 + }; 224 + 225 + &i2c7 { 226 + status = "okay"; 227 + 228 + es8316: audio-codec@11 { 229 + compatible = "everest,es8316"; 230 + reg = <0x11>; 231 + clocks = <&cru I2S0_8CH_MCLKOUT>; 232 + clock-names = "mclk"; 233 + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; 234 + assigned-clock-rates = <12288000>; 235 + #sound-dai-cells = <0>; 236 + 237 + port { 238 + es8316_p0_0: endpoint { 239 + remote-endpoint = <&i2s0_8ch_p0_0>; 240 + }; 241 + }; 242 + }; 243 + }; 244 + 245 + &i2s0_8ch { 246 + pinctrl-names = "default"; 247 + pinctrl-0 = <&i2s0_lrck 248 + &i2s0_mclk 249 + &i2s0_sclk 250 + &i2s0_sdi0 251 + &i2s0_sdo0>; 252 + status = "okay"; 253 + 254 + i2s0_8ch_p0: port { 255 + i2s0_8ch_p0_0: endpoint { 256 + dai-format = "i2s"; 257 + mclk-fs = <256>; 258 + remote-endpoint = <&es8316_p0_0>; 259 + }; 21 260 }; 22 261 }; 23 262 ··· 290 49 }; 291 50 292 51 &pinctrl { 52 + leds { 53 + io_led: io-led { 54 + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 55 + }; 56 + }; 57 + 58 + power { 59 + vcc_5v0_en: vcc-5v0-en { 60 + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 61 + }; 62 + }; 63 + 293 64 rtl8211f { 294 65 rtl8211f_rst: rtl8211f-rst { 295 66 rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 296 67 }; 297 68 }; 69 + 70 + usb { 71 + vcc5v0_host_en: vcc5v0-host-en { 72 + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 73 + }; 74 + }; 75 + 76 + wifibt { 77 + wl_reset: wl-reset { 78 + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; 79 + }; 80 + 81 + wl_dis: wl-dis { 82 + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>; 83 + }; 84 + 85 + wl_wake_host: wl-wake-host { 86 + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 87 + }; 88 + 89 + bt_dis: bt-dis { 90 + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; 91 + }; 92 + 93 + bt_wake_host: bt-wake-host { 94 + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 95 + }; 96 + }; 97 + }; 98 + 99 + &pwm3 { 100 + pinctrl-names = "default"; 101 + pinctrl-0 = <&pwm3m1_pins>; 102 + status = "okay"; 103 + }; 104 + 105 + &saradc { 106 + vref-supply = <&avcc_1v8_s0>; 107 + status = "okay"; 298 108 }; 299 109 300 110 &sdhci { ··· 353 61 no-sdio; 354 62 no-sd; 355 63 non-removable; 356 - max-frequency = <200000000>; 357 64 mmc-hs400-1_8v; 358 65 mmc-hs400-enhanced-strobe; 359 66 status = "okay"; 360 67 }; 361 68 69 + &sdmmc { 70 + bus-width = <4>; 71 + cap-mmc-highspeed; 72 + cap-sd-highspeed; 73 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 74 + disable-wp; 75 + max-frequency = <150000000>; 76 + no-sdio; 77 + no-mmc; 78 + sd-uhs-sdr104; 79 + vmmc-supply = <&vcc_3v3_s0>; 80 + vqmmc-supply = <&vccio_sd_s0>; 81 + status = "okay"; 82 + }; 83 + 84 + &spi2 { 85 + status = "okay"; 86 + assigned-clocks = <&cru CLK_SPI2>; 87 + assigned-clock-rates = <200000000>; 88 + num-cs = <1>; 89 + pinctrl-names = "default"; 90 + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 91 + 92 + pmic@0 { 93 + compatible = "rockchip,rk806"; 94 + reg = <0x0>; 95 + interrupt-parent = <&gpio0>; 96 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 97 + pinctrl-names = "default"; 98 + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 99 + <&rk806_dvs2_null>, <&rk806_dvs3_null>; 100 + spi-max-frequency = <1000000>; 101 + 102 + vcc1-supply = <&vcc5v0_sys>; 103 + vcc2-supply = <&vcc5v0_sys>; 104 + vcc3-supply = <&vcc5v0_sys>; 105 + vcc4-supply = <&vcc5v0_sys>; 106 + vcc5-supply = <&vcc5v0_sys>; 107 + vcc6-supply = <&vcc5v0_sys>; 108 + vcc7-supply = <&vcc5v0_sys>; 109 + vcc8-supply = <&vcc5v0_sys>; 110 + vcc9-supply = <&vcc5v0_sys>; 111 + vcc10-supply = <&vcc5v0_sys>; 112 + vcc11-supply = <&vcc_2v0_pldo_s3>; 113 + vcc12-supply = <&vcc5v0_sys>; 114 + vcc13-supply = <&vcc_1v1_nldo_s3>; 115 + vcc14-supply = <&vcc_1v1_nldo_s3>; 116 + vcca-supply = <&vcc5v0_sys>; 117 + 118 + gpio-controller; 119 + #gpio-cells = <2>; 120 + 121 + rk806_dvs1_null: dvs1-null-pins { 122 + pins = "gpio_pwrctrl2"; 123 + function = "pin_fun0"; 124 + }; 125 + 126 + rk806_dvs2_null: dvs2-null-pins { 127 + pins = "gpio_pwrctrl2"; 128 + function = "pin_fun0"; 129 + }; 130 + 131 + rk806_dvs3_null: dvs3-null-pins { 132 + pins = "gpio_pwrctrl3"; 133 + function = "pin_fun0"; 134 + }; 135 + 136 + regulators { 137 + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { 138 + regulator-name = "vdd_gpu_s0"; 139 + regulator-boot-on; 140 + regulator-min-microvolt = <550000>; 141 + regulator-max-microvolt = <950000>; 142 + regulator-ramp-delay = <12500>; 143 + regulator-enable-ramp-delay = <400>; 144 + 145 + regulator-state-mem { 146 + regulator-off-in-suspend; 147 + }; 148 + }; 149 + 150 + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { 151 + regulator-name = "vdd_cpu_lit_s0"; 152 + regulator-always-on; 153 + regulator-boot-on; 154 + regulator-min-microvolt = <550000>; 155 + regulator-max-microvolt = <950000>; 156 + regulator-ramp-delay = <12500>; 157 + 158 + regulator-state-mem { 159 + regulator-off-in-suspend; 160 + }; 161 + }; 162 + 163 + vdd_log_s0: dcdc-reg3 { 164 + regulator-name = "vdd_log_s0"; 165 + regulator-always-on; 166 + regulator-boot-on; 167 + regulator-min-microvolt = <675000>; 168 + regulator-max-microvolt = <750000>; 169 + regulator-ramp-delay = <12500>; 170 + 171 + regulator-state-mem { 172 + regulator-off-in-suspend; 173 + regulator-suspend-microvolt = <750000>; 174 + }; 175 + }; 176 + 177 + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { 178 + regulator-name = "vdd_vdenc_s0"; 179 + regulator-always-on; 180 + regulator-boot-on; 181 + regulator-min-microvolt = <550000>; 182 + regulator-max-microvolt = <950000>; 183 + regulator-ramp-delay = <12500>; 184 + 185 + regulator-state-mem { 186 + regulator-off-in-suspend; 187 + }; 188 + }; 189 + 190 + vdd_ddr_s0: dcdc-reg5 { 191 + regulator-name = "vdd_ddr_s0"; 192 + regulator-always-on; 193 + regulator-boot-on; 194 + regulator-min-microvolt = <675000>; 195 + regulator-max-microvolt = <900000>; 196 + regulator-ramp-delay = <12500>; 197 + 198 + regulator-state-mem { 199 + regulator-off-in-suspend; 200 + regulator-suspend-microvolt = <850000>; 201 + }; 202 + }; 203 + 204 + vdd2_ddr_s3: dcdc-reg6 { 205 + regulator-name = "vdd2_ddr_s3"; 206 + regulator-always-on; 207 + regulator-boot-on; 208 + 209 + regulator-state-mem { 210 + regulator-on-in-suspend; 211 + }; 212 + }; 213 + 214 + vcc_2v0_pldo_s3: dcdc-reg7 { 215 + regulator-name = "vdd_2v0_pldo_s3"; 216 + regulator-always-on; 217 + regulator-boot-on; 218 + regulator-min-microvolt = <2000000>; 219 + regulator-max-microvolt = <2000000>; 220 + regulator-ramp-delay = <12500>; 221 + 222 + regulator-state-mem { 223 + regulator-on-in-suspend; 224 + regulator-suspend-microvolt = <2000000>; 225 + }; 226 + }; 227 + 228 + vcc_3v3_s3: dcdc-reg8 { 229 + regulator-name = "vcc_3v3_s3"; 230 + regulator-always-on; 231 + regulator-boot-on; 232 + regulator-min-microvolt = <3300000>; 233 + regulator-max-microvolt = <3300000>; 234 + 235 + regulator-state-mem { 236 + regulator-on-in-suspend; 237 + regulator-suspend-microvolt = <3300000>; 238 + }; 239 + }; 240 + 241 + vddq_ddr_s0: dcdc-reg9 { 242 + regulator-name = "vddq_ddr_s0"; 243 + regulator-always-on; 244 + regulator-boot-on; 245 + 246 + regulator-state-mem { 247 + regulator-off-in-suspend; 248 + }; 249 + }; 250 + 251 + vcc_1v8_s3: dcdc-reg10 { 252 + regulator-name = "vcc_1v8_s3"; 253 + regulator-always-on; 254 + regulator-boot-on; 255 + regulator-min-microvolt = <1800000>; 256 + regulator-max-microvolt = <1800000>; 257 + 258 + regulator-state-mem { 259 + regulator-on-in-suspend; 260 + regulator-suspend-microvolt = <1800000>; 261 + }; 262 + }; 263 + 264 + avcc_1v8_s0: pldo-reg1 { 265 + regulator-name = "avcc_1v8_s0"; 266 + regulator-always-on; 267 + regulator-boot-on; 268 + regulator-min-microvolt = <1800000>; 269 + regulator-max-microvolt = <1800000>; 270 + 271 + regulator-state-mem { 272 + regulator-off-in-suspend; 273 + }; 274 + }; 275 + 276 + vcc_1v8_s0: pldo-reg2 { 277 + regulator-name = "vcc_1v8_s0"; 278 + regulator-always-on; 279 + regulator-boot-on; 280 + regulator-min-microvolt = <1800000>; 281 + regulator-max-microvolt = <1800000>; 282 + 283 + regulator-state-mem { 284 + regulator-off-in-suspend; 285 + regulator-suspend-microvolt = <1800000>; 286 + }; 287 + }; 288 + 289 + avdd_1v2_s0: pldo-reg3 { 290 + regulator-name = "avdd_1v2_s0"; 291 + regulator-always-on; 292 + regulator-boot-on; 293 + regulator-min-microvolt = <1200000>; 294 + regulator-max-microvolt = <1200000>; 295 + 296 + regulator-state-mem { 297 + regulator-off-in-suspend; 298 + }; 299 + }; 300 + 301 + vcc_3v3_s0: pldo-reg4 { 302 + regulator-name = "vcc_3v3_s0"; 303 + regulator-always-on; 304 + regulator-boot-on; 305 + regulator-min-microvolt = <3300000>; 306 + regulator-max-microvolt = <3300000>; 307 + regulator-ramp-delay = <12500>; 308 + 309 + regulator-state-mem { 310 + regulator-off-in-suspend; 311 + }; 312 + }; 313 + 314 + vccio_sd_s0: pldo-reg5 { 315 + regulator-name = "vccio_sd_s0"; 316 + regulator-always-on; 317 + regulator-boot-on; 318 + regulator-min-microvolt = <1800000>; 319 + regulator-max-microvolt = <3300000>; 320 + regulator-ramp-delay = <12500>; 321 + 322 + regulator-state-mem { 323 + regulator-off-in-suspend; 324 + }; 325 + }; 326 + 327 + pldo6_s3: pldo-reg6 { 328 + regulator-name = "pldo6_s3"; 329 + regulator-always-on; 330 + regulator-boot-on; 331 + regulator-min-microvolt = <1800000>; 332 + regulator-max-microvolt = <1800000>; 333 + 334 + regulator-state-mem { 335 + regulator-on-in-suspend; 336 + regulator-suspend-microvolt = <1800000>; 337 + }; 338 + }; 339 + 340 + vdd_0v75_s3: nldo-reg1 { 341 + regulator-name = "vdd_0v75_s3"; 342 + regulator-always-on; 343 + regulator-boot-on; 344 + regulator-min-microvolt = <750000>; 345 + regulator-max-microvolt = <750000>; 346 + 347 + regulator-state-mem { 348 + regulator-on-in-suspend; 349 + regulator-suspend-microvolt = <750000>; 350 + }; 351 + }; 352 + 353 + vdd_ddr_pll_s0: nldo-reg2 { 354 + regulator-name = "vdd_ddr_pll_s0"; 355 + regulator-always-on; 356 + regulator-boot-on; 357 + regulator-min-microvolt = <850000>; 358 + regulator-max-microvolt = <850000>; 359 + 360 + regulator-state-mem { 361 + regulator-off-in-suspend; 362 + regulator-suspend-microvolt = <850000>; 363 + }; 364 + }; 365 + 366 + avdd_0v75_s0: nldo-reg3 { 367 + regulator-name = "avdd_0v75_s0"; 368 + regulator-always-on; 369 + regulator-boot-on; 370 + regulator-min-microvolt = <750000>; 371 + regulator-max-microvolt = <750000>; 372 + 373 + regulator-state-mem { 374 + regulator-off-in-suspend; 375 + }; 376 + }; 377 + 378 + vdd_0v85_s0: nldo-reg4 { 379 + regulator-name = "vdd_0v85_s0"; 380 + regulator-always-on; 381 + regulator-boot-on; 382 + regulator-min-microvolt = <850000>; 383 + regulator-max-microvolt = <850000>; 384 + 385 + regulator-state-mem { 386 + regulator-off-in-suspend; 387 + }; 388 + }; 389 + 390 + vdd_0v75_s0: nldo-reg5 { 391 + regulator-name = "vdd_0v75_s0"; 392 + regulator-always-on; 393 + regulator-boot-on; 394 + regulator-min-microvolt = <750000>; 395 + regulator-max-microvolt = <750000>; 396 + 397 + regulator-state-mem { 398 + regulator-off-in-suspend; 399 + }; 400 + }; 401 + }; 402 + }; 403 + }; 404 + 405 + &u2phy2 { 406 + status = "okay"; 407 + }; 408 + 409 + &u2phy2_host { 410 + status = "okay"; 411 + phy-supply = <&vcc5v0_host>; 412 + }; 413 + 414 + &u2phy3 { 415 + status = "okay"; 416 + }; 417 + 418 + &u2phy3_host { 419 + phy-supply = <&vcc5v0_host>; 420 + status = "okay"; 421 + }; 422 + 362 423 &uart2 { 363 424 pinctrl-0 = <&uart2m0_xfer>; 425 + status = "okay"; 426 + }; 427 + 428 + &usb_host0_ehci { 429 + status = "okay"; 430 + pinctrl-names = "default"; 431 + pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>; 432 + }; 433 + 434 + &usb_host0_ohci { 435 + status = "okay"; 436 + }; 437 + 438 + &usb_host1_ehci { 439 + status = "okay"; 440 + }; 441 + 442 + &usb_host1_ohci { 364 443 status = "okay"; 365 444 };

+286

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

··· 8 8 #include <dt-bindings/interrupt-controller/irq.h> 9 9 #include <dt-bindings/power/rk3588-power.h> 10 10 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 + #include <dt-bindings/phy/phy.h> 12 + #include <dt-bindings/ata/ahci.h> 11 13 12 14 / { 13 15 compatible = "rockchip,rk3588"; ··· 399 397 }; 400 398 }; 401 399 400 + usb_host0_ehci: usb@fc800000 { 401 + compatible = "rockchip,rk3588-ehci", "generic-ehci"; 402 + reg = <0x0 0xfc800000 0x0 0x40000>; 403 + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 404 + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 405 + phys = <&u2phy2_host>; 406 + phy-names = "usb"; 407 + power-domains = <&power RK3588_PD_USB>; 408 + status = "disabled"; 409 + }; 410 + 411 + usb_host0_ohci: usb@fc840000 { 412 + compatible = "rockchip,rk3588-ohci", "generic-ohci"; 413 + reg = <0x0 0xfc840000 0x0 0x40000>; 414 + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 415 + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 416 + phys = <&u2phy2_host>; 417 + phy-names = "usb"; 418 + power-domains = <&power RK3588_PD_USB>; 419 + status = "disabled"; 420 + }; 421 + 422 + usb_host1_ehci: usb@fc880000 { 423 + compatible = "rockchip,rk3588-ehci", "generic-ehci"; 424 + reg = <0x0 0xfc880000 0x0 0x40000>; 425 + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 426 + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 427 + phys = <&u2phy3_host>; 428 + phy-names = "usb"; 429 + power-domains = <&power RK3588_PD_USB>; 430 + status = "disabled"; 431 + }; 432 + 433 + usb_host1_ohci: usb@fc8c0000 { 434 + compatible = "rockchip,rk3588-ohci", "generic-ohci"; 435 + reg = <0x0 0xfc8c0000 0x0 0x40000>; 436 + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 437 + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 438 + phys = <&u2phy3_host>; 439 + phy-names = "usb"; 440 + power-domains = <&power RK3588_PD_USB>; 441 + status = "disabled"; 442 + }; 443 + 402 444 sys_grf: syscon@fd58c000 { 403 445 compatible = "rockchip,rk3588-sys-grf", "syscon"; 404 446 reg = <0x0 0xfd58c000 0x0 0x1000>; ··· 451 405 php_grf: syscon@fd5b0000 { 452 406 compatible = "rockchip,rk3588-php-grf", "syscon"; 453 407 reg = <0x0 0xfd5b0000 0x0 0x1000>; 408 + }; 409 + 410 + pipe_phy0_grf: syscon@fd5bc000 { 411 + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 412 + reg = <0x0 0xfd5bc000 0x0 0x100>; 413 + }; 414 + 415 + pipe_phy2_grf: syscon@fd5c4000 { 416 + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 417 + reg = <0x0 0xfd5c4000 0x0 0x100>; 418 + }; 419 + 420 + usb2phy2_grf: syscon@fd5d8000 { 421 + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 422 + reg = <0x0 0xfd5d8000 0x0 0x4000>; 423 + #address-cells = <1>; 424 + #size-cells = <1>; 425 + 426 + u2phy2: usb2-phy@8000 { 427 + compatible = "rockchip,rk3588-usb2phy"; 428 + reg = <0x8000 0x10>; 429 + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 430 + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 431 + reset-names = "phy", "apb"; 432 + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 433 + clock-names = "phyclk"; 434 + clock-output-names = "usb480m_phy2"; 435 + #clock-cells = <0>; 436 + status = "disabled"; 437 + 438 + u2phy2_host: host-port { 439 + #phy-cells = <0>; 440 + status = "disabled"; 441 + }; 442 + }; 443 + }; 444 + 445 + usb2phy3_grf: syscon@fd5dc000 { 446 + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 447 + reg = <0x0 0xfd5dc000 0x0 0x4000>; 448 + #address-cells = <1>; 449 + #size-cells = <1>; 450 + 451 + u2phy3: usb2-phy@c000 { 452 + compatible = "rockchip,rk3588-usb2phy"; 453 + reg = <0xc000 0x10>; 454 + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 455 + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 456 + reset-names = "phy", "apb"; 457 + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 458 + clock-names = "phyclk"; 459 + clock-output-names = "usb480m_phy3"; 460 + #clock-cells = <0>; 461 + status = "disabled"; 462 + 463 + u2phy3_host: host-port { 464 + #phy-cells = <0>; 465 + status = "disabled"; 466 + }; 467 + }; 454 468 }; 455 469 456 470 ioc: syscon@fd5f0000 { ··· 1227 1121 reg = <0x0 0xfdf82200 0x0 0x20>; 1228 1122 }; 1229 1123 1124 + pcie2x1l1: pcie@fe180000 { 1125 + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1126 + bus-range = <0x30 0x3f>; 1127 + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1128 + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1129 + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1130 + clock-names = "aclk_mst", "aclk_slv", 1131 + "aclk_dbi", "pclk", 1132 + "aux", "pipe"; 1133 + device_type = "pci"; 1134 + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1135 + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1136 + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1137 + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1138 + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1139 + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1140 + #interrupt-cells = <1>; 1141 + interrupt-map-mask = <0 0 0 7>; 1142 + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1143 + <0 0 0 2 &pcie2x1l1_intc 1>, 1144 + <0 0 0 3 &pcie2x1l1_intc 2>, 1145 + <0 0 0 4 &pcie2x1l1_intc 3>; 1146 + linux,pci-domain = <3>; 1147 + max-link-speed = <2>; 1148 + msi-map = <0x3000 &its0 0x3000 0x1000>; 1149 + num-lanes = <1>; 1150 + phys = <&combphy2_psu PHY_TYPE_PCIE>; 1151 + phy-names = "pcie-phy"; 1152 + power-domains = <&power RK3588_PD_PCIE>; 1153 + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1154 + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1155 + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1156 + reg = <0xa 0x40c00000 0x0 0x00400000>, 1157 + <0x0 0xfe180000 0x0 0x00010000>, 1158 + <0x0 0xf3000000 0x0 0x00100000>; 1159 + reg-names = "dbi", "apb", "config"; 1160 + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1161 + reset-names = "pwr", "pipe"; 1162 + #address-cells = <3>; 1163 + #size-cells = <2>; 1164 + status = "disabled"; 1165 + 1166 + pcie2x1l1_intc: legacy-interrupt-controller { 1167 + interrupt-controller; 1168 + #address-cells = <0>; 1169 + #interrupt-cells = <1>; 1170 + interrupt-parent = <&gic>; 1171 + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1172 + }; 1173 + }; 1174 + 1175 + pcie2x1l2: pcie@fe190000 { 1176 + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1177 + bus-range = <0x40 0x4f>; 1178 + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1179 + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1180 + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1181 + clock-names = "aclk_mst", "aclk_slv", 1182 + "aclk_dbi", "pclk", 1183 + "aux", "pipe"; 1184 + device_type = "pci"; 1185 + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1186 + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1187 + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1188 + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1189 + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1190 + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1191 + #interrupt-cells = <1>; 1192 + interrupt-map-mask = <0 0 0 7>; 1193 + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1194 + <0 0 0 2 &pcie2x1l2_intc 1>, 1195 + <0 0 0 3 &pcie2x1l2_intc 2>, 1196 + <0 0 0 4 &pcie2x1l2_intc 3>; 1197 + linux,pci-domain = <4>; 1198 + max-link-speed = <2>; 1199 + msi-map = <0x4000 &its0 0x4000 0x1000>; 1200 + num-lanes = <1>; 1201 + phys = <&combphy0_ps PHY_TYPE_PCIE>; 1202 + phy-names = "pcie-phy"; 1203 + power-domains = <&power RK3588_PD_PCIE>; 1204 + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1205 + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1206 + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1207 + reg = <0xa 0x41000000 0x0 0x00400000>, 1208 + <0x0 0xfe190000 0x0 0x00010000>, 1209 + <0x0 0xf4000000 0x0 0x00100000>; 1210 + reg-names = "dbi", "apb", "config"; 1211 + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1212 + reset-names = "pwr", "pipe"; 1213 + #address-cells = <3>; 1214 + #size-cells = <2>; 1215 + status = "disabled"; 1216 + 1217 + pcie2x1l2_intc: legacy-interrupt-controller { 1218 + interrupt-controller; 1219 + #address-cells = <0>; 1220 + #interrupt-cells = <1>; 1221 + interrupt-parent = <&gic>; 1222 + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1223 + }; 1224 + }; 1225 + 1230 1226 gmac1: ethernet@fe1c0000 { 1231 1227 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1232 1228 reg = <0x0 0xfe1c0000 0x0 0x10000>; ··· 1375 1167 snps,tx-queues-to-use = <2>; 1376 1168 queue0 {}; 1377 1169 queue1 {}; 1170 + }; 1171 + }; 1172 + 1173 + sata0: sata@fe210000 { 1174 + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1175 + reg = <0 0xfe210000 0 0x1000>; 1176 + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1177 + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1178 + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1179 + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1180 + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1181 + ports-implemented = <0x1>; 1182 + #address-cells = <1>; 1183 + #size-cells = <0>; 1184 + status = "disabled"; 1185 + 1186 + sata-port@0 { 1187 + reg = <0>; 1188 + hba-port-cap = <HBA_PORT_FBSCP>; 1189 + phys = <&combphy0_ps PHY_TYPE_SATA>; 1190 + phy-names = "sata-phy"; 1191 + snps,rx-ts-max = <32>; 1192 + snps,tx-ts-max = <32>; 1193 + }; 1194 + }; 1195 + 1196 + sata2: sata@fe230000 { 1197 + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1198 + reg = <0 0xfe230000 0 0x1000>; 1199 + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1200 + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1201 + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1202 + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1203 + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1204 + ports-implemented = <0x1>; 1205 + #address-cells = <1>; 1206 + #size-cells = <0>; 1207 + status = "disabled"; 1208 + 1209 + sata-port@0 { 1210 + reg = <0>; 1211 + hba-port-cap = <HBA_PORT_FBSCP>; 1212 + phys = <&combphy2_psu PHY_TYPE_SATA>; 1213 + phy-names = "sata-phy"; 1214 + snps,rx-ts-max = <32>; 1215 + snps,tx-ts-max = <32>; 1378 1216 }; 1379 1217 }; 1380 1218 ··· 2195 1941 clocks = <&cru ACLK_DMAC2>; 2196 1942 clock-names = "apb_pclk"; 2197 1943 #dma-cells = <1>; 1944 + }; 1945 + 1946 + combphy0_ps: phy@fee00000 { 1947 + compatible = "rockchip,rk3588-naneng-combphy"; 1948 + reg = <0x0 0xfee00000 0x0 0x100>; 1949 + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 1950 + <&cru PCLK_PHP_ROOT>; 1951 + clock-names = "ref", "apb", "pipe"; 1952 + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 1953 + assigned-clock-rates = <100000000>; 1954 + #phy-cells = <1>; 1955 + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 1956 + reset-names = "phy", "apb"; 1957 + rockchip,pipe-grf = <&php_grf>; 1958 + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 1959 + status = "disabled"; 1960 + }; 1961 + 1962 + combphy2_psu: phy@fee20000 { 1963 + compatible = "rockchip,rk3588-naneng-combphy"; 1964 + reg = <0x0 0xfee20000 0x0 0x100>; 1965 + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 1966 + <&cru PCLK_PHP_ROOT>; 1967 + clock-names = "ref", "apb", "pipe"; 1968 + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 1969 + assigned-clock-rates = <100000000>; 1970 + #phy-cells = <1>; 1971 + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 1972 + reset-names = "phy", "apb"; 1973 + rockchip,pipe-grf = <&php_grf>; 1974 + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 1975 + status = "disabled"; 2198 1976 }; 2199 1977 2200 1978 system_sram2: sram@ff001000 {

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