tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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i2c: tegra: Add support for Tegra410

Add support for the Tegra410 SoC, which has 4 I2C controllers. The
controllers are feature-equivalent to Tegra264; only the register
offsets differ.

Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260324055843.549808-4-kkartik@nvidia.com

authored by

Kartik Rajput and committed by
Andi Shyti 59717f26 0c0e440b

+63
+63
drivers/i2c/busses/i2c-tegra.c
··· 275 275 .sw_mutex = 0x0ec, 276 276 }; 277 277 278 + static const struct tegra_i2c_regs tegra410_i2c_regs = { 279 + .cnfg = 0x000, 280 + .status = 0x01c, 281 + .sl_cnfg = 0x020, 282 + .sl_addr1 = 0x02c, 283 + .sl_addr2 = 0x030, 284 + .tx_fifo = 0x054, 285 + .rx_fifo = 0x058, 286 + .packet_transfer_status = 0x05c, 287 + .fifo_control = 0x060, 288 + .fifo_status = 0x064, 289 + .int_mask = 0x068, 290 + .int_status = 0x06c, 291 + .clk_divisor = 0x070, 292 + .bus_clear_cnfg = 0x088, 293 + .bus_clear_status = 0x08c, 294 + .config_load = 0x090, 295 + .clken_override = 0x094, 296 + .interface_timing_0 = 0x098, 297 + .interface_timing_1 = 0x09c, 298 + .hs_interface_timing_0 = 0x0a0, 299 + .hs_interface_timing_1 = 0x0a4, 300 + .master_reset_cntrl = 0x0ac, 301 + .mst_fifo_control = 0x0b8, 302 + .mst_fifo_status = 0x0bc, 303 + .sw_mutex = 0x0f0, 304 + }; 305 + 278 306 /* 279 307 * msg_end_type: The bus control which needs to be sent at end of transfer. 280 308 * @MSG_END_STOP: Send stop pulse. ··· 2113 2085 .regs = &tegra264_i2c_regs, 2114 2086 }; 2115 2087 2088 + static const struct tegra_i2c_hw_feature tegra410_i2c_hw = { 2089 + .has_continue_xfer_support = true, 2090 + .has_per_pkt_xfer_complete_irq = true, 2091 + .clk_divisor_hs_mode = 1, 2092 + .clk_divisor_std_mode = 0x3f, 2093 + .clk_divisor_fast_mode = 0x2c, 2094 + .clk_divisor_fast_plus_mode = 0x11, 2095 + .has_config_load_reg = true, 2096 + .has_multi_master_mode = true, 2097 + .has_slcg_override_reg = true, 2098 + .has_mst_fifo = true, 2099 + .has_mst_reset = true, 2100 + .quirks = &tegra194_i2c_quirks, 2101 + .supports_bus_clear = true, 2102 + .has_apb_dma = false, 2103 + .tlow_std_mode = 0x8, 2104 + .thigh_std_mode = 0x7, 2105 + .tlow_fast_mode = 0x2, 2106 + .thigh_fast_mode = 0x2, 2107 + .tlow_fastplus_mode = 0x2, 2108 + .thigh_fastplus_mode = 0x2, 2109 + .tlow_hs_mode = 0x8, 2110 + .thigh_hs_mode = 0x6, 2111 + .setup_hold_time_std_mode = 0x08080808, 2112 + .setup_hold_time_fast_mode = 0x02020202, 2113 + .setup_hold_time_fastplus_mode = 0x02020202, 2114 + .setup_hold_time_hs_mode = 0x0b0b0b, 2115 + .has_interface_timing_reg = true, 2116 + .enable_hs_mode_support = true, 2117 + .has_mutex = true, 2118 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 2119 + .regs = &tegra410_i2c_regs, 2120 + }; 2121 + 2116 2122 static const struct of_device_id tegra_i2c_of_match[] = { 2117 2123 { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, }, 2118 2124 { .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, }, ··· 2457 2395 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 2458 2396 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 2459 2397 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 2398 + {.id = "NVDA2017", .driver_data = (kernel_ulong_t)&tegra410_i2c_hw}, 2460 2399 { } 2461 2400 }; 2462 2401 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);