Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1
Add clock and reset entries for GBETH instances. Include core clocks for
PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
used as clock sources for the GBETH IP.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250509160121.331073-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Lad Prabhakar
and committed by
Geert Uytterhoeven
598b2a06
899e7ede
+71
+64
drivers/clk/renesas/r9a09g057-cpg.c
+64
drivers/clk/renesas/r9a09g057-cpg.c
···
29
29
CLK_PLLDTY,
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CLK_PLLCA55,
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CLK_PLLVDO,
32
+
CLK_PLLETH,
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CLK_PLLGPU,
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/* Internal Core Clocks */
···
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CLK_PLLVDO_CRU1,
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CLK_PLLVDO_CRU2,
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CLK_PLLVDO_CRU3,
52
+
CLK_PLLETH_DIV_250_FIX,
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+
CLK_PLLETH_DIV_125_FIX,
54
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CLK_CSDIV_PLLETH_GBE0,
55
+
CLK_CSDIV_PLLETH_GBE1,
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CLK_SMUX2_GBE0_TXCLK,
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CLK_SMUX2_GBE0_RXCLK,
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CLK_SMUX2_GBE1_TXCLK,
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+
CLK_SMUX2_GBE1_RXCLK,
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CLK_PLLGPU_GEAR,
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/* Module Clocks */
···
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{0, 0},
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};
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+
static const struct clk_div_table dtable_2_100[] = {
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{0, 2},
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{1, 10},
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{2, 100},
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{0, 0},
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+
};
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+
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/* Mux clock tables */
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static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
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+
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
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+
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
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static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
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+
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static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
···
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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+
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
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DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
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/* Internal Core Clocks */
···
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DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
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DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
140
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+
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
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DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
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+
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
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CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
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+
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
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CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
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+
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
125
+
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
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+
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
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+
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
128
+
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DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
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/* Core Clocks */
···
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DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
165
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DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
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DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
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+
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I,
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I,
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
···
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BUS_MSTOP(7, BIT(10))),
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DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
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BUS_MSTOP(7, BIT(11))),
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+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
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BUS_MSTOP(8, BIT(5)), 1),
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+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
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BUS_MSTOP(8, BIT(5)), 1),
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+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
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BUS_MSTOP(8, BIT(5)), 1),
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+
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
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+
BUS_MSTOP(8, BIT(5))),
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+
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
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+
BUS_MSTOP(8, BIT(5))),
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+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
249
+
BUS_MSTOP(8, BIT(6)), 1),
250
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
251
+
BUS_MSTOP(8, BIT(6)), 1),
252
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DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
253
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BUS_MSTOP(8, BIT(6)), 1),
254
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
255
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BUS_MSTOP(8, BIT(6)), 1),
256
+
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
257
+
BUS_MSTOP(8, BIT(6))),
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+
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
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BUS_MSTOP(8, BIT(6))),
274
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DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
275
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
366
304
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
367
305
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
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DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
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+
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
370
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+7
drivers/clk/renesas/rzv2h-cpg.h
+7
drivers/clk/renesas/rzv2h-cpg.h
···
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93
.width = (_width), \
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})
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+
#define CPG_SSEL0 (0x300)
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#define CPG_SSEL1 (0x304)
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#define CPG_CDDIV0 (0x400)
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#define CPG_CDDIV1 (0x404)
···
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#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
115
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#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
116
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+
#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
117
+
#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
117
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#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
118
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+
#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
121
+
#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
122
+
#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1)
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+
#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
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#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
120
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#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
121
126