Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: rzg2l: Remove DSI clock rate restrictions
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Tested-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251124131003.992554-2-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Chris Brandt
and committed by
Geert Uytterhoeven
5a4326f2
879e9fc8
+154
-31
+143
-31
drivers/clk/renesas/rzg2l-cpg.c
+143
-31
drivers/clk/renesas/rzg2l-cpg.c
···
22
22
#include <linux/device.h>
23
23
#include <linux/init.h>
24
24
#include <linux/iopoll.h>
25
+
#include <linux/math64.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
···
74
73
75
74
#define MSTOP_OFF(conf) FIELD_GET(GENMASK(31, 16), (conf))
76
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#define MSTOP_MASK(conf) FIELD_GET(GENMASK(15, 0), (conf))
76
+
77
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#define PLL5_FOUTVCO_MIN 800000000
78
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#define PLL5_FOUTVCO_MAX 3000000000
79
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#define PLL5_POSTDIV_MIN 1
80
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#define PLL5_POSTDIV_MAX 7
81
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#define PLL5_REFDIV_MIN 1
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#define PLL5_REFDIV_MAX 2
83
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#define PLL5_INTIN_MIN 20
84
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#define PLL5_INTIN_MAX 320
85
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#define PLL5_HSCLK_MIN 10000000
86
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#define PLL5_HSCLK_MAX 187500000
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/**
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* struct clk_hw_data - clock hardware data
···
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u8 pl5_spread;
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};
143
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132
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/* PLL5 output will be used for DPI or MIPI-DSI */
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static int dsi_div_target = PLL5_TARGET_DPI;
134
+
135
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/* Required division ratio for MIPI D-PHY clock depending on number of lanes and bpp. */
136
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static u8 dsi_div_ab_desired;
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+
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struct rzg2l_pll5_mux_dsi_div_param {
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u8 clksrc;
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u8 dsi_div_a;
···
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struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
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};
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static inline u8 rzg2l_cpg_div_ab(u8 a, u8 b)
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{
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return (b + 1) << a;
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}
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static void rzg2l_cpg_del_clk_provider(void *data)
192
179
{
···
579
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return clk_hw->clk;
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}
581
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+
/*
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* VCO-->[POSTDIV1,2]--FOUTPOSTDIV--------------->|
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* | |-->[1/(DSI DIV A * B)]--> MIPI_DSI_VCLK
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* |-->[1/2]--FOUT1PH0-->|
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* |
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* |------->[1/16]--------------------------------> hsclk (MIPI-PHY)
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*/
582
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static unsigned long
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rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
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rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_cpg_priv *priv,
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struct rzg2l_pll5_param *params,
584
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unsigned long rate)
585
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{
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-
unsigned long foutpostdiv_rate, foutvco_rate;
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const u32 extal_hz = EXTAL_FREQ_IN_MEGA_HZ * MEGA;
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unsigned long foutpostdiv_rate;
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unsigned int a, b, odd;
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unsigned long hsclk;
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u8 dsi_div_ab_calc;
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u64 foutvco_rate;
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-
params->pl5_intin = rate / MEGA;
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-
params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA);
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params->pl5_refdiv = 2;
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-
params->pl5_postdiv1 = 1;
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-
params->pl5_postdiv2 = 1;
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if (dsi_div_target == PLL5_TARGET_DSI) {
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/* Check hsclk */
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hsclk = rate * dsi_div_ab_desired / 16;
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if (hsclk < PLL5_HSCLK_MIN || hsclk > PLL5_HSCLK_MAX) {
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dev_err(priv->dev, "hsclk out of range\n");
583
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return 0;
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}
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+
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/* Determine the correct clock source based on even/odd of the divider */
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odd = dsi_div_ab_desired & 1;
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if (odd) {
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priv->mux_dsi_div_params.clksrc = 0; /* FOUTPOSTDIV */
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dsi_div_ab_calc = dsi_div_ab_desired;
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} else {
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priv->mux_dsi_div_params.clksrc = 1; /* FOUT1PH0 */
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dsi_div_ab_calc = dsi_div_ab_desired / 2;
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}
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/* Calculate the DIV_DSI_A and DIV_DSI_B based on the desired divider */
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for (a = 0; a < 4; a++) {
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/* FOUT1PH0: Max output of DIV_DSI_A is 750MHz so at least 1/2 to be safe */
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if (!odd && a == 0)
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continue;
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/* FOUTPOSTDIV: DIV_DSI_A must always be 1/1 */
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if (odd && a != 0)
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break;
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+
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for (b = 0; b < 16; b++) {
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/* FOUTPOSTDIV: DIV_DSI_B must always be odd divider 1/(b+1) */
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if (odd && b & 1)
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continue;
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if (rzg2l_cpg_div_ab(a, b) == dsi_div_ab_calc) {
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priv->mux_dsi_div_params.dsi_div_a = a;
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priv->mux_dsi_div_params.dsi_div_b = b;
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goto calc_pll_clk;
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}
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}
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}
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dev_err(priv->dev, "Failed to calculate DIV_DSI_A,B\n");
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return 0;
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} else if (dsi_div_target == PLL5_TARGET_DPI) {
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/* Fixed settings for DPI */
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priv->mux_dsi_div_params.clksrc = 0;
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priv->mux_dsi_div_params.dsi_div_a = 3; /* Divided by 8 */
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priv->mux_dsi_div_params.dsi_div_b = 0; /* Divided by 1 */
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dsi_div_ab_desired = rzg2l_cpg_div_ab(priv->mux_dsi_div_params.dsi_div_a,
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priv->mux_dsi_div_params.dsi_div_b);
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}
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+
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calc_pll_clk:
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/* PLL5 (MIPI_DSI_PLLCLK) = VCO / POSTDIV1 / POSTDIV2 */
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for (params->pl5_postdiv1 = PLL5_POSTDIV_MIN;
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params->pl5_postdiv1 <= PLL5_POSTDIV_MAX;
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params->pl5_postdiv1++) {
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for (params->pl5_postdiv2 = PLL5_POSTDIV_MIN;
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params->pl5_postdiv2 <= PLL5_POSTDIV_MAX;
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params->pl5_postdiv2++) {
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foutvco_rate = rate * params->pl5_postdiv1 * params->pl5_postdiv2 *
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dsi_div_ab_desired;
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if (foutvco_rate <= PLL5_FOUTVCO_MIN || foutvco_rate >= PLL5_FOUTVCO_MAX)
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continue;
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for (params->pl5_refdiv = PLL5_REFDIV_MIN;
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params->pl5_refdiv <= PLL5_REFDIV_MAX;
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params->pl5_refdiv++) {
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u32 rem;
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params->pl5_intin = div_u64_rem(foutvco_rate * params->pl5_refdiv,
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extal_hz, &rem);
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if (params->pl5_intin < PLL5_INTIN_MIN ||
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params->pl5_intin > PLL5_INTIN_MAX)
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continue;
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params->pl5_fracin = div_u64((u64)rem << 24, extal_hz);
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goto clk_valid;
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}
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}
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}
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dev_err(priv->dev, "Failed to calculate PLL5 settings\n");
664
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return 0;
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clk_valid:
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params->pl5_spread = 0x16;
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foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,
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(params->pl5_intin << 24) + params->pl5_fracin),
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params->pl5_refdiv) >> 24;
598
-
foutpostdiv_rate = DIV_ROUND_CLOSEST(foutvco_rate,
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params->pl5_postdiv1 * params->pl5_postdiv2);
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foutpostdiv_rate = DIV_U64_ROUND_CLOSEST(foutvco_rate,
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params->pl5_postdiv1 * params->pl5_postdiv2);
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return foutpostdiv_rate;
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}
···
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struct rzg2l_pll5_param params;
728
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unsigned long parent_rate;
729
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parent_rate = rzg2l_cpg_get_foutpostdiv_rate(¶ms, rate);
610
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parent_rate = rzg2l_cpg_get_foutpostdiv_rate(priv, ¶ms, rate);
731
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if (priv->mux_dsi_div_params.clksrc)
733
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parent_rate /= 2;
···
743
623
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req->best_parent_rate = rzg2l_cpg_get_vclk_parent_rate(hw, req->rate);
745
625
626
+
if (!req->best_parent_rate)
627
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return -EINVAL;
628
+
746
629
return 0;
747
630
}
631
+
632
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void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target)
633
+
{
634
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dsi_div_ab_desired = divider;
635
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dsi_div_target = target;
636
+
}
637
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EXPORT_SYMBOL_GPL(rzg2l_cpg_dsi_div_set_divider);
748
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749
639
static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
750
640
unsigned long rate,
···
926
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927
797
#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
928
798
929
-
static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw,
930
-
unsigned long rate)
931
-
{
932
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struct sipll5 *sipll5 = to_sipll5(hw);
933
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struct rzg2l_cpg_priv *priv = sipll5->priv;
934
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unsigned long vclk;
935
-
936
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vclk = rate / ((1 << priv->mux_dsi_div_params.dsi_div_a) *
937
-
(priv->mux_dsi_div_params.dsi_div_b + 1));
938
-
939
-
if (priv->mux_dsi_div_params.clksrc)
940
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vclk /= 2;
941
-
942
-
return vclk;
943
-
}
944
-
945
799
static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
946
800
unsigned long parent_rate)
947
801
{
···
970
856
if (!rate)
971
857
return -EINVAL;
972
858
973
-
vclk_rate = rzg2l_cpg_get_vclk_rate(hw, rate);
859
+
vclk_rate = rate / dsi_div_ab_desired;
974
860
sipll5->foutpostdiv_rate =
975
-
rzg2l_cpg_get_foutpostdiv_rate(¶ms, vclk_rate);
861
+
rzg2l_cpg_get_foutpostdiv_rate(priv, ¶ms, vclk_rate);
976
862
977
863
/* Put PLL5 into standby mode */
978
864
writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
···
1059
945
if (ret)
1060
946
return ERR_PTR(ret);
1061
947
1062
-
priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */
1063
-
priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */
1064
-
priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */
948
+
rzg2l_cpg_dsi_div_set_divider(8, PLL5_TARGET_DPI);
1065
949
1066
950
return clk_hw->clk;
1067
951
}
+11
include/linux/clk/renesas.h
+11
include/linux/clk/renesas.h
···
35
35
#define cpg_mssr_detach_dev NULL
36
36
#endif
37
37
38
+
enum {
39
+
PLL5_TARGET_DPI,
40
+
PLL5_TARGET_DSI
41
+
};
42
+
43
+
#ifdef CONFIG_CLK_RZG2L
44
+
void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target);
45
+
#else
46
+
static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
47
+
#endif
48
+
38
49
/**
39
50
* struct rzv2h_pll_limits - PLL parameter constraints
40
51
*