drm/amdgpu: add xcc index argument to soc15_grbm_select

+5 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

··· 50 50 uint32_t queue, uint32_t vmid) 51 51 { 52 52 mutex_lock(&adev->srbm_mutex); 53 - soc15_grbm_select(adev, mec, pipe, queue, vmid); 53 + soc15_grbm_select(adev, mec, pipe, queue, vmid, 0); 54 54 } 55 55 56 56 static void unlock_srbm(struct amdgpu_device *adev) 57 57 { 58 - soc15_grbm_select(adev, 0, 0, 0, 0); 58 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 59 59 mutex_unlock(&adev->srbm_mutex); 60 60 } 61 61 ··· 700 700 *wave_cnt = 0; 701 701 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; 702 702 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; 703 - soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0); 703 + soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, 0); 704 704 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) + 705 705 queue_slot); 706 706 *wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; ··· 772 772 DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES); 773 773 774 774 lock_spi_csq_mutexes(adev); 775 - soc15_grbm_select(adev, 1, 0, 0, 0); 775 + soc15_grbm_select(adev, 1, 0, 0, 0, 0); 776 776 777 777 /* 778 778 * Iterate through the shader engines and arrays of the device ··· 821 821 } 822 822 823 823 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 824 - soc15_grbm_select(adev, 0, 0, 0, 0); 824 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 825 825 unlock_spi_csq_mutexes(adev); 826 826 827 827 /* Update the output parameters and return */

+13 -13

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 1831 1831 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1832 1832 u32 me, u32 pipe, u32 q, u32 vm) 1833 1833 { 1834 - soc15_grbm_select(adev, me, pipe, q, vm); 1834 + soc15_grbm_select(adev, me, pipe, q, vm, 0); 1835 1835 } 1836 1836 1837 1837 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { ··· 2324 2324 2325 2325 mutex_lock(&adev->srbm_mutex); 2326 2326 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2327 - soc15_grbm_select(adev, 0, 0, 0, i); 2327 + soc15_grbm_select(adev, 0, 0, 0, i, 0); 2328 2328 /* CP and shaders */ 2329 2329 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2330 2330 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2331 2331 } 2332 - soc15_grbm_select(adev, 0, 0, 0, 0); 2332 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 2333 2333 mutex_unlock(&adev->srbm_mutex); 2334 2334 2335 2335 /* Initialize all compute VMIDs to have no GDS, GWS, or OA ··· 2394 2394 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2395 2395 mutex_lock(&adev->srbm_mutex); 2396 2396 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2397 - soc15_grbm_select(adev, 0, 0, 0, i); 2397 + soc15_grbm_select(adev, 0, 0, 0, i, 0); 2398 2398 /* CP and shaders */ 2399 2399 if (i == 0) { 2400 2400 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, ··· 2416 2416 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2417 2417 } 2418 2418 } 2419 - soc15_grbm_select(adev, 0, 0, 0, 0); 2419 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 2420 2420 2421 2421 mutex_unlock(&adev->srbm_mutex); 2422 2422 ··· 3540 3540 amdgpu_ring_clear_ring(ring); 3541 3541 3542 3542 mutex_lock(&adev->srbm_mutex); 3543 - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3543 + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3544 3544 gfx_v9_0_kiq_init_register(ring); 3545 - soc15_grbm_select(adev, 0, 0, 0, 0); 3545 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3546 3546 mutex_unlock(&adev->srbm_mutex); 3547 3547 } else { 3548 3548 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); ··· 3551 3551 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3552 3552 amdgpu_ring_clear_ring(ring); 3553 3553 mutex_lock(&adev->srbm_mutex); 3554 - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3554 + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3555 3555 gfx_v9_0_mqd_init(ring); 3556 3556 gfx_v9_0_kiq_init_register(ring); 3557 - soc15_grbm_select(adev, 0, 0, 0, 0); 3557 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3558 3558 mutex_unlock(&adev->srbm_mutex); 3559 3559 3560 3560 if (adev->gfx.kiq[0].mqd_backup) ··· 3582 3582 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3583 3583 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3584 3584 mutex_lock(&adev->srbm_mutex); 3585 - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3585 + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3586 3586 gfx_v9_0_mqd_init(ring); 3587 - soc15_grbm_select(adev, 0, 0, 0, 0); 3587 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3588 3588 mutex_unlock(&adev->srbm_mutex); 3589 3589 3590 3590 if (adev->gfx.mec.mqd_backup[mqd_idx]) ··· 3791 3791 mutex_lock(&adev->srbm_mutex); 3792 3792 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, 3793 3793 adev->gfx.kiq[0].ring.pipe, 3794 - adev->gfx.kiq[0].ring.queue, 0); 3794 + adev->gfx.kiq[0].ring.queue, 0, 0); 3795 3795 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); 3796 - soc15_grbm_select(adev, 0, 0, 0, 0); 3796 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3797 3797 mutex_unlock(&adev->srbm_mutex); 3798 3798 } 3799 3799

+2 -2

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

··· 761 761 762 762 for (i = first_vmid; i < last_vmid; i++) { 763 763 data = 0; 764 - soc15_grbm_select(adev, 0, 0, 0, i); 764 + soc15_grbm_select(adev, 0, 0, 0, i, 0); 765 765 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 766 766 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); 767 767 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, ··· 769 769 WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data); 770 770 } 771 771 772 - soc15_grbm_select(adev, 0, 0, 0, 0); 772 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 773 773 mutex_unlock(&adev->srbm_mutex); 774 774 } 775 775

+13 -13

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

··· 658 658 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 659 659 u32 me, u32 pipe, u32 q, u32 vm) 660 660 { 661 - soc15_grbm_select(adev, me, pipe, q, vm); 661 + soc15_grbm_select(adev, me, pipe, q, vm, 0); 662 662 } 663 663 664 664 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { ··· 926 926 927 927 mutex_lock(&adev->srbm_mutex); 928 928 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 929 - soc15_grbm_select(adev, 0, 0, 0, i); 929 + soc15_grbm_select(adev, 0, 0, 0, i, 0); 930 930 /* CP and shaders */ 931 931 WREG32_SOC15_RLC(GC, 0, regSH_MEM_CONFIG, sh_mem_config); 932 932 WREG32_SOC15_RLC(GC, 0, regSH_MEM_BASES, sh_mem_bases); 933 933 } 934 - soc15_grbm_select(adev, 0, 0, 0, 0); 934 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 935 935 mutex_unlock(&adev->srbm_mutex); 936 936 937 937 /* Initialize all compute VMIDs to have no GDS, GWS, or OA ··· 977 977 /* where to put LDS, scratch, GPUVM in FSA64 space */ 978 978 mutex_lock(&adev->srbm_mutex); 979 979 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 980 - soc15_grbm_select(adev, 0, 0, 0, i); 980 + soc15_grbm_select(adev, 0, 0, 0, i, 0); 981 981 /* CP and shaders */ 982 982 if (i == 0) { 983 983 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, ··· 999 999 WREG32_SOC15_RLC(GC, 0, regSH_MEM_BASES, tmp); 1000 1000 } 1001 1001 } 1002 - soc15_grbm_select(adev, 0, 0, 0, 0); 1002 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1003 1003 1004 1004 mutex_unlock(&adev->srbm_mutex); 1005 1005 ··· 1706 1706 amdgpu_ring_clear_ring(ring); 1707 1707 1708 1708 mutex_lock(&adev->srbm_mutex); 1709 - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 1709 + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 1710 1710 gfx_v9_4_3_kiq_init_register(ring); 1711 - soc15_grbm_select(adev, 0, 0, 0, 0); 1711 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1712 1712 mutex_unlock(&adev->srbm_mutex); 1713 1713 } else { 1714 1714 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1715 1715 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1716 1716 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1717 1717 mutex_lock(&adev->srbm_mutex); 1718 - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 1718 + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 1719 1719 gfx_v9_4_3_mqd_init(ring); 1720 1720 gfx_v9_4_3_kiq_init_register(ring); 1721 - soc15_grbm_select(adev, 0, 0, 0, 0); 1721 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1722 1722 mutex_unlock(&adev->srbm_mutex); 1723 1723 1724 1724 if (adev->gfx.kiq[0].mqd_backup) ··· 1746 1746 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1747 1747 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1748 1748 mutex_lock(&adev->srbm_mutex); 1749 - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 1749 + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 1750 1750 gfx_v9_4_3_mqd_init(ring); 1751 - soc15_grbm_select(adev, 0, 0, 0, 0); 1751 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1752 1752 mutex_unlock(&adev->srbm_mutex); 1753 1753 1754 1754 if (adev->gfx.mec.mqd_backup[mqd_idx]) ··· 1896 1896 mutex_lock(&adev->srbm_mutex); 1897 1897 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, 1898 1898 adev->gfx.kiq[0].ring.pipe, 1899 - adev->gfx.kiq[0].ring.queue, 0); 1899 + adev->gfx.kiq[0].ring.queue, 0, 0); 1900 1900 gfx_v9_4_3_kiq_fini_register(&adev->gfx.kiq[0].ring); 1901 - soc15_grbm_select(adev, 0, 0, 0, 0); 1901 + soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1902 1902 mutex_unlock(&adev->srbm_mutex); 1903 1903 } 1904 1904

+2 -2

drivers/gpu/drm/amd/amdgpu/soc15.c

··· 311 311 312 312 313 313 void soc15_grbm_select(struct amdgpu_device *adev, 314 - u32 me, u32 pipe, u32 queue, u32 vmid) 314 + u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 315 315 { 316 316 u32 grbm_gfx_cntl = 0; 317 317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); ··· 319 319 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 320 320 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 321 321 322 - WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 322 + WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 323 323 } 324 324 325 325 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)

+1 -1

drivers/gpu/drm/amd/amdgpu/soc15.h

··· 100 100 #define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift) 101 101 102 102 void soc15_grbm_select(struct amdgpu_device *adev, 103 - u32 me, u32 pipe, u32 queue, u32 vmid); 103 + u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id); 104 104 void soc15_set_virt_ops(struct amdgpu_device *adev); 105 105 106 106 void soc15_program_register_sequence(struct amdgpu_device *adev,

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