Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: split gc v9_4_3 functionality from gc v9_0
To prepare for gc v9_4_3 specific feature.
v2: fix exports (Alex)
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Le Ma
and committed by
Alex Deucher
86301129
def799c6
+2634
-15
+2633
-13
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+2633
-13
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
···
25
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#include "vega10_enum.h"
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+
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#include "clearstate_gfx9.h"
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#include "v9_structs.h"
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+
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#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
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#include "gc/gc_9_4_3_offset.h"
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#include "gc/gc_9_4_3_sh_mask.h"
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#include "gfx_v9_4_3.h"
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MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
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MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
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+
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#define GFX9_MEC_HPD_SIZE 4096
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#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
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static const struct soc15_reg_golden golden_settings_gc_9_4_3[] = {
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};
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static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
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static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
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static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
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static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
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static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
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struct amdgpu_cu_info *cu_info);
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+
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static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
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uint64_t queue_mask)
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{
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
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amdgpu_ring_write(kiq_ring,
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PACKET3_SET_RESOURCES_VMID_MASK(0) |
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/* vmid_mask:0* queue_type:0 (KIQ) */
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PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
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amdgpu_ring_write(kiq_ring,
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lower_32_bits(queue_mask)); /* queue mask lo */
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amdgpu_ring_write(kiq_ring,
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upper_32_bits(queue_mask)); /* queue mask hi */
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amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
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amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
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amdgpu_ring_write(kiq_ring, 0); /* oac mask */
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amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
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}
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static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = kiq_ring->adev;
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uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
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uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
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/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
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amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
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PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
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PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
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PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
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PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
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PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
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/*queue_type: normal compute queue */
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PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
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/* alloc format: all_on_one_pipe */
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PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
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PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
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/* num_queues: must be 1 */
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PACKET3_MAP_QUEUES_NUM_QUEUES(1));
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amdgpu_ring_write(kiq_ring,
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PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
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amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
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amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
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amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
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amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
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}
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+
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static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring,
110
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enum amdgpu_unmap_queues_action action,
111
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u64 gpu_addr, u64 seq)
112
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{
113
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uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
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+
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
116
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amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
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PACKET3_UNMAP_QUEUES_ACTION(action) |
118
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PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
119
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PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
120
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PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
121
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amdgpu_ring_write(kiq_ring,
122
+
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
123
+
124
+
if (action == PREEMPT_QUEUES_NO_UNMAP) {
125
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amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
126
+
amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
127
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amdgpu_ring_write(kiq_ring, seq);
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} else {
129
+
amdgpu_ring_write(kiq_ring, 0);
130
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amdgpu_ring_write(kiq_ring, 0);
131
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amdgpu_ring_write(kiq_ring, 0);
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+
}
133
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}
134
+
135
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static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
136
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struct amdgpu_ring *ring,
137
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u64 addr,
138
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u64 seq)
139
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{
140
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uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
141
+
142
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
143
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amdgpu_ring_write(kiq_ring,
144
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PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
145
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PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
146
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PACKET3_QUERY_STATUS_COMMAND(2));
147
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/* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
148
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amdgpu_ring_write(kiq_ring,
149
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PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
150
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PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
151
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amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
152
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amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
153
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amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
154
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amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
155
+
}
156
+
157
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static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
158
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uint16_t pasid, uint32_t flush_type,
159
+
bool all_hub)
160
+
{
161
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
162
+
amdgpu_ring_write(kiq_ring,
163
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PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
164
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PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
165
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PACKET3_INVALIDATE_TLBS_PASID(pasid) |
166
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PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
167
+
}
168
+
169
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static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
170
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.kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
171
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.kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
172
+
.kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
173
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.kiq_query_status = gfx_v9_4_3_kiq_query_status,
174
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.kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
175
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.set_resources_size = 8,
176
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.map_queues_size = 7,
177
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.unmap_queues_size = 6,
178
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.query_status_size = 7,
179
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.invalidate_tlbs_size = 2,
180
+
};
181
+
182
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static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
183
+
{
184
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adev->gfx.kiq[0].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
185
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}
186
+
187
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static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
188
+
{
189
+
190
+
}
191
+
192
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static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
193
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bool wc, uint32_t reg, uint32_t val)
194
+
{
195
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
196
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amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
197
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WRITE_DATA_DST_SEL(0) |
198
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(wc ? WR_CONFIRM : 0));
199
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amdgpu_ring_write(ring, reg);
200
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amdgpu_ring_write(ring, 0);
201
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amdgpu_ring_write(ring, val);
202
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}
203
+
204
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static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
205
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int mem_space, int opt, uint32_t addr0,
206
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uint32_t addr1, uint32_t ref, uint32_t mask,
207
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uint32_t inv)
208
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{
209
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
210
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amdgpu_ring_write(ring,
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/* memory (1) or register (0) */
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(WAIT_REG_MEM_MEM_SPACE(mem_space) |
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WAIT_REG_MEM_OPERATION(opt) | /* wait */
214
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WAIT_REG_MEM_FUNCTION(3) | /* equal */
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WAIT_REG_MEM_ENGINE(eng_sel)));
216
+
217
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if (mem_space)
218
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BUG_ON(addr0 & 0x3); /* Dword align */
219
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amdgpu_ring_write(ring, addr0);
220
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amdgpu_ring_write(ring, addr1);
221
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amdgpu_ring_write(ring, ref);
222
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amdgpu_ring_write(ring, mask);
223
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amdgpu_ring_write(ring, inv); /* poll interval */
224
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}
225
+
226
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static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
227
+
{
228
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struct amdgpu_device *adev = ring->adev;
229
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uint32_t tmp = 0;
230
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unsigned i;
231
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int r;
232
+
233
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WREG32_SOC15(GC, 0, regSCRATCH_REG0, 0xCAFEDEAD);
234
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r = amdgpu_ring_alloc(ring, 3);
235
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if (r)
236
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return r;
237
+
238
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amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
239
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amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0) -
240
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PACKET3_SET_UCONFIG_REG_START);
241
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amdgpu_ring_write(ring, 0xDEADBEEF);
242
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amdgpu_ring_commit(ring);
243
+
244
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for (i = 0; i < adev->usec_timeout; i++) {
245
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tmp = RREG32_SOC15(GC, 0, regSCRATCH_REG0);
246
+
if (tmp == 0xDEADBEEF)
247
+
break;
248
+
udelay(1);
249
+
}
250
+
251
+
if (i >= adev->usec_timeout)
252
+
r = -ETIMEDOUT;
253
+
return r;
254
+
}
255
+
256
+
static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
257
+
{
258
+
struct amdgpu_device *adev = ring->adev;
259
+
struct amdgpu_ib ib;
260
+
struct dma_fence *f = NULL;
261
+
262
+
unsigned index;
263
+
uint64_t gpu_addr;
264
+
uint32_t tmp;
265
+
long r;
266
+
267
+
r = amdgpu_device_wb_get(adev, &index);
268
+
if (r)
269
+
return r;
270
+
271
+
gpu_addr = adev->wb.gpu_addr + (index * 4);
272
+
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
273
+
memset(&ib, 0, sizeof(ib));
274
+
r = amdgpu_ib_get(adev, NULL, 16,
275
+
AMDGPU_IB_POOL_DIRECT, &ib);
276
+
if (r)
277
+
goto err1;
278
+
279
+
ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
280
+
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
281
+
ib.ptr[2] = lower_32_bits(gpu_addr);
282
+
ib.ptr[3] = upper_32_bits(gpu_addr);
283
+
ib.ptr[4] = 0xDEADBEEF;
284
+
ib.length_dw = 5;
285
+
286
+
r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
287
+
if (r)
288
+
goto err2;
289
+
290
+
r = dma_fence_wait_timeout(f, false, timeout);
291
+
if (r == 0) {
292
+
r = -ETIMEDOUT;
293
+
goto err2;
294
+
} else if (r < 0) {
295
+
goto err2;
296
+
}
297
+
298
+
tmp = adev->wb.wb[index];
299
+
if (tmp == 0xDEADBEEF)
300
+
r = 0;
301
+
else
302
+
r = -EINVAL;
303
+
304
+
err2:
305
+
amdgpu_ib_free(adev, &ib, NULL);
306
+
dma_fence_put(f);
307
+
err1:
308
+
amdgpu_device_wb_free(adev, index);
309
+
return r;
310
+
}
311
+
312
+
313
+
/* This value might differs per partition */
38
314
static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
39
315
{
40
316
uint64_t clock;
···
324
48
amdgpu_gfx_off_ctrl(adev, true);
325
49
326
50
return clock;
51
+
}
52
+
53
+
static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
54
+
{
55
+
amdgpu_ucode_release(&adev->gfx.pfp_fw);
56
+
amdgpu_ucode_release(&adev->gfx.me_fw);
57
+
amdgpu_ucode_release(&adev->gfx.ce_fw);
58
+
amdgpu_ucode_release(&adev->gfx.rlc_fw);
59
+
amdgpu_ucode_release(&adev->gfx.mec_fw);
60
+
amdgpu_ucode_release(&adev->gfx.mec2_fw);
61
+
62
+
kfree(adev->gfx.rlc.register_list_format);
63
+
}
64
+
65
+
static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
66
+
const char *chip_name)
67
+
{
68
+
char fw_name[30];
69
+
int err;
70
+
const struct rlc_firmware_header_v2_0 *rlc_hdr;
71
+
uint16_t version_major;
72
+
uint16_t version_minor;
73
+
74
+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
75
+
76
+
err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
77
+
if (err)
78
+
goto out;
79
+
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
80
+
81
+
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
82
+
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
83
+
err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
84
+
out:
85
+
if (err)
86
+
amdgpu_ucode_release(&adev->gfx.rlc_fw);
87
+
88
+
return err;
89
+
}
90
+
91
+
static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
92
+
{
93
+
return true;
94
+
}
95
+
96
+
static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
97
+
{
98
+
if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
99
+
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
100
+
}
101
+
102
+
static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
103
+
const char *chip_name)
104
+
{
105
+
char fw_name[30];
106
+
int err;
107
+
108
+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
109
+
110
+
err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
111
+
if (err)
112
+
goto out;
113
+
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
114
+
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
115
+
116
+
adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
117
+
adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
118
+
119
+
gfx_v9_4_3_check_if_need_gfxoff(adev);
120
+
121
+
out:
122
+
if (err)
123
+
amdgpu_ucode_release(&adev->gfx.mec_fw);
124
+
return err;
125
+
}
126
+
127
+
static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
128
+
{
129
+
const char *chip_name;
130
+
int r;
131
+
132
+
chip_name = "gc_9_4_3";
133
+
134
+
r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);
135
+
if (r)
136
+
return r;
137
+
138
+
r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);
139
+
if (r)
140
+
return r;
141
+
142
+
return r;
143
+
}
144
+
145
+
static u32 gfx_v9_4_3_get_csb_size(struct amdgpu_device *adev)
146
+
{
147
+
u32 count = 0;
148
+
const struct cs_section_def *sect = NULL;
149
+
const struct cs_extent_def *ext = NULL;
150
+
151
+
/* begin clear state */
152
+
count += 2;
153
+
/* context control state */
154
+
count += 3;
155
+
156
+
for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
157
+
for (ext = sect->section; ext->extent != NULL; ++ext) {
158
+
if (sect->id == SECT_CONTEXT)
159
+
count += 2 + ext->reg_count;
160
+
else
161
+
return 0;
162
+
}
163
+
}
164
+
165
+
/* end clear state */
166
+
count += 2;
167
+
/* clear state */
168
+
count += 2;
169
+
170
+
return count;
171
+
}
172
+
173
+
static void gfx_v9_4_3_get_csb_buffer(struct amdgpu_device *adev,
174
+
volatile u32 *buffer)
175
+
{
176
+
u32 count = 0, i;
177
+
const struct cs_section_def *sect = NULL;
178
+
const struct cs_extent_def *ext = NULL;
179
+
180
+
if (adev->gfx.rlc.cs_data == NULL)
181
+
return;
182
+
if (buffer == NULL)
183
+
return;
184
+
185
+
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
186
+
buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
187
+
188
+
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
189
+
buffer[count++] = cpu_to_le32(0x80000000);
190
+
buffer[count++] = cpu_to_le32(0x80000000);
191
+
192
+
for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
193
+
for (ext = sect->section; ext->extent != NULL; ++ext) {
194
+
if (sect->id == SECT_CONTEXT) {
195
+
buffer[count++] =
196
+
cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
197
+
buffer[count++] = cpu_to_le32(ext->reg_index -
198
+
PACKET3_SET_CONTEXT_REG_START);
199
+
for (i = 0; i < ext->reg_count; i++)
200
+
buffer[count++] = cpu_to_le32(ext->extent[i]);
201
+
} else {
202
+
return;
203
+
}
204
+
}
205
+
}
206
+
207
+
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
208
+
buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
209
+
210
+
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
211
+
buffer[count++] = cpu_to_le32(0);
212
+
}
213
+
214
+
static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
215
+
{
216
+
amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
217
+
amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
218
+
}
219
+
220
+
static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
221
+
{
222
+
int r, i;
223
+
u32 *hpd;
224
+
const __le32 *fw_data;
225
+
unsigned fw_size;
226
+
u32 *fw;
227
+
size_t mec_hpd_size;
228
+
229
+
const struct gfx_firmware_header_v1_0 *mec_hdr;
230
+
231
+
bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
232
+
233
+
/* take ownership of the relevant compute queues */
234
+
amdgpu_gfx_compute_queue_acquire(adev);
235
+
mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
236
+
if (mec_hpd_size) {
237
+
r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
238
+
AMDGPU_GEM_DOMAIN_VRAM,
239
+
&adev->gfx.mec.hpd_eop_obj,
240
+
&adev->gfx.mec.hpd_eop_gpu_addr,
241
+
(void **)&hpd);
242
+
if (r) {
243
+
dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
244
+
gfx_v9_4_3_mec_fini(adev);
245
+
return r;
246
+
}
247
+
248
+
if (amdgpu_emu_mode == 1) {
249
+
for (i = 0; i < mec_hpd_size / 4; i++) {
250
+
memset((void *)(hpd + i), 0, 4);
251
+
if (i % 50 == 0)
252
+
msleep(1);
253
+
}
254
+
} else {
255
+
memset(hpd, 0, mec_hpd_size);
256
+
}
257
+
258
+
amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
259
+
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
260
+
}
261
+
262
+
mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
263
+
264
+
fw_data = (const __le32 *)
265
+
(adev->gfx.mec_fw->data +
266
+
le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
267
+
fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
268
+
269
+
r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
270
+
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
271
+
&adev->gfx.mec.mec_fw_obj,
272
+
&adev->gfx.mec.mec_fw_gpu_addr,
273
+
(void **)&fw);
274
+
if (r) {
275
+
dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
276
+
gfx_v9_4_3_mec_fini(adev);
277
+
return r;
278
+
}
279
+
280
+
memcpy(fw, fw_data, fw_size);
281
+
282
+
amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
283
+
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
284
+
285
+
return 0;
327
286
}
328
287
329
288
static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev,
···
661
150
soc15_grbm_select(adev, me, pipe, q, vm);
662
151
}
663
152
153
+
static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
154
+
.get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
155
+
.select_se_sh = &gfx_v9_4_3_select_se_sh,
156
+
.read_wave_data = &gfx_v9_4_3_read_wave_data,
157
+
.read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
158
+
.read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
159
+
.select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
160
+
};
161
+
162
+
static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
163
+
{
164
+
u32 gb_addr_config;
165
+
166
+
adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
167
+
168
+
switch (adev->ip_versions[GC_HWIP][0]) {
169
+
case IP_VERSION(9, 4, 3):
170
+
adev->gfx.config.max_hw_contexts = 8;
171
+
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
172
+
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
173
+
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
174
+
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
175
+
gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
176
+
break;
177
+
default:
178
+
BUG();
179
+
break;
180
+
}
181
+
182
+
adev->gfx.config.gb_addr_config = gb_addr_config;
183
+
184
+
adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
185
+
REG_GET_FIELD(
186
+
adev->gfx.config.gb_addr_config,
187
+
GB_ADDR_CONFIG,
188
+
NUM_PIPES);
189
+
190
+
adev->gfx.config.max_tile_pipes =
191
+
adev->gfx.config.gb_addr_config_fields.num_pipes;
192
+
193
+
adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
194
+
REG_GET_FIELD(
195
+
adev->gfx.config.gb_addr_config,
196
+
GB_ADDR_CONFIG,
197
+
NUM_BANKS);
198
+
adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
199
+
REG_GET_FIELD(
200
+
adev->gfx.config.gb_addr_config,
201
+
GB_ADDR_CONFIG,
202
+
MAX_COMPRESSED_FRAGS);
203
+
adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
204
+
REG_GET_FIELD(
205
+
adev->gfx.config.gb_addr_config,
206
+
GB_ADDR_CONFIG,
207
+
NUM_RB_PER_SE);
208
+
adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
209
+
REG_GET_FIELD(
210
+
adev->gfx.config.gb_addr_config,
211
+
GB_ADDR_CONFIG,
212
+
NUM_SHADER_ENGINES);
213
+
adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
214
+
REG_GET_FIELD(
215
+
adev->gfx.config.gb_addr_config,
216
+
GB_ADDR_CONFIG,
217
+
PIPE_INTERLEAVE_SIZE));
218
+
219
+
return 0;
220
+
}
221
+
222
+
static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
223
+
int mec, int pipe, int queue)
224
+
{
225
+
unsigned irq_type;
226
+
struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
227
+
unsigned int hw_prio;
228
+
229
+
ring = &adev->gfx.compute_ring[ring_id];
230
+
231
+
/* mec0 is me1 */
232
+
ring->me = mec + 1;
233
+
ring->pipe = pipe;
234
+
ring->queue = queue;
235
+
236
+
ring->ring_obj = NULL;
237
+
ring->use_doorbell = true;
238
+
ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
239
+
ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
240
+
+ (ring_id * GFX9_MEC_HPD_SIZE);
241
+
ring->vm_hub = AMDGPU_GFXHUB_0;
242
+
sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
243
+
244
+
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
245
+
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
246
+
+ ring->pipe;
247
+
hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
248
+
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
249
+
/* type-2 packets are deprecated on MEC, use type-3 instead */
250
+
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
251
+
hw_prio, NULL);
252
+
}
253
+
254
+
static int gfx_v9_4_3_sw_init(void *handle)
255
+
{
256
+
int i, j, k, r, ring_id;
257
+
struct amdgpu_kiq *kiq;
258
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
259
+
260
+
adev->gfx.mec.num_mec = 2;
261
+
adev->gfx.mec.num_pipe_per_mec = 4;
262
+
adev->gfx.mec.num_queue_per_pipe = 8;
263
+
264
+
/* EOP Event */
265
+
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
266
+
if (r)
267
+
return r;
268
+
269
+
/* Privileged reg */
270
+
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
271
+
&adev->gfx.priv_reg_irq);
272
+
if (r)
273
+
return r;
274
+
275
+
/* Privileged inst */
276
+
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
277
+
&adev->gfx.priv_inst_irq);
278
+
if (r)
279
+
return r;
280
+
281
+
adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
282
+
283
+
r = adev->gfx.rlc.funcs->init(adev);
284
+
if (r) {
285
+
DRM_ERROR("Failed to init rlc BOs!\n");
286
+
return r;
287
+
}
288
+
289
+
r = gfx_v9_4_3_mec_init(adev);
290
+
if (r) {
291
+
DRM_ERROR("Failed to init MEC BOs!\n");
292
+
return r;
293
+
}
294
+
295
+
/* set up the compute queues - allocate horizontally across pipes */
296
+
ring_id = 0;
297
+
for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
298
+
for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
299
+
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
300
+
if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
301
+
k, j))
302
+
continue;
303
+
304
+
r = gfx_v9_4_3_compute_ring_init(adev,
305
+
ring_id,
306
+
i, k, j);
307
+
if (r)
308
+
return r;
309
+
310
+
ring_id++;
311
+
}
312
+
}
313
+
}
314
+
315
+
r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0);
316
+
if (r) {
317
+
DRM_ERROR("Failed to init KIQ BOs!\n");
318
+
return r;
319
+
}
320
+
321
+
kiq = &adev->gfx.kiq[0];
322
+
r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
323
+
if (r)
324
+
return r;
325
+
326
+
/* create MQD for all compute queues as wel as KIQ for SRIOV case */
327
+
r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation), 0);
328
+
if (r)
329
+
return r;
330
+
331
+
r = gfx_v9_4_3_gpu_early_init(adev);
332
+
if (r)
333
+
return r;
334
+
335
+
return 0;
336
+
}
337
+
338
+
static int gfx_v9_4_3_sw_fini(void *handle)
339
+
{
340
+
int i;
341
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
342
+
343
+
for (i = 0; i < adev->gfx.num_compute_rings; i++)
344
+
amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
345
+
346
+
amdgpu_gfx_mqd_sw_fini(adev, 0);
347
+
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
348
+
amdgpu_gfx_kiq_fini(adev, 0);
349
+
350
+
gfx_v9_4_3_mec_fini(adev);
351
+
amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
352
+
gfx_v9_4_3_free_microcode(adev);
353
+
354
+
return 0;
355
+
}
356
+
357
+
static u32 gfx_v9_4_3_get_rb_active_bitmap(struct amdgpu_device *adev)
358
+
{
359
+
u32 data, mask;
360
+
361
+
data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
362
+
data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
363
+
364
+
data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
365
+
data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
366
+
367
+
mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
368
+
adev->gfx.config.max_sh_per_se);
369
+
370
+
return (~data) & mask;
371
+
}
372
+
373
+
static void gfx_v9_4_3_setup_rb(struct amdgpu_device *adev)
374
+
{
375
+
int i, j;
376
+
u32 data;
377
+
u32 active_rbs = 0;
378
+
u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
379
+
adev->gfx.config.max_sh_per_se;
380
+
381
+
mutex_lock(&adev->grbm_idx_mutex);
382
+
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
383
+
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
384
+
gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff);
385
+
data = gfx_v9_4_3_get_rb_active_bitmap(adev);
386
+
active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
387
+
rb_bitmap_width_per_sh);
388
+
}
389
+
}
390
+
gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
391
+
mutex_unlock(&adev->grbm_idx_mutex);
392
+
393
+
adev->gfx.config.backend_enable_mask = active_rbs;
394
+
adev->gfx.config.num_rbs = hweight32(active_rbs);
395
+
}
396
+
397
+
#define DEFAULT_SH_MEM_BASES (0x6000)
398
+
static void gfx_v9_4_3_init_compute_vmid(struct amdgpu_device *adev)
399
+
{
400
+
int i;
401
+
uint32_t sh_mem_config;
402
+
uint32_t sh_mem_bases;
403
+
404
+
/*
405
+
* Configure apertures:
406
+
* LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
407
+
* Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
408
+
* GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
409
+
*/
410
+
sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
411
+
412
+
sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
413
+
SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
414
+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
415
+
416
+
mutex_lock(&adev->srbm_mutex);
417
+
for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
418
+
soc15_grbm_select(adev, 0, 0, 0, i);
419
+
/* CP and shaders */
420
+
WREG32_SOC15_RLC(GC, 0, regSH_MEM_CONFIG, sh_mem_config);
421
+
WREG32_SOC15_RLC(GC, 0, regSH_MEM_BASES, sh_mem_bases);
422
+
}
423
+
soc15_grbm_select(adev, 0, 0, 0, 0);
424
+
mutex_unlock(&adev->srbm_mutex);
425
+
426
+
/* Initialize all compute VMIDs to have no GDS, GWS, or OA
427
+
acccess. These should be enabled by FW for target VMIDs. */
428
+
for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
429
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
430
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
431
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
432
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
433
+
}
434
+
}
435
+
436
+
static void gfx_v9_4_3_init_gds_vmid(struct amdgpu_device *adev)
437
+
{
438
+
int vmid;
439
+
440
+
/*
441
+
* Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
442
+
* access. Compute VMIDs should be enabled by FW for target VMIDs,
443
+
* the driver can enable them for graphics. VMID0 should maintain
444
+
* access so that HWS firmware can save/restore entries.
445
+
*/
446
+
for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
447
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
448
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
449
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
450
+
WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
451
+
}
452
+
}
453
+
454
+
static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
455
+
{
456
+
u32 tmp;
457
+
int i;
458
+
459
+
WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
460
+
461
+
gfx_v9_4_3_setup_rb(adev);
462
+
gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
463
+
adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, regDB_DEBUG2);
464
+
465
+
/* XXX SH_MEM regs */
466
+
/* where to put LDS, scratch, GPUVM in FSA64 space */
467
+
mutex_lock(&adev->srbm_mutex);
468
+
for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
469
+
soc15_grbm_select(adev, 0, 0, 0, i);
470
+
/* CP and shaders */
471
+
if (i == 0) {
472
+
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
473
+
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
474
+
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
475
+
!!adev->gmc.noretry);
476
+
WREG32_SOC15_RLC(GC, 0, regSH_MEM_CONFIG, tmp);
477
+
WREG32_SOC15_RLC(GC, 0, regSH_MEM_BASES, 0);
478
+
} else {
479
+
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
480
+
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
481
+
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
482
+
!!adev->gmc.noretry);
483
+
WREG32_SOC15_RLC(GC, 0, regSH_MEM_CONFIG, tmp);
484
+
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
485
+
(adev->gmc.private_aperture_start >> 48));
486
+
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
487
+
(adev->gmc.shared_aperture_start >> 48));
488
+
WREG32_SOC15_RLC(GC, 0, regSH_MEM_BASES, tmp);
489
+
}
490
+
}
491
+
soc15_grbm_select(adev, 0, 0, 0, 0);
492
+
493
+
mutex_unlock(&adev->srbm_mutex);
494
+
495
+
gfx_v9_4_3_init_compute_vmid(adev);
496
+
gfx_v9_4_3_init_gds_vmid(adev);
497
+
}
498
+
499
+
static void gfx_v9_4_3_enable_save_restore_machine(struct amdgpu_device *adev)
500
+
{
501
+
WREG32_FIELD15_PREREG(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
502
+
}
503
+
504
+
static void gfx_v9_4_3_init_csb(struct amdgpu_device *adev)
505
+
{
506
+
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
507
+
/* csib */
508
+
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, regRLC_CSIB_ADDR_HI),
509
+
adev->gfx.rlc.clear_state_gpu_addr >> 32);
510
+
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, regRLC_CSIB_ADDR_LO),
511
+
adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
512
+
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, regRLC_CSIB_LENGTH),
513
+
adev->gfx.rlc.clear_state_size);
514
+
}
515
+
516
+
static void gfx_v9_4_3_init_pg(struct amdgpu_device *adev)
517
+
{
518
+
gfx_v9_4_3_init_csb(adev);
519
+
520
+
/*
521
+
* Rlc save restore list is workable since v2_1.
522
+
* And it's needed by gfxoff feature.
523
+
*/
524
+
if (adev->gfx.rlc.is_rlc_v2_1)
525
+
gfx_v9_4_3_enable_save_restore_machine(adev);
526
+
527
+
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
528
+
AMD_PG_SUPPORT_GFX_SMG |
529
+
AMD_PG_SUPPORT_GFX_DMG |
530
+
AMD_PG_SUPPORT_CP |
531
+
AMD_PG_SUPPORT_GDS |
532
+
AMD_PG_SUPPORT_RLC_SMU_HS)) {
533
+
WREG32_SOC15(GC, 0, regRLC_JUMP_TABLE_RESTORE,
534
+
adev->gfx.rlc.cp_table_gpu_addr >> 8);
535
+
}
536
+
}
537
+
538
+
void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev)
539
+
{
540
+
uint32_t data;
541
+
542
+
data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
543
+
data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
544
+
WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
545
+
}
546
+
664
547
static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
665
548
{
666
549
uint32_t rlc_setting;
···
1094
189
1095
190
static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1096
191
{
192
+
const struct cs_section_def *cs_data;
193
+
int r;
194
+
195
+
adev->gfx.rlc.cs_data = gfx9_cs_data;
196
+
197
+
cs_data = adev->gfx.rlc.cs_data;
198
+
199
+
if (cs_data) {
200
+
/* init clear state block */
201
+
r = amdgpu_gfx_rlc_init_csb(adev);
202
+
if (r)
203
+
return r;
204
+
}
205
+
1097
206
/* init spm vmid with 0xf */
1098
207
if (adev->gfx.rlc.funcs->update_spm_vmid)
1099
208
adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
···
1165
246
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1166
247
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1167
248
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1168
-
if (adev->gfx.num_gfx_rings)
1169
-
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1170
249
1171
250
WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1172
251
}
···
1256
339
/* disable CG */
1257
340
WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
1258
341
1259
-
/* TODO: revisit pg function */
1260
-
/* gfx_v9_4_3_init_pg(adev);*/
342
+
gfx_v9_4_3_init_pg(adev);
1261
343
1262
344
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1263
345
/* legacy rlc firmware loading */
···
1323
407
ARRAY_SIZE(rlcg_access_gc_9_4_3));
1324
408
}
1325
409
1326
-
const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
1327
-
.get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
1328
-
.select_se_sh = &gfx_v9_4_3_select_se_sh,
1329
-
.read_wave_data = &gfx_v9_4_3_read_wave_data,
1330
-
.read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
1331
-
.read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
1332
-
.select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
1333
-
};
410
+
static void gfx_v9_4_3_cp_compute_enable(struct amdgpu_device *adev, bool enable)
411
+
{
412
+
if (enable) {
413
+
WREG32_SOC15_RLC(GC, 0, regCP_MEC_CNTL, 0);
414
+
} else {
415
+
WREG32_SOC15_RLC(GC, 0, regCP_MEC_CNTL,
416
+
(CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
417
+
adev->gfx.kiq[0].ring.sched.ready = false;
418
+
}
419
+
udelay(50);
420
+
}
1334
421
1335
-
const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
422
+
static int gfx_v9_4_3_cp_compute_load_microcode(struct amdgpu_device *adev)
423
+
{
424
+
const struct gfx_firmware_header_v1_0 *mec_hdr;
425
+
const __le32 *fw_data;
426
+
unsigned i;
427
+
u32 tmp;
428
+
u32 mec_ucode_addr_offset;
429
+
u32 mec_ucode_data_offset;
430
+
431
+
if (!adev->gfx.mec_fw)
432
+
return -EINVAL;
433
+
434
+
gfx_v9_4_3_cp_compute_enable(adev, false);
435
+
436
+
mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
437
+
amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
438
+
439
+
fw_data = (const __le32 *)
440
+
(adev->gfx.mec_fw->data +
441
+
le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
442
+
tmp = 0;
443
+
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
444
+
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
445
+
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
446
+
447
+
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
448
+
adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
449
+
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
450
+
upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
451
+
452
+
mec_ucode_addr_offset =
453
+
SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME1_UCODE_ADDR);
454
+
mec_ucode_data_offset =
455
+
SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME1_UCODE_DATA);
456
+
457
+
/* MEC1 */
458
+
WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
459
+
for (i = 0; i < mec_hdr->jt_size; i++)
460
+
WREG32(mec_ucode_data_offset,
461
+
le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
462
+
463
+
WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
464
+
/* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
465
+
466
+
return 0;
467
+
}
468
+
469
+
/* KIQ functions */
470
+
static void gfx_v9_4_3_kiq_setting(struct amdgpu_ring *ring)
471
+
{
472
+
uint32_t tmp;
473
+
struct amdgpu_device *adev = ring->adev;
474
+
475
+
/* tell RLC which is KIQ queue */
476
+
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
477
+
tmp &= 0xffffff00;
478
+
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
479
+
WREG32_SOC15_RLC(GC, 0, regRLC_CP_SCHEDULERS, tmp);
480
+
tmp |= 0x80;
481
+
WREG32_SOC15_RLC(GC, 0, regRLC_CP_SCHEDULERS, tmp);
482
+
}
483
+
484
+
static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
485
+
{
486
+
struct amdgpu_device *adev = ring->adev;
487
+
488
+
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
489
+
if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
490
+
mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
491
+
mqd->cp_hqd_queue_priority =
492
+
AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
493
+
}
494
+
}
495
+
}
496
+
497
+
static int gfx_v9_4_3_mqd_init(struct amdgpu_ring *ring)
498
+
{
499
+
struct amdgpu_device *adev = ring->adev;
500
+
struct v9_mqd *mqd = ring->mqd_ptr;
501
+
uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
502
+
uint32_t tmp;
503
+
504
+
mqd->header = 0xC0310800;
505
+
mqd->compute_pipelinestat_enable = 0x00000001;
506
+
mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
507
+
mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
508
+
mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
509
+
mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
510
+
mqd->compute_misc_reserved = 0x00000003;
511
+
512
+
mqd->dynamic_cu_mask_addr_lo =
513
+
lower_32_bits(ring->mqd_gpu_addr
514
+
+ offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
515
+
mqd->dynamic_cu_mask_addr_hi =
516
+
upper_32_bits(ring->mqd_gpu_addr
517
+
+ offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
518
+
519
+
eop_base_addr = ring->eop_gpu_addr >> 8;
520
+
mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
521
+
mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
522
+
523
+
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
524
+
tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
525
+
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
526
+
(order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
527
+
528
+
mqd->cp_hqd_eop_control = tmp;
529
+
530
+
/* enable doorbell? */
531
+
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
532
+
533
+
if (ring->use_doorbell) {
534
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
535
+
DOORBELL_OFFSET, ring->doorbell_index);
536
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
537
+
DOORBELL_EN, 1);
538
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
539
+
DOORBELL_SOURCE, 0);
540
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
541
+
DOORBELL_HIT, 0);
542
+
} else {
543
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
544
+
DOORBELL_EN, 0);
545
+
}
546
+
547
+
mqd->cp_hqd_pq_doorbell_control = tmp;
548
+
549
+
/* disable the queue if it's active */
550
+
ring->wptr = 0;
551
+
mqd->cp_hqd_dequeue_request = 0;
552
+
mqd->cp_hqd_pq_rptr = 0;
553
+
mqd->cp_hqd_pq_wptr_lo = 0;
554
+
mqd->cp_hqd_pq_wptr_hi = 0;
555
+
556
+
/* set the pointer to the MQD */
557
+
mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
558
+
mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
559
+
560
+
/* set MQD vmid to 0 */
561
+
tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
562
+
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
563
+
mqd->cp_mqd_control = tmp;
564
+
565
+
/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
566
+
hqd_gpu_addr = ring->gpu_addr >> 8;
567
+
mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
568
+
mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
569
+
570
+
/* set up the HQD, this is similar to CP_RB0_CNTL */
571
+
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
572
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
573
+
(order_base_2(ring->ring_size / 4) - 1));
574
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
575
+
((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
576
+
#ifdef __BIG_ENDIAN
577
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
578
+
#endif
579
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
580
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
581
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
582
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
583
+
mqd->cp_hqd_pq_control = tmp;
584
+
585
+
/* set the wb address whether it's enabled or not */
586
+
wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
587
+
mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
588
+
mqd->cp_hqd_pq_rptr_report_addr_hi =
589
+
upper_32_bits(wb_gpu_addr) & 0xffff;
590
+
591
+
/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
592
+
wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
593
+
mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
594
+
mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
595
+
596
+
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
597
+
ring->wptr = 0;
598
+
mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
599
+
600
+
/* set the vmid for the queue */
601
+
mqd->cp_hqd_vmid = 0;
602
+
603
+
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
604
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
605
+
mqd->cp_hqd_persistent_state = tmp;
606
+
607
+
/* set MIN_IB_AVAIL_SIZE */
608
+
tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
609
+
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
610
+
mqd->cp_hqd_ib_control = tmp;
611
+
612
+
/* set static priority for a queue/ring */
613
+
gfx_v9_4_3_mqd_set_priority(ring, mqd);
614
+
mqd->cp_hqd_quantum = RREG32(regCP_HQD_QUANTUM);
615
+
616
+
/* map_queues packet doesn't need activate the queue,
617
+
* so only kiq need set this field.
618
+
*/
619
+
if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
620
+
mqd->cp_hqd_active = 1;
621
+
622
+
return 0;
623
+
}
624
+
625
+
static int gfx_v9_4_3_kiq_init_register(struct amdgpu_ring *ring)
626
+
{
627
+
struct amdgpu_device *adev = ring->adev;
628
+
struct v9_mqd *mqd = ring->mqd_ptr;
629
+
int j;
630
+
631
+
/* disable wptr polling */
632
+
WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
633
+
634
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_EOP_BASE_ADDR,
635
+
mqd->cp_hqd_eop_base_addr_lo);
636
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
637
+
mqd->cp_hqd_eop_base_addr_hi);
638
+
639
+
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
640
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_EOP_CONTROL,
641
+
mqd->cp_hqd_eop_control);
642
+
643
+
/* enable doorbell? */
644
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
645
+
mqd->cp_hqd_pq_doorbell_control);
646
+
647
+
/* disable the queue if it's active */
648
+
if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
649
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
650
+
for (j = 0; j < adev->usec_timeout; j++) {
651
+
if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
652
+
break;
653
+
udelay(1);
654
+
}
655
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
656
+
mqd->cp_hqd_dequeue_request);
657
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_RPTR,
658
+
mqd->cp_hqd_pq_rptr);
659
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_LO,
660
+
mqd->cp_hqd_pq_wptr_lo);
661
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_HI,
662
+
mqd->cp_hqd_pq_wptr_hi);
663
+
}
664
+
665
+
/* set the pointer to the MQD */
666
+
WREG32_SOC15_RLC(GC, 0, regCP_MQD_BASE_ADDR,
667
+
mqd->cp_mqd_base_addr_lo);
668
+
WREG32_SOC15_RLC(GC, 0, regCP_MQD_BASE_ADDR_HI,
669
+
mqd->cp_mqd_base_addr_hi);
670
+
671
+
/* set MQD vmid to 0 */
672
+
WREG32_SOC15_RLC(GC, 0, regCP_MQD_CONTROL,
673
+
mqd->cp_mqd_control);
674
+
675
+
/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
676
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_BASE,
677
+
mqd->cp_hqd_pq_base_lo);
678
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_BASE_HI,
679
+
mqd->cp_hqd_pq_base_hi);
680
+
681
+
/* set up the HQD, this is similar to CP_RB0_CNTL */
682
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_CONTROL,
683
+
mqd->cp_hqd_pq_control);
684
+
685
+
/* set the wb address whether it's enabled or not */
686
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
687
+
mqd->cp_hqd_pq_rptr_report_addr_lo);
688
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
689
+
mqd->cp_hqd_pq_rptr_report_addr_hi);
690
+
691
+
/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
692
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
693
+
mqd->cp_hqd_pq_wptr_poll_addr_lo);
694
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
695
+
mqd->cp_hqd_pq_wptr_poll_addr_hi);
696
+
697
+
/* enable the doorbell if requested */
698
+
if (ring->use_doorbell) {
699
+
WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
700
+
(adev->doorbell_index.kiq * 2) << 2);
701
+
WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
702
+
(adev->doorbell_index.userqueue_end * 2) << 2);
703
+
}
704
+
705
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
706
+
mqd->cp_hqd_pq_doorbell_control);
707
+
708
+
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
709
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_LO,
710
+
mqd->cp_hqd_pq_wptr_lo);
711
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_HI,
712
+
mqd->cp_hqd_pq_wptr_hi);
713
+
714
+
/* set the vmid for the queue */
715
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
716
+
717
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PERSISTENT_STATE,
718
+
mqd->cp_hqd_persistent_state);
719
+
720
+
/* activate the queue */
721
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_ACTIVE,
722
+
mqd->cp_hqd_active);
723
+
724
+
if (ring->use_doorbell)
725
+
WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
726
+
727
+
return 0;
728
+
}
729
+
730
+
static int gfx_v9_4_3_kiq_fini_register(struct amdgpu_ring *ring)
731
+
{
732
+
struct amdgpu_device *adev = ring->adev;
733
+
int j;
734
+
735
+
/* disable the queue if it's active */
736
+
if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
737
+
738
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
739
+
740
+
for (j = 0; j < adev->usec_timeout; j++) {
741
+
if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
742
+
break;
743
+
udelay(1);
744
+
}
745
+
746
+
if (j == AMDGPU_MAX_USEC_TIMEOUT) {
747
+
DRM_DEBUG("KIQ dequeue request failed.\n");
748
+
749
+
/* Manual disable if dequeue request times out */
750
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_ACTIVE, 0);
751
+
}
752
+
753
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
754
+
0);
755
+
}
756
+
757
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_IQ_TIMER, 0);
758
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_IB_CONTROL, 0);
759
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PERSISTENT_STATE, 0);
760
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
761
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
762
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_RPTR, 0);
763
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
764
+
WREG32_SOC15_RLC(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
765
+
766
+
return 0;
767
+
}
768
+
769
+
static int gfx_v9_4_3_kiq_init_queue(struct amdgpu_ring *ring)
770
+
{
771
+
struct amdgpu_device *adev = ring->adev;
772
+
struct v9_mqd *mqd = ring->mqd_ptr;
773
+
struct v9_mqd *tmp_mqd;
774
+
775
+
gfx_v9_4_3_kiq_setting(ring);
776
+
777
+
/* GPU could be in bad state during probe, driver trigger the reset
778
+
* after load the SMU, in this case , the mqd is not be initialized.
779
+
* driver need to re-init the mqd.
780
+
* check mqd->cp_hqd_pq_control since this value should not be 0
781
+
*/
782
+
tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup;
783
+
if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
784
+
/* for GPU_RESET case , reset MQD to a clean status */
785
+
if (adev->gfx.kiq[0].mqd_backup)
786
+
memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation));
787
+
788
+
/* reset ring buffer */
789
+
ring->wptr = 0;
790
+
amdgpu_ring_clear_ring(ring);
791
+
792
+
mutex_lock(&adev->srbm_mutex);
793
+
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
794
+
gfx_v9_4_3_kiq_init_register(ring);
795
+
soc15_grbm_select(adev, 0, 0, 0, 0);
796
+
mutex_unlock(&adev->srbm_mutex);
797
+
} else {
798
+
memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
799
+
((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
800
+
((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
801
+
mutex_lock(&adev->srbm_mutex);
802
+
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
803
+
gfx_v9_4_3_mqd_init(ring);
804
+
gfx_v9_4_3_kiq_init_register(ring);
805
+
soc15_grbm_select(adev, 0, 0, 0, 0);
806
+
mutex_unlock(&adev->srbm_mutex);
807
+
808
+
if (adev->gfx.kiq[0].mqd_backup)
809
+
memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
810
+
}
811
+
812
+
return 0;
813
+
}
814
+
815
+
static int gfx_v9_4_3_kcq_init_queue(struct amdgpu_ring *ring)
816
+
{
817
+
struct amdgpu_device *adev = ring->adev;
818
+
struct v9_mqd *mqd = ring->mqd_ptr;
819
+
int mqd_idx = ring - &adev->gfx.compute_ring[0];
820
+
struct v9_mqd *tmp_mqd;
821
+
822
+
/* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
823
+
* is not be initialized before
824
+
*/
825
+
tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
826
+
827
+
if (!tmp_mqd->cp_hqd_pq_control ||
828
+
(!amdgpu_in_reset(adev) && !adev->in_suspend)) {
829
+
memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
830
+
((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
831
+
((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
832
+
mutex_lock(&adev->srbm_mutex);
833
+
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
834
+
gfx_v9_4_3_mqd_init(ring);
835
+
soc15_grbm_select(adev, 0, 0, 0, 0);
836
+
mutex_unlock(&adev->srbm_mutex);
837
+
838
+
if (adev->gfx.mec.mqd_backup[mqd_idx])
839
+
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
840
+
} else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
841
+
/* reset MQD to a clean status */
842
+
if (adev->gfx.mec.mqd_backup[mqd_idx])
843
+
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
844
+
845
+
/* reset ring buffer */
846
+
ring->wptr = 0;
847
+
atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
848
+
amdgpu_ring_clear_ring(ring);
849
+
} else {
850
+
amdgpu_ring_clear_ring(ring);
851
+
}
852
+
853
+
return 0;
854
+
}
855
+
856
+
static int gfx_v9_4_3_kiq_resume(struct amdgpu_device *adev)
857
+
{
858
+
struct amdgpu_ring *ring;
859
+
int r;
860
+
861
+
ring = &adev->gfx.kiq[0].ring;
862
+
863
+
r = amdgpu_bo_reserve(ring->mqd_obj, false);
864
+
if (unlikely(r != 0))
865
+
return r;
866
+
867
+
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
868
+
if (unlikely(r != 0))
869
+
return r;
870
+
871
+
gfx_v9_4_3_kiq_init_queue(ring);
872
+
amdgpu_bo_kunmap(ring->mqd_obj);
873
+
ring->mqd_ptr = NULL;
874
+
amdgpu_bo_unreserve(ring->mqd_obj);
875
+
ring->sched.ready = true;
876
+
return 0;
877
+
}
878
+
879
+
static int gfx_v9_4_3_kcq_resume(struct amdgpu_device *adev)
880
+
{
881
+
struct amdgpu_ring *ring = NULL;
882
+
int r = 0, i;
883
+
884
+
gfx_v9_4_3_cp_compute_enable(adev, true);
885
+
886
+
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
887
+
ring = &adev->gfx.compute_ring[i];
888
+
889
+
r = amdgpu_bo_reserve(ring->mqd_obj, false);
890
+
if (unlikely(r != 0))
891
+
goto done;
892
+
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
893
+
if (!r) {
894
+
r = gfx_v9_4_3_kcq_init_queue(ring);
895
+
amdgpu_bo_kunmap(ring->mqd_obj);
896
+
ring->mqd_ptr = NULL;
897
+
}
898
+
amdgpu_bo_unreserve(ring->mqd_obj);
899
+
if (r)
900
+
goto done;
901
+
}
902
+
903
+
r = amdgpu_gfx_enable_kcq(adev, 0);
904
+
done:
905
+
return r;
906
+
}
907
+
908
+
static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
909
+
{
910
+
int r, i;
911
+
struct amdgpu_ring *ring;
912
+
913
+
gfx_v9_4_3_enable_gui_idle_interrupt(adev, false);
914
+
915
+
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
916
+
gfx_v9_4_3_disable_gpa_mode(adev);
917
+
918
+
r = gfx_v9_4_3_cp_compute_load_microcode(adev);
919
+
if (r)
920
+
return r;
921
+
}
922
+
923
+
r = gfx_v9_4_3_kiq_resume(adev);
924
+
if (r)
925
+
return r;
926
+
927
+
r = gfx_v9_4_3_kcq_resume(adev);
928
+
if (r)
929
+
return r;
930
+
931
+
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
932
+
ring = &adev->gfx.compute_ring[i];
933
+
amdgpu_ring_test_helper(ring);
934
+
}
935
+
936
+
gfx_v9_4_3_enable_gui_idle_interrupt(adev, true);
937
+
938
+
return 0;
939
+
}
940
+
941
+
static void gfx_v9_4_3_cp_enable(struct amdgpu_device *adev, bool enable)
942
+
{
943
+
gfx_v9_4_3_cp_compute_enable(adev, enable);
944
+
}
945
+
946
+
static int gfx_v9_4_3_hw_init(void *handle)
947
+
{
948
+
int r;
949
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
950
+
951
+
gfx_v9_4_3_init_golden_registers(adev);
952
+
953
+
gfx_v9_4_3_constants_init(adev);
954
+
955
+
r = adev->gfx.rlc.funcs->resume(adev);
956
+
if (r)
957
+
return r;
958
+
959
+
r = gfx_v9_4_3_cp_resume(adev);
960
+
if (r)
961
+
return r;
962
+
963
+
return r;
964
+
}
965
+
966
+
static int gfx_v9_4_3_hw_fini(void *handle)
967
+
{
968
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
969
+
970
+
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
971
+
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
972
+
973
+
if (amdgpu_gfx_disable_kcq(adev, 0))
974
+
DRM_ERROR("KCQ disable failed\n");
975
+
976
+
/* Use deinitialize sequence from CAIL when unbinding device from driver,
977
+
* otherwise KIQ is hanging when binding back
978
+
*/
979
+
if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
980
+
mutex_lock(&adev->srbm_mutex);
981
+
soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me,
982
+
adev->gfx.kiq[0].ring.pipe,
983
+
adev->gfx.kiq[0].ring.queue, 0);
984
+
gfx_v9_4_3_kiq_fini_register(&adev->gfx.kiq[0].ring);
985
+
soc15_grbm_select(adev, 0, 0, 0, 0);
986
+
mutex_unlock(&adev->srbm_mutex);
987
+
}
988
+
989
+
gfx_v9_4_3_cp_enable(adev, false);
990
+
991
+
/* Skip suspend with A+A reset */
992
+
if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) {
993
+
dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n");
994
+
return 0;
995
+
}
996
+
997
+
adev->gfx.rlc.funcs->stop(adev);
998
+
return 0;
999
+
}
1000
+
1001
+
static int gfx_v9_4_3_suspend(void *handle)
1002
+
{
1003
+
return gfx_v9_4_3_hw_fini(handle);
1004
+
}
1005
+
1006
+
static int gfx_v9_4_3_resume(void *handle)
1007
+
{
1008
+
return gfx_v9_4_3_hw_init(handle);
1009
+
}
1010
+
1011
+
static bool gfx_v9_4_3_is_idle(void *handle)
1012
+
{
1013
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014
+
1015
+
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
1016
+
GRBM_STATUS, GUI_ACTIVE))
1017
+
return false;
1018
+
else
1019
+
return true;
1020
+
}
1021
+
1022
+
static int gfx_v9_4_3_wait_for_idle(void *handle)
1023
+
{
1024
+
unsigned i;
1025
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
+
1027
+
for (i = 0; i < adev->usec_timeout; i++) {
1028
+
if (gfx_v9_4_3_is_idle(handle))
1029
+
return 0;
1030
+
udelay(1);
1031
+
}
1032
+
return -ETIMEDOUT;
1033
+
}
1034
+
1035
+
static int gfx_v9_4_3_soft_reset(void *handle)
1036
+
{
1037
+
u32 grbm_soft_reset = 0;
1038
+
u32 tmp;
1039
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1040
+
1041
+
/* GRBM_STATUS */
1042
+
tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS);
1043
+
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
1044
+
GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
1045
+
GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
1046
+
GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
1047
+
GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
1048
+
GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
1049
+
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1050
+
GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
1051
+
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1052
+
GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
1053
+
}
1054
+
1055
+
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
1056
+
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1057
+
GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
1058
+
}
1059
+
1060
+
/* GRBM_STATUS2 */
1061
+
tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS2);
1062
+
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
1063
+
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1064
+
GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1065
+
1066
+
1067
+
if (grbm_soft_reset) {
1068
+
/* stop the rlc */
1069
+
adev->gfx.rlc.funcs->stop(adev);
1070
+
1071
+
/* Disable MEC parsing/prefetching */
1072
+
gfx_v9_4_3_cp_compute_enable(adev, false);
1073
+
1074
+
if (grbm_soft_reset) {
1075
+
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
1076
+
tmp |= grbm_soft_reset;
1077
+
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1078
+
WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
1079
+
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
1080
+
1081
+
udelay(50);
1082
+
1083
+
tmp &= ~grbm_soft_reset;
1084
+
WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
1085
+
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
1086
+
}
1087
+
1088
+
/* Wait a little for things to settle down */
1089
+
udelay(50);
1090
+
}
1091
+
return 0;
1092
+
}
1093
+
1094
+
static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
1095
+
uint32_t vmid,
1096
+
uint32_t gds_base, uint32_t gds_size,
1097
+
uint32_t gws_base, uint32_t gws_size,
1098
+
uint32_t oa_base, uint32_t oa_size)
1099
+
{
1100
+
struct amdgpu_device *adev = ring->adev;
1101
+
1102
+
/* GDS Base */
1103
+
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
1104
+
SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
1105
+
gds_base);
1106
+
1107
+
/* GDS Size */
1108
+
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
1109
+
SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
1110
+
gds_size);
1111
+
1112
+
/* GWS */
1113
+
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
1114
+
SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
1115
+
gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
1116
+
1117
+
/* OA */
1118
+
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
1119
+
SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
1120
+
(1 << (oa_size + oa_base)) - (1 << oa_base));
1121
+
}
1122
+
1123
+
static int gfx_v9_4_3_early_init(void *handle)
1124
+
{
1125
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
+
1127
+
adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
1128
+
AMDGPU_MAX_COMPUTE_RINGS);
1129
+
gfx_v9_4_3_set_kiq_pm4_funcs(adev);
1130
+
gfx_v9_4_3_set_ring_funcs(adev);
1131
+
gfx_v9_4_3_set_irq_funcs(adev);
1132
+
gfx_v9_4_3_set_gds_init(adev);
1133
+
gfx_v9_4_3_set_rlc_funcs(adev);
1134
+
1135
+
return gfx_v9_4_3_init_microcode(adev);
1136
+
}
1137
+
1138
+
static int gfx_v9_4_3_late_init(void *handle)
1139
+
{
1140
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141
+
int r;
1142
+
1143
+
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
1144
+
if (r)
1145
+
return r;
1146
+
1147
+
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
1148
+
if (r)
1149
+
return r;
1150
+
1151
+
return 0;
1152
+
}
1153
+
1154
+
static void gfx_v9_4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1155
+
bool enable)
1156
+
{
1157
+
uint32_t data, def;
1158
+
1159
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
1160
+
1161
+
/* It is disabled by HW by default */
1162
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
1163
+
/* 1 - RLC_CGTT_MGCG_OVERRIDE */
1164
+
def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
1165
+
1166
+
data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
1167
+
RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
1168
+
RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
1169
+
1170
+
/* only for Vega10 & Raven1 */
1171
+
data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
1172
+
1173
+
if (def != data)
1174
+
WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
1175
+
1176
+
/* MGLS is a global flag to control all MGLS in GFX */
1177
+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
1178
+
/* 2 - RLC memory Light sleep */
1179
+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
1180
+
def = data = RREG32_SOC15(GC, 0, regRLC_MEM_SLP_CNTL);
1181
+
data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
1182
+
if (def != data)
1183
+
WREG32_SOC15(GC, 0, regRLC_MEM_SLP_CNTL, data);
1184
+
}
1185
+
/* 3 - CP memory Light sleep */
1186
+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
1187
+
def = data = RREG32_SOC15(GC, 0, regCP_MEM_SLP_CNTL);
1188
+
data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
1189
+
if (def != data)
1190
+
WREG32_SOC15(GC, 0, regCP_MEM_SLP_CNTL, data);
1191
+
}
1192
+
}
1193
+
} else {
1194
+
/* 1 - MGCG_OVERRIDE */
1195
+
def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
1196
+
1197
+
data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
1198
+
RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
1199
+
RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
1200
+
RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
1201
+
1202
+
if (def != data)
1203
+
WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
1204
+
1205
+
/* 2 - disable MGLS in RLC */
1206
+
data = RREG32_SOC15(GC, 0, regRLC_MEM_SLP_CNTL);
1207
+
if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
1208
+
data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
1209
+
WREG32_SOC15(GC, 0, regRLC_MEM_SLP_CNTL, data);
1210
+
}
1211
+
1212
+
/* 3 - disable MGLS in CP */
1213
+
data = RREG32_SOC15(GC, 0, regCP_MEM_SLP_CNTL);
1214
+
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
1215
+
data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
1216
+
WREG32_SOC15(GC, 0, regCP_MEM_SLP_CNTL, data);
1217
+
}
1218
+
}
1219
+
1220
+
amdgpu_gfx_rlc_exit_safe_mode(adev);
1221
+
}
1222
+
1223
+
static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
1224
+
bool enable)
1225
+
{
1226
+
uint32_t def, data;
1227
+
1228
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
1229
+
1230
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
1231
+
def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
1232
+
/* unset CGCG override */
1233
+
data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
1234
+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
1235
+
data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
1236
+
else
1237
+
data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
1238
+
/* update CGCG and CGLS override bits */
1239
+
if (def != data)
1240
+
WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
1241
+
1242
+
/* enable cgcg FSM(0x0000363F) */
1243
+
def = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
1244
+
1245
+
if (adev->asic_type == CHIP_ARCTURUS)
1246
+
data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
1247
+
RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
1248
+
else
1249
+
data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
1250
+
RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
1251
+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
1252
+
data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
1253
+
RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
1254
+
if (def != data)
1255
+
WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
1256
+
1257
+
/* set IDLE_POLL_COUNT(0x00900100) */
1258
+
def = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
1259
+
data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
1260
+
(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1261
+
if (def != data)
1262
+
WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
1263
+
} else {
1264
+
def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
1265
+
/* reset CGCG/CGLS bits */
1266
+
data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
1267
+
/* disable cgcg and cgls in FSM */
1268
+
if (def != data)
1269
+
WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
1270
+
}
1271
+
1272
+
amdgpu_gfx_rlc_exit_safe_mode(adev);
1273
+
}
1274
+
1275
+
static int gfx_v9_4_3_update_gfx_clock_gating(struct amdgpu_device *adev,
1276
+
bool enable)
1277
+
{
1278
+
if (enable) {
1279
+
/* CGCG/CGLS should be enabled after MGCG/MGLS
1280
+
* === MGCG + MGLS ===
1281
+
*/
1282
+
gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable);
1283
+
/* === CGCG + CGLS === */
1284
+
gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable);
1285
+
} else {
1286
+
/* CGCG/CGLS should be disabled before MGCG/MGLS
1287
+
* === CGCG + CGLS ===
1288
+
*/
1289
+
gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable);
1290
+
/* === MGCG + MGLS === */
1291
+
gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable);
1292
+
}
1293
+
return 0;
1294
+
}
1295
+
1296
+
static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
1336
1297
.is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
1337
1298
.set_safe_mode = gfx_v9_4_3_set_safe_mode,
1338
1299
.unset_safe_mode = gfx_v9_4_3_unset_safe_mode,
1339
1300
.init = gfx_v9_4_3_rlc_init,
1301
+
.get_csb_size = gfx_v9_4_3_get_csb_size,
1302
+
.get_csb_buffer = gfx_v9_4_3_get_csb_buffer,
1340
1303
.resume = gfx_v9_4_3_rlc_resume,
1341
1304
.stop = gfx_v9_4_3_rlc_stop,
1342
1305
.reset = gfx_v9_4_3_rlc_reset,
1343
1306
.start = gfx_v9_4_3_rlc_start,
1344
1307
.update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
1345
1308
.is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
1309
+
};
1310
+
1311
+
static int gfx_v9_4_3_set_powergating_state(void *handle,
1312
+
enum amd_powergating_state state)
1313
+
{
1314
+
return 0;
1315
+
}
1316
+
1317
+
static int gfx_v9_4_3_set_clockgating_state(void *handle,
1318
+
enum amd_clockgating_state state)
1319
+
{
1320
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
+
1322
+
if (amdgpu_sriov_vf(adev))
1323
+
return 0;
1324
+
1325
+
switch (adev->ip_versions[GC_HWIP][0]) {
1326
+
case IP_VERSION(9, 4, 3):
1327
+
gfx_v9_4_3_update_gfx_clock_gating(adev,
1328
+
state == AMD_CG_STATE_GATE);
1329
+
break;
1330
+
default:
1331
+
break;
1332
+
}
1333
+
return 0;
1334
+
}
1335
+
1336
+
static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
1337
+
{
1338
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
+
int data;
1340
+
1341
+
if (amdgpu_sriov_vf(adev))
1342
+
*flags = 0;
1343
+
1344
+
/* AMD_CG_SUPPORT_GFX_MGCG */
1345
+
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_CGTT_MGCG_OVERRIDE));
1346
+
if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
1347
+
*flags |= AMD_CG_SUPPORT_GFX_MGCG;
1348
+
1349
+
/* AMD_CG_SUPPORT_GFX_CGCG */
1350
+
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_CGCG_CGLS_CTRL));
1351
+
if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
1352
+
*flags |= AMD_CG_SUPPORT_GFX_CGCG;
1353
+
1354
+
/* AMD_CG_SUPPORT_GFX_CGLS */
1355
+
if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
1356
+
*flags |= AMD_CG_SUPPORT_GFX_CGLS;
1357
+
1358
+
/* AMD_CG_SUPPORT_GFX_RLC_LS */
1359
+
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_MEM_SLP_CNTL));
1360
+
if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
1361
+
*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
1362
+
1363
+
/* AMD_CG_SUPPORT_GFX_CP_LS */
1364
+
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regCP_MEM_SLP_CNTL));
1365
+
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
1366
+
*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
1367
+
}
1368
+
1369
+
static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1370
+
{
1371
+
struct amdgpu_device *adev = ring->adev;
1372
+
u32 ref_and_mask, reg_mem_engine;
1373
+
const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
1374
+
1375
+
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1376
+
switch (ring->me) {
1377
+
case 1:
1378
+
ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
1379
+
break;
1380
+
case 2:
1381
+
ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
1382
+
break;
1383
+
default:
1384
+
return;
1385
+
}
1386
+
reg_mem_engine = 0;
1387
+
} else {
1388
+
ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
1389
+
reg_mem_engine = 1; /* pfp */
1390
+
}
1391
+
1392
+
gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
1393
+
adev->nbio.funcs->get_hdp_flush_req_offset(adev),
1394
+
adev->nbio.funcs->get_hdp_flush_done_offset(adev),
1395
+
ref_and_mask, ref_and_mask, 0x20);
1396
+
}
1397
+
1398
+
static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
1399
+
struct amdgpu_job *job,
1400
+
struct amdgpu_ib *ib,
1401
+
uint32_t flags)
1402
+
{
1403
+
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1404
+
u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
1405
+
1406
+
/* Currently, there is a high possibility to get wave ID mismatch
1407
+
* between ME and GDS, leading to a hw deadlock, because ME generates
1408
+
* different wave IDs than the GDS expects. This situation happens
1409
+
* randomly when at least 5 compute pipes use GDS ordered append.
1410
+
* The wave IDs generated by ME are also wrong after suspend/resume.
1411
+
* Those are probably bugs somewhere else in the kernel driver.
1412
+
*
1413
+
* Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
1414
+
* GDS to 0 for this ring (me/pipe).
1415
+
*/
1416
+
if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
1417
+
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1418
+
amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
1419
+
amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
1420
+
}
1421
+
1422
+
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1423
+
BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
1424
+
amdgpu_ring_write(ring,
1425
+
#ifdef __BIG_ENDIAN
1426
+
(2 << 0) |
1427
+
#endif
1428
+
lower_32_bits(ib->gpu_addr));
1429
+
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1430
+
amdgpu_ring_write(ring, control);
1431
+
}
1432
+
1433
+
static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1434
+
u64 seq, unsigned flags)
1435
+
{
1436
+
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1437
+
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1438
+
bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
1439
+
1440
+
/* RELEASE_MEM - flush caches, send int */
1441
+
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
1442
+
amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
1443
+
EOP_TC_NC_ACTION_EN) :
1444
+
(EOP_TCL1_ACTION_EN |
1445
+
EOP_TC_ACTION_EN |
1446
+
EOP_TC_WB_ACTION_EN |
1447
+
EOP_TC_MD_ACTION_EN)) |
1448
+
EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1449
+
EVENT_INDEX(5)));
1450
+
amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1451
+
1452
+
/*
1453
+
* the address should be Qword aligned if 64bit write, Dword
1454
+
* aligned if only send 32bit data low (discard data high)
1455
+
*/
1456
+
if (write64bit)
1457
+
BUG_ON(addr & 0x7);
1458
+
else
1459
+
BUG_ON(addr & 0x3);
1460
+
amdgpu_ring_write(ring, lower_32_bits(addr));
1461
+
amdgpu_ring_write(ring, upper_32_bits(addr));
1462
+
amdgpu_ring_write(ring, lower_32_bits(seq));
1463
+
amdgpu_ring_write(ring, upper_32_bits(seq));
1464
+
amdgpu_ring_write(ring, 0);
1465
+
}
1466
+
1467
+
static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1468
+
{
1469
+
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
1470
+
uint32_t seq = ring->fence_drv.sync_seq;
1471
+
uint64_t addr = ring->fence_drv.gpu_addr;
1472
+
1473
+
gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
1474
+
lower_32_bits(addr), upper_32_bits(addr),
1475
+
seq, 0xffffffff, 4);
1476
+
}
1477
+
1478
+
static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
1479
+
unsigned vmid, uint64_t pd_addr)
1480
+
{
1481
+
amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1482
+
}
1483
+
1484
+
static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
1485
+
{
1486
+
return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
1487
+
}
1488
+
1489
+
static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
1490
+
{
1491
+
u64 wptr;
1492
+
1493
+
/* XXX check if swapping is necessary on BE */
1494
+
if (ring->use_doorbell)
1495
+
wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
1496
+
else
1497
+
BUG();
1498
+
return wptr;
1499
+
}
1500
+
1501
+
static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
1502
+
{
1503
+
struct amdgpu_device *adev = ring->adev;
1504
+
1505
+
/* XXX check if swapping is necessary on BE */
1506
+
if (ring->use_doorbell) {
1507
+
atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
1508
+
WDOORBELL64(ring->doorbell_index, ring->wptr);
1509
+
} else {
1510
+
BUG(); /* only DOORBELL method supported on gfx9 now */
1511
+
}
1512
+
}
1513
+
1514
+
static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
1515
+
u64 seq, unsigned int flags)
1516
+
{
1517
+
struct amdgpu_device *adev = ring->adev;
1518
+
1519
+
/* we only allocate 32bit for each seq wb address */
1520
+
BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1521
+
1522
+
/* write fence seq to the "addr" */
1523
+
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1524
+
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1525
+
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
1526
+
amdgpu_ring_write(ring, lower_32_bits(addr));
1527
+
amdgpu_ring_write(ring, upper_32_bits(addr));
1528
+
amdgpu_ring_write(ring, lower_32_bits(seq));
1529
+
1530
+
if (flags & AMDGPU_FENCE_FLAG_INT) {
1531
+
/* set register to trigger INT */
1532
+
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1533
+
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1534
+
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
1535
+
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
1536
+
amdgpu_ring_write(ring, 0);
1537
+
amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
1538
+
}
1539
+
}
1540
+
1541
+
static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
1542
+
uint32_t reg_val_offs)
1543
+
{
1544
+
struct amdgpu_device *adev = ring->adev;
1545
+
1546
+
amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
1547
+
amdgpu_ring_write(ring, 0 | /* src: register*/
1548
+
(5 << 8) | /* dst: memory */
1549
+
(1 << 20)); /* write confirm */
1550
+
amdgpu_ring_write(ring, reg);
1551
+
amdgpu_ring_write(ring, 0);
1552
+
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
1553
+
reg_val_offs * 4));
1554
+
amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
1555
+
reg_val_offs * 4));
1556
+
}
1557
+
1558
+
static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
1559
+
uint32_t val)
1560
+
{
1561
+
uint32_t cmd = 0;
1562
+
1563
+
switch (ring->funcs->type) {
1564
+
case AMDGPU_RING_TYPE_GFX:
1565
+
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
1566
+
break;
1567
+
case AMDGPU_RING_TYPE_KIQ:
1568
+
cmd = (1 << 16); /* no inc addr */
1569
+
break;
1570
+
default:
1571
+
cmd = WR_CONFIRM;
1572
+
break;
1573
+
}
1574
+
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1575
+
amdgpu_ring_write(ring, cmd);
1576
+
amdgpu_ring_write(ring, reg);
1577
+
amdgpu_ring_write(ring, 0);
1578
+
amdgpu_ring_write(ring, val);
1579
+
}
1580
+
1581
+
static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1582
+
uint32_t val, uint32_t mask)
1583
+
{
1584
+
gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
1585
+
}
1586
+
1587
+
static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1588
+
uint32_t reg0, uint32_t reg1,
1589
+
uint32_t ref, uint32_t mask)
1590
+
{
1591
+
amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
1592
+
ref, mask);
1593
+
}
1594
+
1595
+
static void gfx_v9_4_3_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
1596
+
int me, int pipe,
1597
+
enum amdgpu_interrupt_state state)
1598
+
{
1599
+
u32 mec_int_cntl, mec_int_cntl_reg;
1600
+
1601
+
/*
1602
+
* amdgpu controls only the first MEC. That's why this function only
1603
+
* handles the setting of interrupts for this specific MEC. All other
1604
+
* pipes' interrupts are set by amdkfd.
1605
+
*/
1606
+
1607
+
if (me == 1) {
1608
+
switch (pipe) {
1609
+
case 0:
1610
+
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1611
+
break;
1612
+
case 1:
1613
+
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1614
+
break;
1615
+
case 2:
1616
+
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
1617
+
break;
1618
+
case 3:
1619
+
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
1620
+
break;
1621
+
default:
1622
+
DRM_DEBUG("invalid pipe %d\n", pipe);
1623
+
return;
1624
+
}
1625
+
} else {
1626
+
DRM_DEBUG("invalid me %d\n", me);
1627
+
return;
1628
+
}
1629
+
1630
+
switch (state) {
1631
+
case AMDGPU_IRQ_STATE_DISABLE:
1632
+
mec_int_cntl = RREG32(mec_int_cntl_reg);
1633
+
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
1634
+
TIME_STAMP_INT_ENABLE, 0);
1635
+
WREG32(mec_int_cntl_reg, mec_int_cntl);
1636
+
break;
1637
+
case AMDGPU_IRQ_STATE_ENABLE:
1638
+
mec_int_cntl = RREG32(mec_int_cntl_reg);
1639
+
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
1640
+
TIME_STAMP_INT_ENABLE, 1);
1641
+
WREG32(mec_int_cntl_reg, mec_int_cntl);
1642
+
break;
1643
+
default:
1644
+
break;
1645
+
}
1646
+
}
1647
+
1648
+
static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
1649
+
struct amdgpu_irq_src *source,
1650
+
unsigned type,
1651
+
enum amdgpu_interrupt_state state)
1652
+
{
1653
+
switch (state) {
1654
+
case AMDGPU_IRQ_STATE_DISABLE:
1655
+
case AMDGPU_IRQ_STATE_ENABLE:
1656
+
WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
1657
+
PRIV_REG_INT_ENABLE,
1658
+
state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1659
+
break;
1660
+
default:
1661
+
break;
1662
+
}
1663
+
1664
+
return 0;
1665
+
}
1666
+
1667
+
static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
1668
+
struct amdgpu_irq_src *source,
1669
+
unsigned type,
1670
+
enum amdgpu_interrupt_state state)
1671
+
{
1672
+
switch (state) {
1673
+
case AMDGPU_IRQ_STATE_DISABLE:
1674
+
case AMDGPU_IRQ_STATE_ENABLE:
1675
+
WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
1676
+
PRIV_INSTR_INT_ENABLE,
1677
+
state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1678
+
break;
1679
+
default:
1680
+
break;
1681
+
}
1682
+
1683
+
return 0;
1684
+
}
1685
+
1686
+
static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
1687
+
struct amdgpu_irq_src *src,
1688
+
unsigned type,
1689
+
enum amdgpu_interrupt_state state)
1690
+
{
1691
+
switch (type) {
1692
+
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
1693
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 0, state);
1694
+
break;
1695
+
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
1696
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 1, state);
1697
+
break;
1698
+
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
1699
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 2, state);
1700
+
break;
1701
+
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
1702
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 3, state);
1703
+
break;
1704
+
case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
1705
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 0, state);
1706
+
break;
1707
+
case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
1708
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 1, state);
1709
+
break;
1710
+
case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
1711
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 2, state);
1712
+
break;
1713
+
case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
1714
+
gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 3, state);
1715
+
break;
1716
+
default:
1717
+
break;
1718
+
}
1719
+
return 0;
1720
+
}
1721
+
1722
+
static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
1723
+
struct amdgpu_irq_src *source,
1724
+
struct amdgpu_iv_entry *entry)
1725
+
{
1726
+
int i;
1727
+
u8 me_id, pipe_id, queue_id;
1728
+
struct amdgpu_ring *ring;
1729
+
1730
+
DRM_DEBUG("IH: CP EOP\n");
1731
+
me_id = (entry->ring_id & 0x0c) >> 2;
1732
+
pipe_id = (entry->ring_id & 0x03) >> 0;
1733
+
queue_id = (entry->ring_id & 0x70) >> 4;
1734
+
1735
+
switch (me_id) {
1736
+
case 0:
1737
+
case 1:
1738
+
case 2:
1739
+
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1740
+
ring = &adev->gfx.compute_ring[i];
1741
+
/* Per-queue interrupt is supported for MEC starting from VI.
1742
+
* The interrupt can only be enabled/disabled per pipe instead of per queue.
1743
+
*/
1744
+
if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
1745
+
amdgpu_fence_process(ring);
1746
+
}
1747
+
break;
1748
+
}
1749
+
return 0;
1750
+
}
1751
+
1752
+
static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
1753
+
struct amdgpu_iv_entry *entry)
1754
+
{
1755
+
u8 me_id, pipe_id, queue_id;
1756
+
struct amdgpu_ring *ring;
1757
+
int i;
1758
+
1759
+
me_id = (entry->ring_id & 0x0c) >> 2;
1760
+
pipe_id = (entry->ring_id & 0x03) >> 0;
1761
+
queue_id = (entry->ring_id & 0x70) >> 4;
1762
+
1763
+
switch (me_id) {
1764
+
case 0:
1765
+
case 1:
1766
+
case 2:
1767
+
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1768
+
ring = &adev->gfx.compute_ring[i];
1769
+
if (ring->me == me_id && ring->pipe == pipe_id &&
1770
+
ring->queue == queue_id)
1771
+
drm_sched_fault(&ring->sched);
1772
+
}
1773
+
break;
1774
+
}
1775
+
}
1776
+
1777
+
static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
1778
+
struct amdgpu_irq_src *source,
1779
+
struct amdgpu_iv_entry *entry)
1780
+
{
1781
+
DRM_ERROR("Illegal register access in command stream\n");
1782
+
gfx_v9_4_3_fault(adev, entry);
1783
+
return 0;
1784
+
}
1785
+
1786
+
static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
1787
+
struct amdgpu_irq_src *source,
1788
+
struct amdgpu_iv_entry *entry)
1789
+
{
1790
+
DRM_ERROR("Illegal instruction in command stream\n");
1791
+
gfx_v9_4_3_fault(adev, entry);
1792
+
return 0;
1793
+
}
1794
+
1795
+
static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
1796
+
{
1797
+
const unsigned int cp_coher_cntl =
1798
+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
1799
+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
1800
+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
1801
+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
1802
+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
1803
+
1804
+
/* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
1805
+
amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
1806
+
amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
1807
+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
1808
+
amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
1809
+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
1810
+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
1811
+
amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
1812
+
}
1813
+
1814
+
static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
1815
+
uint32_t pipe, bool enable)
1816
+
{
1817
+
struct amdgpu_device *adev = ring->adev;
1818
+
uint32_t val;
1819
+
uint32_t wcl_cs_reg;
1820
+
1821
+
/* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
1822
+
val = enable ? 0x1 : 0x7f;
1823
+
1824
+
switch (pipe) {
1825
+
case 0:
1826
+
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS0);
1827
+
break;
1828
+
case 1:
1829
+
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS1);
1830
+
break;
1831
+
case 2:
1832
+
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS2);
1833
+
break;
1834
+
case 3:
1835
+
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS3);
1836
+
break;
1837
+
default:
1838
+
DRM_DEBUG("invalid pipe %d\n", pipe);
1839
+
return;
1840
+
}
1841
+
1842
+
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
1843
+
1844
+
}
1845
+
static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
1846
+
{
1847
+
struct amdgpu_device *adev = ring->adev;
1848
+
uint32_t val;
1849
+
int i;
1850
+
1851
+
/* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
1852
+
* number of gfx waves. Setting 5 bit will make sure gfx only gets
1853
+
* around 25% of gpu resources.
1854
+
*/
1855
+
val = enable ? 0x1f : 0x07ffffff;
1856
+
amdgpu_ring_emit_wreg(ring,
1857
+
SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_GFX),
1858
+
val);
1859
+
1860
+
/* Restrict waves for normal/low priority compute queues as well
1861
+
* to get best QoS for high priority compute jobs.
1862
+
*
1863
+
* amdgpu controls only 1st ME(0-3 CS pipes).
1864
+
*/
1865
+
for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
1866
+
if (i != ring->pipe)
1867
+
gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
1868
+
1869
+
}
1870
+
}
1871
+
1872
+
static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
1873
+
.name = "gfx_v9_4_3",
1874
+
.early_init = gfx_v9_4_3_early_init,
1875
+
.late_init = gfx_v9_4_3_late_init,
1876
+
.sw_init = gfx_v9_4_3_sw_init,
1877
+
.sw_fini = gfx_v9_4_3_sw_fini,
1878
+
.hw_init = gfx_v9_4_3_hw_init,
1879
+
.hw_fini = gfx_v9_4_3_hw_fini,
1880
+
.suspend = gfx_v9_4_3_suspend,
1881
+
.resume = gfx_v9_4_3_resume,
1882
+
.is_idle = gfx_v9_4_3_is_idle,
1883
+
.wait_for_idle = gfx_v9_4_3_wait_for_idle,
1884
+
.soft_reset = gfx_v9_4_3_soft_reset,
1885
+
.set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
1886
+
.set_powergating_state = gfx_v9_4_3_set_powergating_state,
1887
+
.get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
1888
+
};
1889
+
1890
+
static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
1891
+
.type = AMDGPU_RING_TYPE_COMPUTE,
1892
+
.align_mask = 0xff,
1893
+
.nop = PACKET3(PACKET3_NOP, 0x3FFF),
1894
+
.support_64bit_ptrs = true,
1895
+
.get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
1896
+
.get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
1897
+
.set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
1898
+
.emit_frame_size =
1899
+
20 + /* gfx_v9_4_3_ring_emit_gds_switch */
1900
+
7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
1901
+
5 + /* hdp invalidate */
1902
+
7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
1903
+
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
1904
+
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
1905
+
2 + /* gfx_v9_4_3_ring_emit_vm_flush */
1906
+
8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
1907
+
7 + /* gfx_v9_4_3_emit_mem_sync */
1908
+
5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
1909
+
15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
1910
+
.emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
1911
+
.emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
1912
+
.emit_fence = gfx_v9_4_3_ring_emit_fence,
1913
+
.emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
1914
+
.emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
1915
+
.emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
1916
+
.emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
1917
+
.test_ring = gfx_v9_4_3_ring_test_ring,
1918
+
.test_ib = gfx_v9_4_3_ring_test_ib,
1919
+
.insert_nop = amdgpu_ring_insert_nop,
1920
+
.pad_ib = amdgpu_ring_generic_pad_ib,
1921
+
.emit_wreg = gfx_v9_4_3_ring_emit_wreg,
1922
+
.emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
1923
+
.emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
1924
+
.emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
1925
+
.emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
1926
+
};
1927
+
1928
+
static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
1929
+
.type = AMDGPU_RING_TYPE_KIQ,
1930
+
.align_mask = 0xff,
1931
+
.nop = PACKET3(PACKET3_NOP, 0x3FFF),
1932
+
.support_64bit_ptrs = true,
1933
+
.get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
1934
+
.get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
1935
+
.set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
1936
+
.emit_frame_size =
1937
+
20 + /* gfx_v9_4_3_ring_emit_gds_switch */
1938
+
7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
1939
+
5 + /* hdp invalidate */
1940
+
7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
1941
+
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
1942
+
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
1943
+
2 + /* gfx_v9_4_3_ring_emit_vm_flush */
1944
+
8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
1945
+
.emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
1946
+
.emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
1947
+
.test_ring = gfx_v9_4_3_ring_test_ring,
1948
+
.insert_nop = amdgpu_ring_insert_nop,
1949
+
.pad_ib = amdgpu_ring_generic_pad_ib,
1950
+
.emit_rreg = gfx_v9_4_3_ring_emit_rreg,
1951
+
.emit_wreg = gfx_v9_4_3_ring_emit_wreg,
1952
+
.emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
1953
+
.emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
1954
+
};
1955
+
1956
+
static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
1957
+
{
1958
+
int i;
1959
+
1960
+
adev->gfx.kiq[0].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
1961
+
1962
+
for (i = 0; i < adev->gfx.num_compute_rings; i++)
1963
+
adev->gfx.compute_ring[i].funcs = &gfx_v9_4_3_ring_funcs_compute;
1964
+
}
1965
+
1966
+
static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
1967
+
.set = gfx_v9_4_3_set_eop_interrupt_state,
1968
+
.process = gfx_v9_4_3_eop_irq,
1969
+
};
1970
+
1971
+
static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
1972
+
.set = gfx_v9_4_3_set_priv_reg_fault_state,
1973
+
.process = gfx_v9_4_3_priv_reg_irq,
1974
+
};
1975
+
1976
+
static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
1977
+
.set = gfx_v9_4_3_set_priv_inst_fault_state,
1978
+
.process = gfx_v9_4_3_priv_inst_irq,
1979
+
};
1980
+
1981
+
static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
1982
+
{
1983
+
adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
1984
+
adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
1985
+
1986
+
adev->gfx.priv_reg_irq.num_types = 1;
1987
+
adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
1988
+
1989
+
adev->gfx.priv_inst_irq.num_types = 1;
1990
+
adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
1991
+
}
1992
+
1993
+
static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
1994
+
{
1995
+
adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
1996
+
}
1997
+
1998
+
1999
+
static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
2000
+
{
2001
+
/* init asci gds info */
2002
+
switch (adev->ip_versions[GC_HWIP][0]) {
2003
+
case IP_VERSION(9, 4, 3):
2004
+
/* 9.4.3 removed all the GDS internal memory,
2005
+
* only support GWS opcode in kernel, like barrier
2006
+
* semaphore.etc */
2007
+
adev->gds.gds_size = 0;
2008
+
break;
2009
+
default:
2010
+
adev->gds.gds_size = 0x10000;
2011
+
break;
2012
+
}
2013
+
2014
+
switch (adev->ip_versions[GC_HWIP][0]) {
2015
+
case IP_VERSION(9, 4, 3):
2016
+
/* deprecated for 9.4.3, no usage at all */
2017
+
adev->gds.gds_compute_max_wave_id = 0;
2018
+
break;
2019
+
default:
2020
+
/* this really depends on the chip */
2021
+
adev->gds.gds_compute_max_wave_id = 0x7ff;
2022
+
break;
2023
+
}
2024
+
2025
+
adev->gds.gws_size = 64;
2026
+
adev->gds.oa_size = 16;
2027
+
}
2028
+
2029
+
static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
2030
+
u32 bitmap)
2031
+
{
2032
+
u32 data;
2033
+
2034
+
if (!bitmap)
2035
+
return;
2036
+
2037
+
data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
2038
+
data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
2039
+
2040
+
WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
2041
+
}
2042
+
2043
+
static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev)
2044
+
{
2045
+
u32 data, mask;
2046
+
2047
+
data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
2048
+
data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
2049
+
2050
+
data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
2051
+
data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
2052
+
2053
+
mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
2054
+
2055
+
return (~data) & mask;
2056
+
}
2057
+
2058
+
static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
2059
+
struct amdgpu_cu_info *cu_info)
2060
+
{
2061
+
int i, j, k, counter, active_cu_number = 0;
2062
+
u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
2063
+
unsigned disable_masks[4 * 4];
2064
+
2065
+
if (!adev || !cu_info)
2066
+
return -EINVAL;
2067
+
2068
+
/*
2069
+
* 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
2070
+
*/
2071
+
if (adev->gfx.config.max_shader_engines *
2072
+
adev->gfx.config.max_sh_per_se > 16)
2073
+
return -EINVAL;
2074
+
2075
+
amdgpu_gfx_parse_disable_cu(disable_masks,
2076
+
adev->gfx.config.max_shader_engines,
2077
+
adev->gfx.config.max_sh_per_se);
2078
+
2079
+
mutex_lock(&adev->grbm_idx_mutex);
2080
+
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2081
+
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2082
+
mask = 1;
2083
+
ao_bitmap = 0;
2084
+
counter = 0;
2085
+
gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff);
2086
+
gfx_v9_4_3_set_user_cu_inactive_bitmap(
2087
+
adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
2088
+
bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev);
2089
+
2090
+
/*
2091
+
* The bitmap(and ao_cu_bitmap) in cu_info structure is
2092
+
* 4x4 size array, and it's usually suitable for Vega
2093
+
* ASICs which has 4*2 SE/SH layout.
2094
+
* But for Arcturus, SE/SH layout is changed to 8*1.
2095
+
* To mostly reduce the impact, we make it compatible
2096
+
* with current bitmap array as below:
2097
+
* SE4,SH0 --> bitmap[0][1]
2098
+
* SE5,SH0 --> bitmap[1][1]
2099
+
* SE6,SH0 --> bitmap[2][1]
2100
+
* SE7,SH0 --> bitmap[3][1]
2101
+
*/
2102
+
cu_info->bitmap[i % 4][j + i / 4] = bitmap;
2103
+
2104
+
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2105
+
if (bitmap & mask) {
2106
+
if (counter < adev->gfx.config.max_cu_per_sh)
2107
+
ao_bitmap |= mask;
2108
+
counter++;
2109
+
}
2110
+
mask <<= 1;
2111
+
}
2112
+
active_cu_number += counter;
2113
+
if (i < 2 && j < 2)
2114
+
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
2115
+
cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
2116
+
}
2117
+
}
2118
+
gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2119
+
mutex_unlock(&adev->grbm_idx_mutex);
2120
+
2121
+
cu_info->number = active_cu_number;
2122
+
cu_info->ao_cu_mask = ao_cu_mask;
2123
+
cu_info->simd_per_cu = NUM_SIMD_PER_CU;
2124
+
2125
+
return 0;
2126
+
}
2127
+
2128
+
const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
2129
+
.type = AMD_IP_BLOCK_TYPE_GFX,
2130
+
.major = 9,
2131
+
.minor = 4,
2132
+
.rev = 0,
2133
+
.funcs = &gfx_v9_4_3_ip_funcs,
1346
2134
};
+1
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h
+1
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h
···
24
24
#ifndef __GFX_V9_4_3_H__
25
25
#define __GFX_V9_4_3_H__
26
26
27
-
extern const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs;
28
-
extern const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs;
27
+
extern const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block;
29
28
30
29
#endif /* __GFX_V9_4_3_H__ */