Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/dram: Use REG_GENMASK() & co. for the SKL+ DIMM regs
Modernize the SKL/ICL DIMM registers with REG_GENMASK() & co.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251029204215.12292-2-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
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-34
+23
-28
drivers/gpu/drm/i915/intel_mchbar_regs.h
+23
-28
drivers/gpu/drm/i915/intel_mchbar_regs.h
···
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#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
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#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
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#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
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#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
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#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
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#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
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#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
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#define SKL_DRAM_DDR_TYPE_MASK REG_GENMASK(1, 0)
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#define SKL_DRAM_DDR_TYPE_DDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 0)
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#define SKL_DRAM_DDR_TYPE_DDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 1)
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#define SKL_DRAM_DDR_TYPE_LPDDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 2)
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#define SKL_DRAM_DDR_TYPE_LPDDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 3)
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/* snb MCH registers for reading the DRAM channel configuration */
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#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
···
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#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
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#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
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#define SKL_DRAM_S_SHIFT 16
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#define SKL_DRAM_SIZE_MASK 0x3F
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#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
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#define SKL_DRAM_WIDTH_SHIFT 8
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#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
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#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
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#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
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#define SKL_DRAM_RANK_MASK (0x1 << 10)
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#define SKL_DRAM_RANK_SHIFT 10
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#define SKL_DRAM_RANK_1 (0x0 << 10)
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#define SKL_DRAM_RANK_2 (0x1 << 10)
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#define SKL_DRAM_RANK_MASK (0x1 << 10)
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#define ICL_DRAM_SIZE_MASK 0x7F
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#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
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#define ICL_DRAM_WIDTH_SHIFT 7
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#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
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#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
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#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
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#define ICL_DRAM_RANK_MASK (0x3 << 9)
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#define ICL_DRAM_RANK_SHIFT 9
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#define ICL_DRAM_RANK_1 (0x0 << 9)
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#define ICL_DRAM_RANK_2 (0x1 << 9)
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#define ICL_DRAM_RANK_3 (0x2 << 9)
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#define ICL_DRAM_RANK_4 (0x3 << 9)
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#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
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#define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8)
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#define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0)
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#define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1)
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#define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2)
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#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
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#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
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#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
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#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
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#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
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#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
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#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
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#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
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#define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9)
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#define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0)
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#define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1)
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#define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2)
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#define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3)
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#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
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#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
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drivers/gpu/drm/i915/soc/intel_dram.c
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drivers/gpu/drm/i915/soc/intel_dram.c
···
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/* Returns total Gb for the whole DIMM */
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static int skl_get_dimm_size(u16 val)
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{
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return (val & SKL_DRAM_SIZE_MASK) * 8;
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return REG_FIELD_GET(SKL_DRAM_SIZE_MASK, val) * 8;
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}
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static int skl_get_dimm_width(u16 val)
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case SKL_DRAM_WIDTH_X8:
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case SKL_DRAM_WIDTH_X16:
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case SKL_DRAM_WIDTH_X32:
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val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
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val = REG_FIELD_GET(SKL_DRAM_WIDTH_MASK, val);
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return 8 << val;
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default:
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MISSING_CASE(val);
···
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if (skl_get_dimm_size(val) == 0)
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return 0;
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val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
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val = REG_FIELD_GET(SKL_DRAM_RANK_MASK, val);
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return val + 1;
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}
···
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/* Returns total Gb for the whole DIMM */
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static int icl_get_dimm_size(u16 val)
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{
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return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
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return REG_FIELD_GET(ICL_DRAM_SIZE_MASK, val) * 8 / 2;
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}
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static int icl_get_dimm_width(u16 val)
···
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case ICL_DRAM_WIDTH_X8:
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case ICL_DRAM_WIDTH_X16:
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case ICL_DRAM_WIDTH_X32:
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val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
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val = REG_FIELD_GET(ICL_DRAM_WIDTH_MASK, val);
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return 8 << val;
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default:
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MISSING_CASE(val);
···
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if (icl_get_dimm_size(val) == 0)
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return 0;
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val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
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val = REG_FIELD_GET(ICL_DRAM_RANK_MASK, val);
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return val + 1;
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}