tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings

For SuperSpeed USB to work properly, there is a set of HW settings that
need to be programmed into the USB blocks within the QMP PHY. Ensure that
these settings follow the latest settings mentioned in the HW programming
guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some
new ways to define certain registers, such as the replacement of TXA/RXA
and TXB/RXB register sets. This was replaced with the LALB register set.

There are also some PHY init updates to modify the PCS MISC register space.
Without these, the QMP PHY PLL locking fails.

Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20251209-linux-next-12825-v8-8-42133596bda0@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Wesley Cheng and committed by
Vinod Koul 5b289913 c9543cca

+1212
+285
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 31 31 32 32 #include "phy-qcom-qmp.h" 33 33 #include "phy-qcom-qmp-pcs-aon-v6.h" 34 + #include "phy-qcom-qmp-pcs-aon-v8.h" 34 35 #include "phy-qcom-qmp-pcs-misc-v3.h" 35 36 #include "phy-qcom-qmp-pcs-misc-v4.h" 36 37 #include "phy-qcom-qmp-pcs-misc-v5.h" 38 + #include "phy-qcom-qmp-pcs-misc-v8.h" 37 39 #include "phy-qcom-qmp-pcs-usb-v4.h" 38 40 #include "phy-qcom-qmp-pcs-usb-v5.h" 39 41 #include "phy-qcom-qmp-pcs-usb-v6.h" ··· 48 46 #include "phy-qcom-qmp-dp-phy-v4.h" 49 47 #include "phy-qcom-qmp-dp-phy-v5.h" 50 48 #include "phy-qcom-qmp-dp-phy-v6.h" 49 + 50 + #include "phy-qcom-qmp-usb43-pcs-v8.h" 51 51 52 52 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 53 53 /* DP PHY soft reset */ ··· 102 98 QPHY_TX_HIGHZ_DRVR_EN, 103 99 QPHY_TX_TRANSCEIVER_BIAS_EN, 104 100 101 + QPHY_AON_TOGGLE_ENABLE, 105 102 /* Keep last to ensure regs_layout arrays are properly initialized */ 106 103 QPHY_LAYOUT_SIZE 107 104 }; ··· 263 258 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL, 264 259 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN, 265 260 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, 261 + }; 262 + 263 + static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = { 264 + [QPHY_SW_RESET] = QPHY_V8_USB43_PCS_SW_RESET, 265 + [QPHY_START_CTRL] = QPHY_V8_USB43_PCS_START_CONTROL, 266 + [QPHY_PCS_STATUS] = QPHY_V8_USB43_PCS_PCS_STATUS1, 267 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_USB43_PCS_POWER_DOWN_CONTROL, 268 + 269 + /* In PCS_USB */ 270 + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 271 + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 272 + 273 + [QPHY_PCS_CLAMP_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE, 274 + [QPHY_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE, 275 + 276 + [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 277 + [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 278 + [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 279 + [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 280 + 281 + [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_LALB_TX0_DRV_LVL, 282 + [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 283 + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_LALB_HIGHZ_DRVR_EN, 284 + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 285 + }; 286 + 287 + static const struct qmp_phy_init_tbl glymur_usb43dp_serdes_tbl[] = { 288 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1, 0xe1), 289 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1, 0x01), 290 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE1, 0x06), 291 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x16), 292 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x36), 293 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1, 0x02), 294 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1, 0x1a), 295 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1, 0x41), 296 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE1, 0x41), 297 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1, 0x00), 298 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1, 0xab), 299 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1, 0xaa), 300 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1, 0x01), 301 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x13), 302 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 303 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1, 0x4d), 304 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1, 0x03), 305 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x95), 306 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 307 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x4b), 308 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 309 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0xe1), 310 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x01), 311 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 312 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 313 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 314 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x05), 315 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x0a), 316 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x1a), 317 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x41), 318 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0, 0x00), 319 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0xab), 320 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xaa), 321 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01), 322 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 323 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 324 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0x4d), 325 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x03), 326 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a), 327 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00), 328 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x62), 329 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02), 330 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x0a), 331 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x0f), 332 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO_MODE1, 0x0f), 333 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x1a), 334 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x04), 335 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_CFG, 0x04), 336 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 337 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x14), 338 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0xa0), 339 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x76), 340 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x0a), 341 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x01), 342 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO, 0x40), 343 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), 344 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_2, 0x01), 345 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60), 346 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x05), 347 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x33), 348 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xaf), 349 + }; 350 + 351 + static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_misc_tbl[] = { 352 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_MISC_PCS_MISC_CONFIG1, 0x01), 353 + }; 354 + 355 + static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_tbl[] = { 356 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1, 0xc4), 357 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2, 0x89), 358 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3, 0x20), 359 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6, 0x13), 360 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1, 0x21), 361 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_SIGDET_LVL, 0x55), 362 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 363 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 364 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME, 0xa4), 365 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_CONFIG, 0x0a), 366 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_DLY_TIME, 0x04), 367 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 368 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2, 0x30), 369 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG, 0x0c), 370 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG1, 0x4b), 371 + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG5, 0x10), 372 + }; 373 + 374 + static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_usb_tbl[] = { 375 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 376 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 377 + }; 378 + 379 + static const struct qmp_phy_init_tbl glymur_usb43dp_lalb_tbl[] = { 380 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x81), 381 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0d), 382 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL1, 0x00), 383 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL2, 0x00), 384 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL3, 0x80), 385 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL4, 0x8D), 386 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x13), 387 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0c), 388 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x00), 389 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x11), 390 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_4, 0x11), 391 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), 392 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), 393 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), 394 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_VREF_SEL, 0x00), 395 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_VREF_SEL, 0x00), 396 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x00), 397 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x00), 398 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B0, 0xa4), 399 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B1, 0xa2), 400 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B2, 0x6e), 401 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B3, 0x51), 402 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B4, 0x0a), 403 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B5, 0x26), 404 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B6, 0x12), 405 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B7, 0x2a), 406 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B0, 0x4c), 407 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B1, 0xc4), 408 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B2, 0x38), 409 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B3, 0x64), 410 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B4, 0x0c), 411 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B5, 0x4b), 412 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B6, 0x12), 413 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B7, 0x0a), 414 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c), 415 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, 0x26), 416 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, 0x26), 417 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, 0x26), 418 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, 0x26), 419 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_0_1, 0x11), 420 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_2_3, 0x11), 421 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE1, 0x03), 422 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE2, 0x03), 423 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE1, 0x15), 424 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE1, 0x00), 425 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE2, 0x22), 426 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE2, 0x00), 427 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CODE_OVRD_RATE_2_3, 0x22), 428 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1, 0xff), 429 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE1, 0x00), 430 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2, 0xff), 431 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE2, 0x00), 432 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1, 0x07), 433 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2, 0x09), 434 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_SUMMER_CAL_SPD_MODE_RATE_0123, 0x2f), 435 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE1, 0x00), 436 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE2, 0x00), 437 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL2, 0x85), 438 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL3, 0x45), 439 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE1, 0x00), 440 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE2, 0x00), 441 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_ENABLES, 0x0c), 442 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CNTRL, 0xa3), 443 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_LVL, 0x04), 444 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_DEGLITCH_CNTRL, 0x0e), 445 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL1, 0x14), 446 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE, 0x00), 447 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_TRIM, 0x66), 448 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE1, 0xff), 449 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE2, 0x32), 450 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE1, 0x07), 451 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE2, 0x0a), 452 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE1, 0x02), 453 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE2, 0x04), 454 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_01, 0x76), 455 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_23, 0x67), 456 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_0_1, 0x20), 457 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_2_3, 0x02), 458 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_0_1, 0x33), 459 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_2_3, 0x43), 460 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_0_1, 0x00), 461 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_2_3, 0x51), 462 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_FLL_DIV_RATIO_RATE_0123, 0xe5), 463 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_RATE_0123, 0xf5), 464 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_TYPE_CONFIG, 0x1f), 465 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_EN_LOWFREQ, 0x07), 466 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_FUNC_CTRL, 0xd0), 467 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_EN, 0x1f), 468 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE0_1, 0x88), 469 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE2_3, 0x88), 470 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_AUX_CLK_CTRL, 0x20), 471 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_EOM_CTRL1, 0x10), 472 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 473 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL3, 0x0a), 474 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL4, 0xaa), 475 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CTLE_POST_CAL_OFFSET_RATE_0_1_2, 0x77), 476 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_CNTRL1, 0x00), 477 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE0_1, 0xdd), 478 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE2_3, 0xd8), 479 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP1_DAC_ENABLE, 0x1c), 480 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP2_DAC_ENABLE, 0x1c), 481 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP345_DAC_ENABLE, 0x18), 482 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP67_DAC_ENABLE, 0x10), 483 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_CTRL, 0x00), 484 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_MAN_INDEX, 0x10), 485 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_DIV2_CTRL_RATE0123, 0x1C), 486 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_OVRD_MUXES, 0x00), 487 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DIG_BKUP_CTRL16, 0x37), 266 488 }; 267 489 268 490 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ··· 1895 1663 { .supply = "vdda-pll", .init_load_uA = 36000, }, 1896 1664 }; 1897 1665 1666 + static struct regulator_bulk_data qmp_phy_vreg_refgen[] = { 1667 + { .supply = "vdda-phy", .init_load_uA = 21800 }, 1668 + { .supply = "vdda-pll", .init_load_uA = 36000 }, 1669 + { .supply = "refgen", .init_load_uA = 3270 }, 1670 + }; 1671 + 1898 1672 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1899 1673 { 0x00, 0x0c, 0x15, 0x1a }, 1900 1674 { 0x02, 0x0e, 0x16, 0xff }, ··· 2045 1807 int pcs_tbl_num; 2046 1808 const struct qmp_phy_init_tbl *pcs_usb_tbl; 2047 1809 int pcs_usb_tbl_num; 1810 + const struct qmp_phy_init_tbl *pcs_misc_tbl; 1811 + int pcs_misc_tbl_num; 2048 1812 2049 1813 const struct qmp_phy_init_tbl *dp_serdes_tbl; 2050 1814 int dp_serdes_tbl_num; ··· 2238 1998 .dp_txa = 0x3400, 2239 1999 .dp_txb = 0x3800, 2240 2000 .dp_dp_phy = 0x3c00, 2001 + }; 2002 + 2003 + static const struct qmp_combo_offsets qmp_combo_usb43dp_offsets_v8 = { 2004 + .com = 0x0000, 2005 + .usb3_pcs_aon = 0x0100, 2006 + .usb3_serdes = 0x1000, 2007 + .usb3_pcs_misc = 0x1400, 2008 + .usb3_pcs = 0x1600, 2009 + .usb3_pcs_usb = 0x1900, 2010 + .dp_serdes = 0x2000, 2011 + .dp_dp_phy = 0x2400, 2012 + .txa = 0x4000, 2013 + .txb = 0x5000, 2241 2014 }; 2242 2015 2243 2016 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { ··· 2797 2544 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2798 2545 }; 2799 2546 2547 + static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = { 2548 + .offsets = &qmp_combo_usb43dp_offsets_v8, 2549 + 2550 + .serdes_tbl = glymur_usb43dp_serdes_tbl, 2551 + .serdes_tbl_num = ARRAY_SIZE(glymur_usb43dp_serdes_tbl), 2552 + .tx_tbl = glymur_usb43dp_lalb_tbl, 2553 + .tx_tbl_num = ARRAY_SIZE(glymur_usb43dp_lalb_tbl), 2554 + .pcs_tbl = glymur_usb43dp_pcs_tbl, 2555 + .pcs_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_tbl), 2556 + .pcs_usb_tbl = glymur_usb43dp_pcs_usb_tbl, 2557 + .pcs_usb_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl), 2558 + .pcs_misc_tbl = glymur_usb43dp_pcs_misc_tbl, 2559 + .pcs_misc_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl), 2560 + 2561 + .regs = qmp_v8_n3_usb43dpphy_regs_layout, 2562 + .reset_list = msm8996_usb3phy_reset_l, 2563 + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2564 + .vreg_list = qmp_phy_vreg_refgen, 2565 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_refgen), 2566 + }; 2567 + 2800 2568 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 2801 2569 { 2802 2570 const struct qmp_phy_cfg *cfg = qmp->cfg; ··· 3314 3040 { 3315 3041 const struct qmp_phy_cfg *cfg = qmp->cfg; 3316 3042 void __iomem *com = qmp->com; 3043 + void __iomem *pcs_aon = qmp->pcs_aon; 3317 3044 int ret; 3318 3045 u32 val; 3319 3046 ··· 3349 3074 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3350 3075 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3351 3076 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3077 + 3078 + /* override hardware control for reset of qmp phy */ 3079 + if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) 3080 + qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); 3352 3081 3353 3082 /* Use software based port select and switch on typec orientation */ 3354 3083 val = SW_PORTSELECT_MUX; ··· 3531 3252 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 3532 3253 3533 3254 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 3255 + qmp_configure(qmp->dev, qmp->pcs_misc, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); 3256 + 3534 3257 3535 3258 if (pcs_usb) 3536 3259 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, ··· 4628 4347 } 4629 4348 4630 4349 static const struct of_device_id qmp_combo_of_match_table[] = { 4350 + { 4351 + .compatible = "qcom,glymur-qmp-usb3-dp-phy", 4352 + .data = &glymur_usb3dpphy_cfg, 4353 + }, 4631 4354 { 4632 4355 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 4633 4356 .data = &sar2130p_usb3dpphy_cfg,
+17
drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_AON_V8_H_ 7 + #define QCOM_PHY_QMP_PCS_AON_V8_H_ 8 + 9 + /* Only for QMP V8 PHY - PCS_AON registers */ 10 + #define QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE 0x00 11 + #define QPHY_V8_PCS_AON_USB4_AON_CLAMP_ENABLE 0x04 12 + #define QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE 0x08 13 + #define QPHY_V8_PCS_AON_USB4_AON_TOGGLE_ENABLE 0x0c 14 + #define QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE 0x10 15 + #define QPHY_V8_PCS_AON_DUMMY_STATUS 0x14 16 + 17 + #endif
+12
drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_MISC_V8_H_ 7 + #define QCOM_PHY_QMP_PCS_MISC_V8_H_ 8 + 9 + /* Only for QMP V8 PHY - PCS_MISC registers */ 10 + #define QPHY_V8_PCS_MISC_PCS_MISC_CONFIG1 0x08 11 + 12 + #endif
+639
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_V8_LALBH_ 7 + #define QCOM_PHY_QMP_QSERDES_V8_LALBH_ 8 + 9 + #define QSERDES_V8_LALB_BIST_MODE_LANENO 0x0 10 + #define QSERDES_V8_LALB_BIST_INVERT 0x4 11 + #define QSERDES_V8_LALB_PERL_LENGTH1 0x8 12 + #define QSERDES_V8_LALB_PERL_LENGTH2 0xc 13 + #define QSERDES_V8_LALB_BIST_PATTERN1 0x10 14 + #define QSERDES_V8_LALB_BIST_PATTERN2 0x14 15 + #define QSERDES_V8_LALB_BIST_PATTERN3 0x18 16 + #define QSERDES_V8_LALB_BIST_PATTERN4 0x1c 17 + #define QSERDES_V8_LALB_BIST_PATTERN5 0x20 18 + #define QSERDES_V8_LALB_BIST_PATTERN6 0x24 19 + #define QSERDES_V8_LALB_BIST_PATTERN7 0x28 20 + #define QSERDES_V8_LALB_BIST_PATTERN8 0x2c 21 + #define QSERDES_V8_LALB_PRBS_SEED1 0x30 22 + #define QSERDES_V8_LALB_PRBS_SEED2 0x34 23 + #define QSERDES_V8_LALB_PRBS_SEED3 0x38 24 + #define QSERDES_V8_LALB_PRBS_SEED4 0x3c 25 + #define QSERDES_V8_LALB_PRBS_SEED5 0x40 26 + #define QSERDES_V8_LALB_PRBS_SEED6 0x44 27 + #define QSERDES_V8_LALB_PRBS_SEED7 0x48 28 + #define QSERDES_V8_LALB_SW_RESET_PWRDNB 0x4c 29 + #define QSERDES_V8_LALB_RESET_GEN 0x50 30 + #define QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL 0x54 31 + #define QSERDES_V8_LALB_CDR_EN_RXEQ_RESET 0x58 32 + #define QSERDES_V8_LALB_CLKBUF_ENABLE 0x5c 33 + #define QSERDES_V8_LALB_TX0_EMP_POST1_LVL 0x60 34 + #define QSERDES_V8_LALB_TX1_EMP_POST1_LVL 0x64 35 + #define QSERDES_V8_LALB_TX0_IDLE_CTRL 0x68 36 + #define QSERDES_V8_LALB_TX1_IDLE_CTRL 0x6c 37 + #define QSERDES_V8_LALB_TX0_DRV_LVL 0x70 38 + #define QSERDES_V8_LALB_TX0_DRV_LVL_OFFSET 0x74 39 + #define QSERDES_V8_LALB_TX1_DRV_LVL 0x78 40 + #define QSERDES_V8_LALB_TX1_DRV_LVL_OFFSET 0x7c 41 + #define QSERDES_V8_LALB_TRAN_DRVR_EMP_EN 0x80 42 + #define QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL 0x84 43 + #define QSERDES_V8_LALB_TX0_PRE1_EMPH 0x88 44 + #define QSERDES_V8_LALB_TX1_PRE1_EMPH 0x8c 45 + #define QSERDES_V8_LALB_TX0_PRE2_EMPH 0x90 46 + #define QSERDES_V8_LALB_TX1_PRE2_EMPH 0x94 47 + #define QSERDES_V8_LALB_STALL_LDO_BOOST_EN 0x98 48 + #define QSERDES_V8_LALB_PRE_EMPH_EN_CTRL 0x9c 49 + #define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL1 0xa0 50 + #define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL2 0xa4 51 + #define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL3 0xa8 52 + #define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL4 0xac 53 + #define QSERDES_V8_LALB_TRANSMITTER_EN_CTRL 0xb0 54 + #define QSERDES_V8_LALB_HIGHZ_DRVR_EN 0xb4 55 + #define QSERDES_V8_LALB_TX_MISC_CTRL1 0xb8 56 + #define QSERDES_V8_LALB_LPB_EN_CTRL1 0xbc 57 + #define QSERDES_V8_LALB_LBP_EN_CTRL2 0xc0 58 + #define QSERDES_V8_LALB_TX0_SERDES_BYP_CTRL 0xc4 59 + #define QSERDES_V8_LALB_TX1_SERDES_BYP_CTRL 0xc8 60 + #define QSERDES_V8_LALB_LANE_MODE_1 0xcc 61 + #define QSERDES_V8_LALB_LANE_MODE_2 0xd0 62 + #define QSERDES_V8_LALB_LANE_MODE_3 0xd4 63 + #define QSERDES_V8_LALB_LANE_MODE_4 0xd8 64 + #define QSERDES_V8_LALB_ATB_SEL1 0xdc 65 + #define QSERDES_V8_LALB_ATB_SEL2 0xe0 66 + #define QSERDES_V8_LALB_TX0_RES_CODE_LANE 0xe4 67 + #define QSERDES_V8_LALB_TX0_RESTRIM_ICAL_OVRD 0xe8 68 + #define QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL 0xec 69 + #define QSERDES_V8_LALB_TX0_RESTRIM_INIT_CODE 0xf0 70 + #define QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET 0xf4 71 + #define QSERDES_V8_LALB_TX1_RES_CODE_LANE 0xf8 72 + #define QSERDES_V8_LALB_TX1_RESTRIM_ICAL_OVRD 0xfc 73 + #define QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL 0x100 74 + #define QSERDES_V8_LALB_TX1_RESTRIM_INIT_CODE 0x104 75 + #define QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET 0x108 76 + #define QSERDES_V8_LALB_TX0_RESTRIM_VREF_SEL 0x10c 77 + #define QSERDES_V8_LALB_TX1_RESTRIM_VREF_SEL 0x110 78 + #define QSERDES_V8_LALB_VMODE_CTRL1 0x114 79 + #define QSERDES_V8_LALB_SLEW_CNTL_RATE01 0x118 80 + #define QSERDES_V8_LALB_SLEW_CNTL_RATE23 0x11c 81 + #define QSERDES_V8_LALB_SLEW_CNTL_RATE4 0x120 82 + #define QSERDES_V8_LALB_ANA_INTERFACE_SELECT1 0x124 83 + #define QSERDES_V8_LALB_ANA_INTERFACE_SELECT2 0x128 84 + #define QSERDES_V8_LALB_ANA_INTERFACE_SELECT3 0x12c 85 + #define QSERDES_V8_LALB_PCS_INTERFACE_SELECT1 0x130 86 + #define QSERDES_V8_LALB_PCS_INTERFACE_SELECT2 0x134 87 + #define QSERDES_V8_LALB_LDO_TIMER_CTRL 0x138 88 + #define QSERDES_V8_LALB_AC_JTAG_ENABLE 0x13c 89 + #define QSERDES_V8_LALB_AC_JTAG_INITP 0x140 90 + #define QSERDES_V8_LALB_AC_JTAG_INITN 0x144 91 + #define QSERDES_V8_LALB_AC_JTAG_LVL 0x148 92 + #define QSERDES_V8_LALB_AC_JTAG_MODE 0x14c 93 + #define QSERDES_V8_LALB_AC_JTAG_RESET 0x150 94 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B0 0x154 95 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B1 0x158 96 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B2 0x15c 97 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B3 0x160 98 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B4 0x164 99 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B5 0x168 100 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B6 0x16c 101 + #define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B7 0x170 102 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B0 0x174 103 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B1 0x178 104 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B2 0x17c 105 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B3 0x180 106 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B4 0x184 107 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B5 0x188 108 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B6 0x18c 109 + #define QSERDES_V8_LALB_RX_MODE_RATE2_B7 0x190 110 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B0 0x194 111 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B1 0x198 112 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B2 0x19c 113 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B3 0x1a0 114 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B4 0x1a4 115 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B5 0x1a8 116 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B6 0x1ac 117 + #define QSERDES_V8_LALB_RX_MODE_RATE3_B7 0x1b0 118 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B0 0x1b4 119 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B1 0x1b8 120 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B2 0x1bc 121 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B3 0x1c0 122 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B4 0x1c4 123 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B5 0x1c8 124 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B6 0x1cc 125 + #define QSERDES_V8_LALB_RX_MODE_RATE4_B7 0x1d0 126 + #define QSERDES_V8_LALB_TX_DCC_ANA_CTRL1 0x1d4 127 + #define QSERDES_V8_LALB_TX_DCC_ANA_CTRL2 0x1d8 128 + #define QSERDES_V8_LALB_CMUX_DCC_CTRL1 0x1dc 129 + #define QSERDES_V8_LALB_CMUX_DCC_POSTCAL_OFFSET 0x1e0 130 + #define QSERDES_V8_LALB_CMUX_DCC_OVRD 0x1e4 131 + #define QSERDES_V8_LALB_TX_DCC_CTRL 0x1e8 132 + #define QSERDES_V8_LALB_TX0_CTUNE_DCC_CONFIG 0x1ec 133 + #define QSERDES_V8_LALB_TX0_CTUNE_DCC_POSTCAL_OFFSET 0x1f0 134 + #define QSERDES_V8_LALB_TX0_CTUNE_DCC_OVRD 0x1f4 135 + #define QSERDES_V8_LALB_TX0_FTUNE_MSB_DCC_CONFIG 0x1f8 136 + #define QSERDES_V8_LALB_TX0_FTUNE_MSB_DCC_OFFSET_AND_OVRD 0x1fc 137 + #define QSERDES_V8_LALB_TX0_FTUNE_LSB_DCC_CONFIG 0x200 138 + #define QSERDES_V8_LALB_TX0_FTUNE_LSB_DCC_OFFSET_AND_OVRD 0x204 139 + #define QSERDES_V8_LALB_TX1_CTUNE_DCC_CONFIG 0x208 140 + #define QSERDES_V8_LALB_TX1_CTUNE_DCC_POSTCAL_OFFSET 0x20c 141 + #define QSERDES_V8_LALB_TX1_CTUNE_DCC_OVRD 0x210 142 + #define QSERDES_V8_LALB_TX1_FTUNE_MSB_DCC_CONFIG 0x214 143 + #define QSERDES_V8_LALB_TX1_FTUNE_MSB_DCC_OFFSET_AND_OVRD 0x218 144 + #define QSERDES_V8_LALB_TX1_FTUNE_LSB_DCC_CONFIG 0x21c 145 + #define QSERDES_V8_LALB_TX1_FTUNE_LSB_DCC_OFFSET_AND_OVRD 0x220 146 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_CTRL 0x224 147 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_CODE_OVRD_RATE0 0x228 148 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_CODE_OVRD_RATE1 0x22c 149 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_CODE_OVRD_RATE2 0x230 150 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_CODE_OVRD_RATE3 0x234 151 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_CODE_OVRD_RATE4 0x238 152 + #define QSERDES_V8_LALB_CDR_VCO_CAL_CTRL 0x23c 153 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE0 0x240 154 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE0 0x244 155 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE1 0x248 156 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE1 0x24c 157 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE2 0x250 158 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE2 0x254 159 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE3 0x258 160 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE3 0x25c 161 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE4 0x260 162 + #define QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE4 0x264 163 + #define QSERDES_V8_LALB_CDR_VCTRL_RATE_0_1 0x268 164 + #define QSERDES_V8_LALB_CDR_VCTRL_RATE_2_3 0x26c 165 + #define QSERDES_V8_LALB_CDR_VCTRL_RATE_4 0x270 166 + #define QSERDES_V8_LALB_KVCO_INIT_RATE_0_1 0x274 167 + #define QSERDES_V8_LALB_KVCO_INIT_RATE_2_3 0x278 168 + #define QSERDES_V8_LALB_KVCO_INIT_RATE_4 0x27c 169 + #define QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE0 0x280 170 + #define QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE1 0x284 171 + #define QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE2 0x288 172 + #define QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE3 0x28c 173 + #define QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE4 0x290 174 + #define QSERDES_V8_LALB_KVCO_CAL_VCTRL_HIGH_RATE_0_1 0x294 175 + #define QSERDES_V8_LALB_KVCO_CAL_VCTRL_HIGH_RATE_2_3 0x298 176 + #define QSERDES_V8_LALB_KVCO_CAL_VCTRL_HIGH_RATE_4 0x29c 177 + #define QSERDES_V8_LALB_KVCO_CAL_VCTRL_LOW_RATE_0_1 0x2a0 178 + #define QSERDES_V8_LALB_KVCO_CAL_VCTRL_LOW_RATE_2_3 0x2a4 179 + #define QSERDES_V8_LALB_KVCO_CAL_VCTRL_LOW_RATE_4 0x2a8 180 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE0 0x2ac 181 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE0 0x2b0 182 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE1 0x2b4 183 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE1 0x2b8 184 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE2 0x2bc 185 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE2 0x2c0 186 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE3 0x2c4 187 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE3 0x2c8 188 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE4 0x2cc 189 + #define QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE4 0x2d0 190 + #define QSERDES_V8_LALB_KP_CDR_UP_DN 0x2d4 191 + #define QSERDES_V8_LALB_KP_CODE_OVRD_RATE_0_1 0x2d8 192 + #define QSERDES_V8_LALB_KP_CODE_OVRD_RATE_2_3 0x2dc 193 + #define QSERDES_V8_LALB_KP_CODE_OVRD_RATE4 0x2e0 194 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE0 0x2e4 195 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE0 0x2e8 196 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1 0x2ec 197 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE1 0x2f0 198 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2 0x2f4 199 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE2 0x2f8 200 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE3 0x2fc 201 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE3 0x300 202 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE4 0x304 203 + #define QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE4 0x308 204 + #define QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE0 0x30c 205 + #define QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1 0x310 206 + #define QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2 0x314 207 + #define QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE3 0x318 208 + #define QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE4 0x31c 209 + #define QSERDES_V8_LALB_CDR_KVCO_KP_CAL_FREQ_MEAS_CTRL 0x320 210 + #define QSERDES_V8_LALB_PLLLOCK_CMP_DEBUG_CTRL 0x324 211 + #define QSERDES_V8_LALB_PLLLOCK_CMP_DEBUG_CNT1 0x328 212 + #define QSERDES_V8_LALB_PLLLOCK_CMP_DEBUG_CNT2 0x32c 213 + #define QSERDES_V8_LALB_PLLLOCK_CMP_DEBUG_CNT3 0x330 214 + #define QSERDES_V8_LALB_RX_SUMMER_CAL_SPD_MODE_RATE_0123 0x334 215 + #define QSERDES_V8_LALB_RX_SUMMER_CAL_SPD_MODE_RATE_4 0x338 216 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE0 0x33c 217 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE1 0x340 218 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE2 0x344 219 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE3 0x348 220 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE4 0x34c 221 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CTRL1 0x350 222 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CTRL2 0x354 223 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CTRL3 0x358 224 + #define QSERDES_V8_LALB_RX_IVCM_CAL_CTRL4 0x35c 225 + #define QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE0 0x360 226 + #define QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE1 0x364 227 + #define QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE2 0x368 228 + #define QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE3 0x36c 229 + #define QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE4 0x370 230 + #define QSERDES_V8_LALB_RX_IDAC_I0_DC_OFFSETS 0x374 231 + #define QSERDES_V8_LALB_RX_IDAC_I0BAR_DC_OFFSETS 0x378 232 + #define QSERDES_V8_LALB_RX_IDAC_I1_DC_OFFSETS 0x37c 233 + #define QSERDES_V8_LALB_RX_IDAC_I1BAR_DC_OFFSETS 0x380 234 + #define QSERDES_V8_LALB_RX_IDAC_Q_DC_OFFSETS 0x384 235 + #define QSERDES_V8_LALB_RX_IDAC_QBAR_DC_OFFSETS 0x388 236 + #define QSERDES_V8_LALB_RX_IDAC_A_DC_OFFSETS 0x38c 237 + #define QSERDES_V8_LALB_RX_IDAC_ABAR_DC_OFFSETS 0x390 238 + #define QSERDES_V8_LALB_RX_IDAC_EN 0x394 239 + #define QSERDES_V8_LALB_DATA_SLICER_INIT_TIMER_CTRL 0x398 240 + #define QSERDES_V8_LALB_RX_IDAC_ENABLES 0x39c 241 + #define QSERDES_V8_LALB_RX_IDAC_SIGN 0x3a0 242 + #define QSERDES_V8_LALB_RX_IDAC_TSETTLE 0x3a4 243 + #define QSERDES_V8_LALB_SIGDET_ENABLES 0x3a8 244 + #define QSERDES_V8_LALB_SIGDET_CNTRL 0x3ac 245 + #define QSERDES_V8_LALB_SIGDET_LVL 0x3b0 246 + #define QSERDES_V8_LALB_SIGDET_DEGLITCH_CNTRL 0x3b4 247 + #define QSERDES_V8_LALB_SIGDET_CAL_CTRL1 0x3b8 248 + #define QSERDES_V8_LALB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x3bc 249 + #define QSERDES_V8_LALB_SIGDET_CAL_TRIM 0x3c0 250 + #define QSERDES_V8_LALB_IA_OFFSET_CENTER_CAL_CTRL 0x3c4 251 + #define QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE0 0x3c8 252 + #define QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE1 0x3cc 253 + #define QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE2 0x3d0 254 + #define QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE3 0x3d4 255 + #define QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE4 0x3d8 256 + #define QSERDES_V8_LALB_CDR_PHASE_LOCK_CNT_RATE0 0x3dc 257 + #define QSERDES_V8_LALB_CDR_PHASE_LOCK_CNT_RATE1 0x3e0 258 + #define QSERDES_V8_LALB_CDR_PHASE_LOCK_CNT_RATE2 0x3e4 259 + #define QSERDES_V8_LALB_CDR_PHASE_LOCK_CNT_RATE3 0x3e8 260 + #define QSERDES_V8_LALB_CDR_PHASE_LOCK_CNT_RATE4 0x3ec 261 + #define QSERDES_V8_LALB_CDR_LOCK_CTRL 0x3f0 262 + #define QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE0 0x3f4 263 + #define QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE1 0x3f8 264 + #define QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE2 0x3fc 265 + #define QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE3 0x400 266 + #define QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE4 0x404 267 + #define QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE0 0x408 268 + #define QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE1 0x40c 269 + #define QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE2 0x410 270 + #define QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE3 0x414 271 + #define QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE4 0x418 272 + #define QSERDES_V8_LALB_CDR_FLL_DIV_RATIO_RATE_0123 0x41c 273 + #define QSERDES_V8_LALB_CDR_FLL_DIV_RATIO_RATE4 0x420 274 + #define QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_01 0x424 275 + #define QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_23 0x428 276 + #define QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE4 0x42c 277 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_0_1 0x430 278 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_2_3 0x434 279 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE4 0x438 280 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_0_1 0x43c 281 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_2_3 0x440 282 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE4 0x444 283 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_0_1 0x448 284 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_2_3 0x44c 285 + #define QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE4 0x450 286 + #define QSERDES_V8_LALB_CDR_VCO_CAP_CODE_RATE_0123 0x454 287 + #define QSERDES_V8_LALB_CDR_VCO_CAP_CODE_RATE4 0x458 288 + #define QSERDES_V8_LALB_CDR_VCO_TYPE_CONFIG 0x45c 289 + #define QSERDES_V8_LALB_CDR_VCO_EN_LOWFREQ 0x460 290 + #define QSERDES_V8_LALB_CDR_FAST_SLOW_VCO_OVRD 0x464 291 + #define QSERDES_V8_LALB_CDR_LOOP_FUNC_CTRL 0x468 292 + #define QSERDES_V8_LALB_CDR_FAST_LOCK_EN_CTRL 0x46c 293 + #define QSERDES_V8_LALB_RX_RCVR_EN 0x470 294 + #define QSERDES_V8_LALB_LANE_RATE_CTRL 0x474 295 + #define QSERDES_V8_LALB_RX_TERM_RCVR_CTRL 0x478 296 + #define QSERDES_V8_LALB_REC_DETECT_CTRL 0x47c 297 + #define QSERDES_V8_LALB_RCV_DETECT_LVL 0x480 298 + #define QSERDES_V8_LALB_GM_CAL_EN 0x484 299 + #define QSERDES_V8_LALB_GM_CAL_RES_RATE0_1 0x488 300 + #define QSERDES_V8_LALB_GM_CAL_RES_RATE2_3 0x48c 301 + #define QSERDES_V8_LALB_GM_CAL_RES_RATE4 0x490 302 + #define QSERDES_V8_LALB_RX_TERM_BW_RATE_0123 0x494 303 + #define QSERDES_V8_LALB_RX_TERM_BW_RATE4 0x498 304 + #define QSERDES_V8_LALB_AUX_CLK_CTRL 0x49c 305 + #define QSERDES_V8_LALB_AUX_OFFSET_CONTROL 0x4a0 306 + #define QSERDES_V8_LALB_AUXDATA_TB 0x4a4 307 + #define QSERDES_V8_LALB_EOM_CTRL1 0x4a8 308 + #define QSERDES_V8_LALB_EOM_CTRL2 0x4ac 309 + #define QSERDES_V8_LALB_EOM_CTRL3 0x4b0 310 + #define QSERDES_V8_LALB_EOM_CTRL4 0x4b4 311 + #define QSERDES_V8_LALB_DFE_EN_TIMER 0x4b8 312 + #define QSERDES_V8_LALB_RX_EQ_OFFSET_LSB 0x4bc 313 + #define QSERDES_V8_LALB_RX_EQ_OFFSET_MSB 0x4c0 314 + #define QSERDES_V8_LALB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x4c4 315 + #define QSERDES_V8_LALB_RX_OFFSET_ADAPTOR_CNTRL2 0x4c8 316 + #define QSERDES_V8_LALB_RX_OFFSET_ADAPTOR_CNTRL3 0x4cc 317 + #define QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL1 0x4d0 318 + #define QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL2 0x4d4 319 + #define QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL3 0x4d8 320 + #define QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL4 0x4dc 321 + #define QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL5 0x4e0 322 + #define QSERDES_V8_LALB_RX_EQU_KEQ_UP_LSB 0x4e4 323 + #define QSERDES_V8_LALB_RX_EQU_KEQ_UP_MSB 0x4e8 324 + #define QSERDES_V8_LALB_RX_EQU_KEQ_DN_LSB 0x4ec 325 + #define QSERDES_V8_LALB_RX_EQU_KEQ_DN_MSB 0x4f0 326 + #define QSERDES_V8_LALB_CTLE_ADP_RESET_INIT_CODE_RATE_0_1_2 0x4f4 327 + #define QSERDES_V8_LALB_CTLE_ADP_RESET_INIT_CODE_RATE_3_4 0x4f8 328 + #define QSERDES_V8_LALB_CTLE_POST_CAL_OFFSET_RATE_0_1_2 0x4fc 329 + #define QSERDES_V8_LALB_CTLE_POST_CAL_OFFSET_RATE_3_4 0x500 330 + #define QSERDES_V8_LALB_RX_VGA_GAIN2_BLK1 0x504 331 + #define QSERDES_V8_LALB_RX_VGA_GAIN2_BLK2 0x508 332 + #define QSERDES_V8_LALB_VGA_CAL_CNTRL1 0x50c 333 + #define QSERDES_V8_LALB_VGA_CAL_CNTRL2 0x510 334 + #define QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE0_1 0x514 335 + #define QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE2_3 0x518 336 + #define QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE4 0x51c 337 + #define QSERDES_V8_LALB_KVGA_CTRL1 0x520 338 + #define QSERDES_V8_LALB_KVGA_CTRL2 0x524 339 + #define QSERDES_V8_LALB_VTHRESH_CAL_CNTRL1 0x528 340 + #define QSERDES_V8_LALB_VTHRESH_CAL_CNTRL2 0x52c 341 + #define QSERDES_V8_LALB_VTHRESH_CAL_MAN_VAL_RATE0 0x530 342 + #define QSERDES_V8_LALB_VTHRESH_CAL_MAN_VAL_RATE1 0x534 343 + #define QSERDES_V8_LALB_VTHRESH_CAL_MAN_VAL_RATE2 0x538 344 + #define QSERDES_V8_LALB_VTHRESH_CAL_MAN_VAL_RATE3 0x53c 345 + #define QSERDES_V8_LALB_VTHRESH_CAL_MAN_VAL_RATE4 0x540 346 + #define QSERDES_V8_LALB_VTHRESH_CAL_MAN_CAL_PAM3 0x544 347 + #define QSERDES_V8_LALB_VTH_POST_CAL_OFFSET_RATE_0_1 0x548 348 + #define QSERDES_V8_LALB_VTH_POST_CAL_OFFSET_RATE_2_3 0x54c 349 + #define QSERDES_V8_LALB_VTH_POST_CAL_OFFSET_RATE4 0x550 350 + #define QSERDES_V8_LALB_DFE_TAP1_CTRL 0x554 351 + #define QSERDES_V8_LALB_DFE_TAP1_MANVAL_KTAP 0x558 352 + #define QSERDES_V8_LALB_DFE_TAP1_POST_CAL_OFFSET_RATE_0_1_2 0x55c 353 + #define QSERDES_V8_LALB_DFE_TAP1_POST_CAL_OFFSET_RATE_3_4 0x560 354 + #define QSERDES_V8_LALB_DFE_TAP2_CTRL 0x564 355 + #define QSERDES_V8_LALB_DFE_TAP2_MANVAL_KTAP 0x568 356 + #define QSERDES_V8_LALB_DFE_TAP3_CTRL 0x56c 357 + #define QSERDES_V8_LALB_DFE_TAP3_MANVAL_KTAP 0x570 358 + #define QSERDES_V8_LALB_DFE_TAP4_CTRL 0x574 359 + #define QSERDES_V8_LALB_DFE_TAP4_MANVAL_KTAP 0x578 360 + #define QSERDES_V8_LALB_DFE_TAP5_CTRL 0x57c 361 + #define QSERDES_V8_LALB_DFE_TAP5_MANVAL_KTAP 0x580 362 + #define QSERDES_V8_LALB_DFE_TAP6_CTRL 0x584 363 + #define QSERDES_V8_LALB_DFE_TAP6_MANVAL_KTAP 0x588 364 + #define QSERDES_V8_LALB_DFE_TAP7_CTRL 0x58c 365 + #define QSERDES_V8_LALB_DFE_TAP7_MANVAL_KTAP 0x590 366 + #define QSERDES_V8_LALB_DFE_TAP1_DAC_ENABLE 0x594 367 + #define QSERDES_V8_LALB_DFE_TAP2_DAC_ENABLE 0x598 368 + #define QSERDES_V8_LALB_DFE_TAP345_DAC_ENABLE 0x59c 369 + #define QSERDES_V8_LALB_DFE_TAP67_DAC_ENABLE 0x5a0 370 + #define QSERDES_V8_LALB_CDR_IQTUNE_CTRL 0x5a4 371 + #define QSERDES_V8_LALB_CDR_IQTUNE_GAIN 0x5a8 372 + #define QSERDES_V8_LALB_CDR_IQTUNE_MAN_INDEX 0x5ac 373 + #define QSERDES_V8_LALB_CDR_IQTUNE_FILTER_CAL_CTRL1 0x5b0 374 + #define QSERDES_V8_LALB_CDR_IQTUNE_FILTER_CAL_CTRL2 0x5b4 375 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK0_CAL_CODE_RATE0 0x5b8 376 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK0_CAL_CODE_RATE1 0x5bc 377 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK0_CAL_CODE_RATE2 0x5c0 378 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK0_CAL_CODE_RATE3 0x5c4 379 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK0_CAL_CODE_RATE4 0x5c8 380 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK90_CAL_CODE_RATE0 0x5cc 381 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK90_CAL_CODE_RATE1 0x5d0 382 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK90_CAL_CODE_RATE2 0x5d4 383 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK90_CAL_CODE_RATE3 0x5d8 384 + #define QSERDES_V8_LALB_CDR_IQTUNE_CLK90_CAL_CODE_RATE4 0x5dc 385 + #define QSERDES_V8_LALB_CDR_IQTUNE_ANA_CTRL 0x5e0 386 + #define QSERDES_V8_LALB_CDR_IQTUNE_VDCC_CTRL 0x5e4 387 + #define QSERDES_V8_LALB_CDR_IQTUNE_DIV2_CTRL_RATE0123 0x5e8 388 + #define QSERDES_V8_LALB_CDR_IQTUNE_DIV2_CTRL_RATE4 0x5ec 389 + #define QSERDES_V8_LALB_BLW_CTRL 0x5f0 390 + #define QSERDES_V8_LALB_BLW_ANA_VER_CTRL 0x5f4 391 + #define QSERDES_V8_LALB_BLW_GAIN_CAL_CTRL 0x5f8 392 + #define QSERDES_V8_LALB_BLW_GAIN_FORCE_CODE 0x5fc 393 + #define QSERDES_V8_LALB_BLW_MAN_VAL_RATE3 0x600 394 + #define QSERDES_V8_LALB_BLW_MAN_VAL_RATE4 0x604 395 + #define QSERDES_V8_LALB_IVTH_CAL_CTRL1 0x608 396 + #define QSERDES_V8_LALB_IVTH_CAL_CTRL2 0x60c 397 + #define QSERDES_V8_LALB_IVTH_CAL_CTRL3 0x610 398 + #define QSERDES_V8_LALB_VTH_I_UP_CNTRL_VAL 0x614 399 + #define QSERDES_V8_LALB_VTH_I_DN_CNTRL_VAL 0x618 400 + #define QSERDES_V8_LALB_NRZ_EYE_HEIGHT_SEL_VAL 0x61c 401 + #define QSERDES_V8_LALB_IVTH_CAL_VAL_OVRD_MUX 0x620 402 + #define QSERDES_V8_LALB_CDR_VCO_CAP_CODE_OVRD_MUXES 0x624 403 + #define QSERDES_V8_LALB_VCO_CTUNE_LOWER_BND_RATE0 0x628 404 + #define QSERDES_V8_LALB_VCO_CTUNE_LOWER_BND_RATE1 0x62c 405 + #define QSERDES_V8_LALB_VCO_CTUNE_LOWER_BND_RATE2 0x630 406 + #define QSERDES_V8_LALB_VCO_CTUNE_LOWER_BND_RATE3 0x634 407 + #define QSERDES_V8_LALB_VCO_CTUNE_LOWER_BND_RATE4 0x638 408 + #define QSERDES_V8_LALB_VCO_CTUNE_UPPER_BND_RATE0 0x63c 409 + #define QSERDES_V8_LALB_VCO_CTUNE_UPPER_BND_RATE1 0x640 410 + #define QSERDES_V8_LALB_VCO_CTUNE_UPPER_BND_RATE2 0x644 411 + #define QSERDES_V8_LALB_VCO_CTUNE_UPPER_BND_RATE3 0x648 412 + #define QSERDES_V8_LALB_VCO_CTUNE_UPPER_BND_RATE4 0x64c 413 + #define QSERDES_V8_LALB_CDR_LOCK_KVCO_OFFSET_RATE0 0x650 414 + #define QSERDES_V8_LALB_CDR_LOCK_KVCO_OFFSET_RATE1 0x654 415 + #define QSERDES_V8_LALB_CDR_LOCK_KVCO_OFFSET_RATE2 0x658 416 + #define QSERDES_V8_LALB_CDR_LOCK_KVCO_OFFSET_RATE3 0x65c 417 + #define QSERDES_V8_LALB_CDR_LOCK_KVCO_OFFSET_RATE4 0x660 418 + #define QSERDES_V8_LALB_CDR_LOCK_KP_OFFSET_RATE0 0x664 419 + #define QSERDES_V8_LALB_CDR_LOCK_KP_OFFSET_RATE1 0x668 420 + #define QSERDES_V8_LALB_CDR_LOCK_KP_OFFSET_RATE2 0x66c 421 + #define QSERDES_V8_LALB_CDR_LOCK_KP_OFFSET_RATE3 0x670 422 + #define QSERDES_V8_LALB_CDR_LOCK_KP_OFFSET_RATE4 0x674 423 + #define QSERDES_V8_LALB_CDR_FASTLOCK_CP_CUR_PLL_RATE0 0x678 424 + #define QSERDES_V8_LALB_CDR_FASTLOCK_CP_CUR_PLL_RATE1 0x67c 425 + #define QSERDES_V8_LALB_CDR_FASTLOCK_CP_CUR_PLL_RATE2 0x680 426 + #define QSERDES_V8_LALB_CDR_FASTLOCK_CP_CUR_PLL_RATE3 0x684 427 + #define QSERDES_V8_LALB_CDR_FASTLOCK_CP_CUR_PLL_RATE4 0x688 428 + #define QSERDES_V8_LALB_DEBUG_BUS_SEL 0x68c 429 + #define QSERDES_V8_LALB_BIST_STATUS 0x690 430 + #define QSERDES_V8_LALB_BIST_ERROR_COUNT1 0x694 431 + #define QSERDES_V8_LALB_BIST_ERROR_COUNT2 0x698 432 + #define QSERDES_V8_LALB_AC_JTAG_OUTP 0x69c 433 + #define QSERDES_V8_LALB_AC_JTAG_OUTN 0x6a0 434 + #define QSERDES_V8_LALB_DATA_SLICER_DEBUG_STATUS 0x6a4 435 + #define QSERDES_V8_LALB_DATA_SLICER_TIMER1_STATUS 0x6a8 436 + #define QSERDES_V8_LALB_DATA_SLICER_TIMER2_STATUS 0x6ac 437 + #define QSERDES_V8_LALB_TX0_RESTRIM_CODE_STATUS 0x6b0 438 + #define QSERDES_V8_LALB_TX0_RESTRIM_ICAL_CODE_STATUS 0x6b4 439 + #define QSERDES_V8_LALB_TX0_RESTRIM_CAL_STATUS 0x6b8 440 + #define QSERDES_V8_LALB_TX1_RESTRIM_CODE_STATUS 0x6bc 441 + #define QSERDES_V8_LALB_TX1_RESTRIM_ICAL_CODE_STATUS 0x6c0 442 + #define QSERDES_V8_LALB_TX1_RESTRIM_CAL_STATUS 0x6c4 443 + #define QSERDES_V8_LALB_CMUX_DCC_CAL_FSM_STATUS 0x6c8 444 + #define QSERDES_V8_LALB_CMUX_DCC_READCODE_STATUS 0x6cc 445 + #define QSERDES_V8_LALB_TX_DCC_CAL_ANA_STATUS 0x6d0 446 + #define QSERDES_V8_LALB_TX0_CTUNE_DCC_FSM_DEBUG_STATUS 0x6d4 447 + #define QSERDES_V8_LALB_TX0_COARSE_DCC_READCODE_STATUS 0x6d8 448 + #define QSERDES_V8_LALB_TX0_FTUNE_MSB_DCC_FSM_DEBUG_STATUS 0x6dc 449 + #define QSERDES_V8_LALB_TX0_FTUNE_LSB_DCC_FSM_DEBUG_STATUS 0x6e0 450 + #define QSERDES_V8_LALB_TX0_FINE_DCC_READCODE_STATUS 0x6e4 451 + #define QSERDES_V8_LALB_TX1_CTUNE_DCC_FSM_DEBUG_STATUS 0x6e8 452 + #define QSERDES_V8_LALB_TX1_COARSE_DCC_READCODE_STATUS 0x6ec 453 + #define QSERDES_V8_LALB_TX1_FTUNE_MSB_DCC_FSM_DEBUG_STATUS 0x6f0 454 + #define QSERDES_V8_LALB_TX1_FTUNE_LSB_DCC_FSM_DEBUG_STATUS 0x6f4 455 + #define QSERDES_V8_LALB_TX1_FINE_DCC_READCODE_STATUS 0x6f8 456 + #define QSERDES_V8_LALB_CDR_VCO_CAL_STATUS 0x6fc 457 + #define QSERDES_V8_LALB_CDR_VCTRL_STATUS 0x700 458 + #define QSERDES_V8_LALB_CDR_VCO_CAP_CODE_STATUS 0x704 459 + #define QSERDES_V8_LALB_KVCO_CAL_DEBUG1_STATUS 0x708 460 + #define QSERDES_V8_LALB_KVCO_CAL_DEBUG2_STATUS 0x70c 461 + #define QSERDES_V8_LALB_KP_CAL_DEBUG1_STATUS 0x710 462 + #define QSERDES_V8_LALB_KP_CAL_DEBUG2_STATUS 0x714 463 + #define QSERDES_V8_LALB_CDR_VCO_FREQ_DEBUG1_STATUS 0x718 464 + #define QSERDES_V8_LALB_CDR_VCO_FREQ_DEBUG2_STATUS 0x71c 465 + #define QSERDES_V8_LALB_CDR_VCO_FREQ_DEBUG3_STATUS 0x720 466 + #define QSERDES_V8_LALB_CDR_VCO_FREQ_DEBUG4_STATUS 0x724 467 + #define QSERDES_V8_LALB_IVCM_CAL_STATUS 0x728 468 + #define QSERDES_V8_LALB_IVCM_CAL_DEBUG_STATUS 0x72c 469 + #define QSERDES_V8_LALB_IDAC_STATUS_I0 0x730 470 + #define QSERDES_V8_LALB_IDAC_STATUS_I0BAR 0x734 471 + #define QSERDES_V8_LALB_IDAC_STATUS_I1 0x738 472 + #define QSERDES_V8_LALB_IDAC_STATUS_I1BAR 0x73c 473 + #define QSERDES_V8_LALB_IDAC_STATUS_Q 0x740 474 + #define QSERDES_V8_LALB_IDAC_STATUS_QBAR 0x744 475 + #define QSERDES_V8_LALB_IDAC_STATUS_A 0x748 476 + #define QSERDES_V8_LALB_IDAC_STATUS_ABAR 0x74c 477 + #define QSERDES_V8_LALB_IDAC_STATUS_SM_ON 0x750 478 + #define QSERDES_V8_LALB_IDAC_STATUS_SIGNERROR 0x754 479 + #define QSERDES_V8_LALB_RX_SIGDET_STATUS 0x758 480 + #define QSERDES_V8_LALB_SIGDET_CAL_CODE_STATUS 0x75c 481 + #define QSERDES_V8_LALB_SIGDET_CAL_FSM_DEBUG_STATUS 0x760 482 + #define QSERDES_V8_LALB_CDR_FREQ_LOCK_CNT_STATUS 0x764 483 + #define QSERDES_V8_LALB_CDR_PHASE_LOCK_CNT_STATUS 0x768 484 + #define QSERDES_V8_LALB_CDR_LOCK_DEBUG_STATUS 0x76c 485 + #define QSERDES_V8_LALB_IDATA_HIGH_STATUS1 0x770 486 + #define QSERDES_V8_LALB_IDATA_HIGH_STATUS2 0x774 487 + #define QSERDES_V8_LALB_IDATA_HIGH_STATUS3 0x778 488 + #define QSERDES_V8_LALB_IDATA_HIGH_STATUS4 0x77c 489 + #define QSERDES_V8_LALB_IDATA_LOW_STATUS1 0x780 490 + #define QSERDES_V8_LALB_IDATA_LOW_STATUS2 0x784 491 + #define QSERDES_V8_LALB_IDATA_LOW_STATUS3 0x788 492 + #define QSERDES_V8_LALB_IDATA_LOW_STATUS4 0x78c 493 + #define QSERDES_V8_LALB_QDATA_STATUS1 0x790 494 + #define QSERDES_V8_LALB_QDATA_STATUS2 0x794 495 + #define QSERDES_V8_LALB_QDATA_STATUS3 0x798 496 + #define QSERDES_V8_LALB_QDATA_STATUS4 0x79c 497 + #define QSERDES_V8_LALB_IA_ERROR_COUNTER_LOW 0x7a0 498 + #define QSERDES_V8_LALB_IA_ERROR_COUNTER_HIGH 0x7a4 499 + #define QSERDES_V8_LALB_EOM_ERR_CNT_LSB_STATUS 0x7a8 500 + #define QSERDES_V8_LALB_EOM_ERR_CNT_MSB_STATUS 0x7ac 501 + #define QSERDES_V8_LALB_EOM_OP_STATUS 0x7b0 502 + #define QSERDES_V8_LALB_AUX_MIXER_INDEX_STATUS 0x7b4 503 + #define QSERDES_V8_LALB_AUX_OFFSET_STATUS 0x7b8 504 + #define QSERDES_V8_LALB_AUXDATA_TB_STATUS 0x7bc 505 + #define QSERDES_V8_LALB_AUX_MIXER_CTRL_0_STATUS 0x7c0 506 + #define QSERDES_V8_LALB_AUX_MIXER_CTRL_90_STATUS 0x7c4 507 + #define QSERDES_V8_LALB_AUX_MIXER_CTRL_180_STATUS 0x7c8 508 + #define QSERDES_V8_LALB_IQ_MIXER_INDEX_STATUS 0x7cc 509 + #define QSERDES_V8_LALB_IQTUNE_FLTR_INDEX_STATUS 0x7d0 510 + #define QSERDES_V8_LALB_IQ_MIXER_CTRL_0_STATUS 0x7d4 511 + #define QSERDES_V8_LALB_IQ_MIXER_CTRL_90_STATUS 0x7d8 512 + #define QSERDES_V8_LALB_IQ_MIXER_CTRL_180_STATUS 0x7dc 513 + #define QSERDES_V8_LALB_READ_EQCODE 0x7e0 514 + #define QSERDES_V8_LALB_READ_OFFSETCODE 0x7e4 515 + #define QSERDES_V8_LALB_VGA_READ_CODE 0x7e8 516 + #define QSERDES_V8_LALB_VTHRESH_READ_CODE 0x7ec 517 + #define QSERDES_V8_LALB_DFE_TAP1_READ_CODE 0x7f0 518 + #define QSERDES_V8_LALB_DFE_TAP2_READ_CODE 0x7f4 519 + #define QSERDES_V8_LALB_DFE_TAP3_READ_CODE 0x7f8 520 + #define QSERDES_V8_LALB_DFE_TAP4_READ_CODE 0x7fc 521 + #define QSERDES_V8_LALB_DFE_TAP5_READ_CODE 0x800 522 + #define QSERDES_V8_LALB_DFE_TAP6_READ_CODE 0x804 523 + #define QSERDES_V8_LALB_DFE_TAP7_READ_CODE 0x808 524 + #define QSERDES_V8_LALB_CDR_IQTUNE_FILTER_BIN_CODE 0x80c 525 + #define QSERDES_V8_LALB_CDR_IQTUNE_FILTER_CLK0_CODE 0x810 526 + #define QSERDES_V8_LALB_CDR_IQTUNE_FILTER_CLK90_CODE 0x814 527 + #define QSERDES_V8_LALB_BLW_READ_CODE 0x818 528 + #define QSERDES_V8_LALB_IA_OFFSET_CAL_DEBUG_STATUS 0x81c 529 + #define QSERDES_V8_LALB_IA_OFFSET_CAL_STATUS 0x820 530 + #define QSERDES_V8_LALB_IVTH_CAL_STATUS 0x824 531 + #define QSERDES_V8_LALB_IVTH_NRZ_EYE_HEIGHT_STATUS 0x828 532 + #define QSERDES_V8_LALB_IVTH_UPPER_EYE_MAX_STATUS 0x82c 533 + #define QSERDES_V8_LALB_IVTH_UPPER_EYE_MIN_STATUS 0x830 534 + #define QSERDES_V8_LALB_IVTH_LOWER_EYE_MAX_STATUS 0x834 535 + #define QSERDES_V8_LALB_IVTH_LOWER_EYE_MIN_STATUS 0x838 536 + #define QSERDES_V8_LALB_IVTH_UP_INIT_CTR_STATUS 0x83c 537 + #define QSERDES_V8_LALB_VTH_I_UP_CNTRL_STATUS 0x840 538 + #define QSERDES_V8_LALB_VTH_I_DN_CNTRL_STATUS 0x844 539 + #define QSERDES_V8_LALB_NRZ_EYE_HEIGHT_SEL_STATUS 0x848 540 + #define QSERDES_V8_LALB_DEBUG_BUS0 0x84c 541 + #define QSERDES_V8_LALB_DEBUG_BUS1 0x850 542 + #define QSERDES_V8_LALB_DEBUG_BUS2 0x854 543 + #define QSERDES_V8_LALB_DEBUG_BUS3 0x858 544 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL1 0x85c 545 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL2 0x860 546 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL3 0x864 547 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL4 0x868 548 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL5 0x86c 549 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL6 0x870 550 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL7 0x874 551 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL8 0x878 552 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL9 0x87c 553 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL10 0x880 554 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL11 0x884 555 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL12 0x888 556 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL13 0x88c 557 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL14 0x890 558 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL15 0x894 559 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL16 0x898 560 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL17 0x89c 561 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL18 0x8a0 562 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL19 0x8a4 563 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL20 0x8a8 564 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL21 0x8ac 565 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL22 0x8b0 566 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL23 0x8b4 567 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL24 0x8b8 568 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL25 0x8bc 569 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL26 0x8c0 570 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL27 0x8c4 571 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL28 0x8c8 572 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL29 0x8cc 573 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL30 0x8d0 574 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL31 0x8d4 575 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL32 0x8d8 576 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL_V2_1 0x8dc 577 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL_V2_2 0x8e0 578 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL_V2_3 0x8e4 579 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL_V2_4 0x8e8 580 + #define QSERDES_V8_LALB_DIG_BKUP_CTRL_V2_5 0x8ec 581 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS1 0x8f0 582 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS2 0x8f4 583 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS3 0x8f8 584 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS4 0x8fc 585 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS5 0x900 586 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS6 0x904 587 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS7 0x908 588 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS8 0x90c 589 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS9 0x910 590 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS10 0x914 591 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS11 0x918 592 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS12 0x91c 593 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS13 0x920 594 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS14 0x924 595 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS15 0x928 596 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS16 0x92c 597 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS17 0x930 598 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS18 0x934 599 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS19 0x938 600 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS20 0x93c 601 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS21 0x940 602 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS22 0x944 603 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS23 0x948 604 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS24 0x94c 605 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS25 0x950 606 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS26 0x954 607 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS27 0x958 608 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS28 0x95c 609 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS29 0x960 610 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS30 0x964 611 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS31 0x968 612 + #define QSERDES_V8_LALB_DIG_BKUP_RO_BUS32 0x96c 613 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS1 0x970 614 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS2 0x974 615 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS3 0x978 616 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS4 0x97c 617 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS5 0x980 618 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS6 0x984 619 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS7 0x988 620 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS8 0x98c 621 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS9 0x990 622 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS10 0x994 623 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS11 0x998 624 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS12 0x99c 625 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS13 0x9a0 626 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS14 0x9a4 627 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS15 0x9a8 628 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS16 0x9ac 629 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS17 0x9b0 630 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS18 0x9b4 631 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS19 0x9b8 632 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS20 0x9bc 633 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS21 0x9c0 634 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS22 0x9c4 635 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS23 0x9c8 636 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS24 0x9cc 637 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS25 0x9d0 638 + #define QSERDES_V8_LALB_DIG_BKUP_RO_V2_BUS26 0x9d4 639 + #endif /* QCOM_PHY_QMP_QSERDES_V8_LALBH_ */
+33
drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_USB43_PCS_V8_H_ 7 + #define QCOM_PHY_QMP_USB43_PCS_V8_H_ 8 + 9 + #define QPHY_V8_USB43_PCS_SW_RESET 0x000 10 + #define QPHY_V8_USB43_PCS_PCS_STATUS1 0x014 11 + #define QPHY_V8_USB43_PCS_POWER_DOWN_CONTROL 0x040 12 + #define QPHY_V8_USB43_PCS_START_CONTROL 0x044 13 + #define QPHY_V8_USB43_PCS_POWER_STATE_CONFIG1 0x090 14 + #define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1 0x0c4 15 + #define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2 0x0c8 16 + #define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3 0x0cc 17 + #define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6 0x0d8 18 + #define QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1 0x0dc 19 + #define QPHY_V8_USB43_PCS_RX_SIGDET_LVL 0x188 20 + #define QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 21 + #define QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 22 + #define QPHY_V8_USB43_PCS_RATE_SLEW_CNTRL1 0x198 23 + #define QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME 0x1ac 24 + #define QPHY_V8_USB43_PCS_RX_CONFIG 0x1b0 25 + #define QPHY_V8_USB43_PCS_TSYNC_DLY_TIME 0x1b4 26 + #define QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1 0x1c0 27 + #define QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2 0x1c4 28 + #define QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG 0x1d0 29 + #define QPHY_V8_USB43_PCS_EQ_CONFIG1 0x1dc 30 + #define QPHY_V8_USB43_PCS_EQ_CONFIG2 0x1e0 31 + #define QPHY_V8_USB43_PCS_EQ_CONFIG5 0x1ec 32 + 33 + #endif
+224
drivers/phy/qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_USB43_QSERDES_COM_V8_H_ 7 + #define QCOM_PHY_QMP_USB43_QSERDES_COM_V8_H_ 8 + 9 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1 0x000 10 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1 0x004 11 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE1 0x008 12 + #define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE1 0x00c 13 + #define QSERDES_V8_USB43_COM_CP_CTRL_MODE1 0x010 14 + #define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1 0x014 15 + #define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1 0x018 16 + #define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1 0x01c 17 + #define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1 0x020 18 + #define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1 0x024 19 + #define QSERDES_V8_USB43_COM_DEC_START_MODE1 0x028 20 + #define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1 0x02c 21 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1 0x030 22 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1 0x034 23 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1 0x038 24 + #define QSERDES_V8_USB43_COM_HSCLK_SEL_1 0x03c 25 + #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1 0x040 26 + #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE1 0x044 27 + #define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1 0x048 28 + #define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1 0x04c 29 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050 30 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054 31 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 32 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c 33 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0 0x060 34 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0 0x064 35 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE0 0x068 36 + #define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE0 0x06c 37 + #define QSERDES_V8_USB43_COM_CP_CTRL_MODE0 0x070 38 + #define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0 0x074 39 + #define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0 0x078 40 + #define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0 0x07c 41 + #define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0 0x080 42 + #define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0 0x084 43 + #define QSERDES_V8_USB43_COM_DEC_START_MODE0 0x088 44 + #define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0 0x08c 45 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0 0x090 46 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0 0x094 47 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0 0x098 48 + #define QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1 0x09c 49 + #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 50 + #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 51 + #define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0 0x0a8 52 + #define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0 0x0ac 53 + #define QSERDES_V8_USB43_COM_ATB_SEL1 0x0b0 54 + #define QSERDES_V8_USB43_COM_ATB_SEL2 0x0b4 55 + #define QSERDES_V8_USB43_COM_FREQ_UPDATE 0x0b8 56 + #define QSERDES_V8_USB43_COM_BG_TIMER 0x0bc 57 + #define QSERDES_V8_USB43_COM_SSC_EN_CENTER 0x0c0 58 + #define QSERDES_V8_USB43_COM_SSC_ADJ_PER1 0x0c4 59 + #define QSERDES_V8_USB43_COM_SSC_ADJ_PER2 0x0c8 60 + #define QSERDES_V8_USB43_COM_SSC_PER1 0x0cc 61 + #define QSERDES_V8_USB43_COM_SSC_PER2 0x0d0 62 + #define QSERDES_V8_USB43_COM_POST_DIV 0x0d4 63 + #define QSERDES_V8_USB43_COM_POST_DIV_MUX 0x0d8 64 + #define QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN 0x0dc 65 + #define QSERDES_V8_USB43_COM_CLK_ENABLE1 0x0e0 66 + #define QSERDES_V8_USB43_COM_SYS_CLK_CTRL 0x0e4 67 + #define QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE 0x0e8 68 + #define QSERDES_V8_USB43_COM_PLL_EN 0x0ec 69 + #define QSERDES_V8_USB43_COM_DEBUG_BUS_OVRD 0x0f0 70 + #define QSERDES_V8_USB43_COM_PLL_IVCO 0x0f4 71 + #define QSERDES_V8_USB43_COM_PLL_IVCO_MODE1 0x0f8 72 + #define QSERDES_V8_USB43_COM_CMN_IETRIM 0x0fc 73 + #define QSERDES_V8_USB43_COM_CMN_IPTRIM 0x100 74 + #define QSERDES_V8_USB43_COM_EP_CLOCK_DETECT_CTRL 0x104 75 + #define QSERDES_V8_USB43_COM_PLL_CNTRL 0x108 76 + #define QSERDES_V8_USB43_COM_BIAS_EN_CTRL_BY_PSM 0x10c 77 + #define QSERDES_V8_USB43_COM_SYSCLK_EN_SEL 0x110 78 + #define QSERDES_V8_USB43_COM_CML_SYSCLK_SEL 0x114 79 + #define QSERDES_V8_USB43_COM_RESETSM_CNTRL 0x118 80 + #define QSERDES_V8_USB43_COM_RESETSM_CNTRL2 0x11c 81 + #define QSERDES_V8_USB43_COM_LOCK_CMP_EN 0x120 82 + #define QSERDES_V8_USB43_COM_LOCK_CMP_CFG 0x124 83 + #define QSERDES_V8_USB43_COM_INTEGLOOP_INITVAL 0x128 84 + #define QSERDES_V8_USB43_COM_INTEGLOOP_EN 0x12c 85 + #define QSERDES_V8_USB43_COM_INTEGLOOP_P_PATH_GAIN0 0x130 86 + #define QSERDES_V8_USB43_COM_INTEGLOOP_P_PATH_GAIN1 0x134 87 + #define QSERDES_V8_USB43_COM_VCOCAL_DEADMAN_CTRL 0x138 88 + #define QSERDES_V8_USB43_COM_VCO_TUNE_CTRL 0x13c 89 + #define QSERDES_V8_USB43_COM_VCO_TUNE_MAP 0x140 90 + #define QSERDES_V8_USB43_COM_VCO_TUNE_INITVAL1 0x144 91 + #define QSERDES_V8_USB43_COM_VCO_TUNE_INITVAL2 0x148 92 + #define QSERDES_V8_USB43_COM_VCO_TUNE_MINVAL1 0x14c 93 + #define QSERDES_V8_USB43_COM_VCO_TUNE_MINVAL2 0x150 94 + #define QSERDES_V8_USB43_COM_VCO_TUNE_MAXVAL1 0x154 95 + #define QSERDES_V8_USB43_COM_VCO_TUNE_MAXVAL2 0x158 96 + #define QSERDES_V8_USB43_COM_VCO_TUNE_TIMER1 0x15c 97 + #define QSERDES_V8_USB43_COM_VCO_TUNE_TIMER2 0x160 98 + #define QSERDES_V8_USB43_COM_CLK_SELECT 0x164 99 + #define QSERDES_V8_USB43_COM_PLL_ANALOG 0x168 100 + #define QSERDES_V8_USB43_COM_SW_RESET 0x16c 101 + #define QSERDES_V8_USB43_COM_CORE_CLK_EN 0x170 102 + #define QSERDES_V8_USB43_COM_CMN_CONFIG_1 0x174 103 + #define QSERDES_V8_USB43_COM_CMN_CONFIG_3 0x178 104 + #define QSERDES_V8_USB43_COM_CMN_RATE_OVERRIDE 0x17c 105 + #define QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL 0x180 106 + #define QSERDES_V8_USB43_COM_DEBUG_BUS_SEL 0x184 107 + #define QSERDES_V8_USB43_COM_CMN_MISC1 0x188 108 + #define QSERDES_V8_USB43_COM_CMN_MODE 0x18c 109 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD 0x190 110 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD1 0x194 111 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD2 0x198 112 + #define QSERDES_V8_USB43_COM_VCO_DC_LEVEL_CTRL 0x19c 113 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1 0x1a0 114 + #define QSERDES_V8_USB43_COM_ADDITIONAL_CTRL_1 0x1a4 115 + #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a8 116 + #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_2 0x1ac 117 + #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_3 0x1b0 118 + #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_4 0x1b4 119 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC 0x1b8 120 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_2 0x1bc 121 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_3 0x1c0 122 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_4 0x1c4 123 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_5 0x1c8 124 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE2 0x1cc 125 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE2 0x1d0 126 + #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE2 0x1d4 127 + #define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE2 0x1d8 128 + #define QSERDES_V8_USB43_COM_CP_CTRL_MODE2 0x1dc 129 + #define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE2 0x1e0 130 + #define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE2 0x1e4 131 + #define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE2 0x1e8 132 + #define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE2 0x1ec 133 + #define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE2 0x1f0 134 + #define QSERDES_V8_USB43_COM_DEC_START_MODE2 0x1f4 135 + #define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE2 0x1f8 136 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE2 0x1fc 137 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE2 0x200 138 + #define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE2 0x204 139 + #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE2 0x208 140 + #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE2 0x20c 141 + #define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE2 0x210 142 + #define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE2 0x214 143 + #define QSERDES_V8_USB43_COM_PLL_IVCO_MODE2 0x218 144 + #define QSERDES_V8_USB43_COM_HSCLK_SEL_2 0x21c 145 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE2 0x220 146 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE2 0x224 147 + #define QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_2 0x228 148 + #define QSERDES_V8_USB43_COM_CMN_CONFIG_2 0x22c 149 + #define QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_2 0x230 150 + #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_0 0x234 151 + #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_1 0x238 152 + #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_2 0x23c 153 + #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_3 0x240 154 + #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_4 0x244 155 + #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_5 0x248 156 + #define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE0 0x24c 157 + #define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE0 0x250 158 + #define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE1 0x254 159 + #define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE1 0x258 160 + #define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE2 0x25c 161 + #define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE2 0x260 162 + #define QSERDES_V8_USB43_COM_EARLY_LOCK_CONFIG_0 0x264 163 + #define QSERDES_V8_USB43_COM_EARLY_LOCK_CONFIG_1 0x268 164 + #define QSERDES_V8_USB43_COM_ADAPTIVE_ANALOG_CONFIG 0x26c 165 + #define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE0 0x270 166 + #define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x274 167 + #define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x278 168 + #define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE1 0x27c 169 + #define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x280 170 + #define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x284 171 + #define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE2 0x288 172 + #define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE2 0x28c 173 + #define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE2 0x290 174 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD3 0x294 175 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD4 0x298 176 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD5 0x29c 177 + #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD6 0x2a0 178 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_6 0x2a4 179 + #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_7 0x2a8 180 + #define QSERDES_V8_USB43_COM_VCO_WAIT_CYCLES 0x2ac 181 + #define QSERDES_V8_USB43_COM_BIAS_WAIT_CYCLES 0x2b0 182 + #define QSERDES_V8_USB43_COM_AUX_CLK_PSM_ENABLE 0x2b4 183 + #define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO 0x2b8 184 + #define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO_1 0x2bc 185 + #define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO_2 0x2c0 186 + #define QSERDES_V8_USB43_COM_LDO_CAL_1 0x2c4 187 + #define QSERDES_V8_USB43_COM_LDO_CAL_2 0x2c8 188 + #define QSERDES_V8_USB43_COM_LDO_CAL_3 0x2cc 189 + #define QSERDES_V8_USB43_COM_LDO_CAL_4 0x2d0 190 + #define QSERDES_V8_USB43_COM_LDO_CAL_5 0x2d4 191 + #define QSERDES_V8_USB43_COM_DCC_CAL_1 0x2d8 192 + #define QSERDES_V8_USB43_COM_DCC_CAL_2 0x2dc 193 + #define QSERDES_V8_USB43_COM_DCC_CAL_3 0x2e0 194 + #define QSERDES_V8_USB43_COM_DCC_CAL_4 0x2e4 195 + #define QSERDES_V8_USB43_COM_DCC_CAL_5 0x2e8 196 + #define QSERDES_V8_USB43_COM_DCC_CAL_6 0x2ec 197 + #define QSERDES_V8_USB43_COM_PSM_CAL_EN 0x2f0 198 + #define QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1 0x2f4 199 + #define QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_2 0x2f8 200 + #define QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL 0x2fc 201 + #define QSERDES_V8_USB43_COM_DCC_CAL_7 0x300 202 + #define QSERDES_V8_USB43_COM_DCC_CAL_8 0x304 203 + #define QSERDES_V8_USB43_COM_DCC_CAL_9 0x308 204 + #define QSERDES_V8_USB43_COM_MODE_OPERATION_STATUS 0x30c 205 + #define QSERDES_V8_USB43_COM_SYSCLK_DET_COMP_STATUS 0x310 206 + #define QSERDES_V8_USB43_COM_CMN_STATUS 0x314 207 + #define QSERDES_V8_USB43_COM_RESET_SM_STATUS 0x318 208 + #define QSERDES_V8_USB43_COM_RESTRIM_CODE_STATUS 0x31c 209 + #define QSERDES_V8_USB43_COM_PLLCAL_CODE1_STATUS 0x320 210 + #define QSERDES_V8_USB43_COM_PLLCAL_CODE2_STATUS 0x324 211 + #define QSERDES_V8_USB43_COM_INTEGLOOP_BINCODE_STATUS 0x328 212 + #define QSERDES_V8_USB43_COM_DEBUG_BUS0 0x32c 213 + #define QSERDES_V8_USB43_COM_DEBUG_BUS1 0x330 214 + #define QSERDES_V8_USB43_COM_DEBUG_BUS2 0x334 215 + #define QSERDES_V8_USB43_COM_DEBUG_BUS3 0x338 216 + #define QSERDES_V8_USB43_COM_C_READY_STATUS 0x33c 217 + #define QSERDES_V8_USB43_COM_READ_DUMMY_1 0x340 218 + #define QSERDES_V8_USB43_COM_READ_DUMMY_2 0x344 219 + #define QSERDES_V8_USB43_COM_READ_DUMMY_3 0x348 220 + #define QSERDES_V8_USB43_COM_IVCO_CAL_CODE_STATUS 0x34c 221 + #define QSERDES_V8_USB43_COM_PLL_LDO_CAL_STATUS_2 0x350 222 + #define QSERDES_V8_USB43_COM_PLL_LDO_CAL_STATUS_3 0x354 223 + 224 + #endif
+2
drivers/phy/qualcomm/phy-qcom-qmp.h
··· 35 35 #include "phy-qcom-qmp-qserdes-txrx-v7.h" 36 36 37 37 #include "phy-qcom-qmp-qserdes-com-v8.h" 38 + #include "phy-qcom-qmp-usb43-qserdes-com-v8.h" 38 39 #include "phy-qcom-qmp-qserdes-txrx-v8.h" 40 + #include "phy-qcom-qmp-qserdes-lalb-v8.h" 39 41 40 42 #include "phy-qcom-qmp-qserdes-pll.h" 41 43