Merge tag 'drm-intel-fixes-2015-12-23' of git://anongit.freedesktop.org/drm-intel

+20 -8

drivers/gpu/drm/i915/i915_drv.h

··· 2193 2193 struct drm_i915_private *i915; 2194 2194 struct intel_engine_cs *ring; 2195 2195 2196 - /** GEM sequence number associated with this request. */ 2197 - uint32_t seqno; 2196 + /** GEM sequence number associated with the previous request, 2197 + * when the HWS breadcrumb is equal to this the GPU is processing 2198 + * this request. 2199 + */ 2200 + u32 previous_seqno; 2201 + 2202 + /** GEM sequence number associated with this request, 2203 + * when the HWS breadcrumb is equal or greater than this the GPU 2204 + * has finished processing this request. 2205 + */ 2206 + u32 seqno; 2198 2207 2199 2208 /** Position in the ringbuffer of the start of the request */ 2200 2209 u32 head; ··· 2848 2839 2849 2840 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 2850 2841 u32 flags); 2842 + void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); 2851 2843 int __must_check i915_vma_unbind(struct i915_vma *vma); 2852 2844 /* 2853 2845 * BEWARE: Do not use the function below unless you can _absolutely_ ··· 2920 2910 return (int32_t)(seq1 - seq2) >= 0; 2921 2911 } 2922 2912 2913 + static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, 2914 + bool lazy_coherency) 2915 + { 2916 + u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2917 + return i915_seqno_passed(seqno, req->previous_seqno); 2918 + } 2919 + 2923 2920 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, 2924 2921 bool lazy_coherency) 2925 2922 { 2926 - u32 seqno; 2927 - 2928 - BUG_ON(req == NULL); 2929 - 2930 - seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2931 - 2923 + u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2932 2924 return i915_seqno_passed(seqno, req->seqno); 2933 2925 } 2934 2926

+84 -27

drivers/gpu/drm/i915/i915_gem.c

··· 1146 1146 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); 1147 1147 } 1148 1148 1149 - static int __i915_spin_request(struct drm_i915_gem_request *req) 1149 + static unsigned long local_clock_us(unsigned *cpu) 1150 + { 1151 + unsigned long t; 1152 + 1153 + /* Cheaply and approximately convert from nanoseconds to microseconds. 1154 + * The result and subsequent calculations are also defined in the same 1155 + * approximate microseconds units. The principal source of timing 1156 + * error here is from the simple truncation. 1157 + * 1158 + * Note that local_clock() is only defined wrt to the current CPU; 1159 + * the comparisons are no longer valid if we switch CPUs. Instead of 1160 + * blocking preemption for the entire busywait, we can detect the CPU 1161 + * switch and use that as indicator of system load and a reason to 1162 + * stop busywaiting, see busywait_stop(). 1163 + */ 1164 + *cpu = get_cpu(); 1165 + t = local_clock() >> 10; 1166 + put_cpu(); 1167 + 1168 + return t; 1169 + } 1170 + 1171 + static bool busywait_stop(unsigned long timeout, unsigned cpu) 1172 + { 1173 + unsigned this_cpu; 1174 + 1175 + if (time_after(local_clock_us(&this_cpu), timeout)) 1176 + return true; 1177 + 1178 + return this_cpu != cpu; 1179 + } 1180 + 1181 + static int __i915_spin_request(struct drm_i915_gem_request *req, int state) 1150 1182 { 1151 1183 unsigned long timeout; 1184 + unsigned cpu; 1152 1185 1153 - if (i915_gem_request_get_ring(req)->irq_refcount) 1186 + /* When waiting for high frequency requests, e.g. during synchronous 1187 + * rendering split between the CPU and GPU, the finite amount of time 1188 + * required to set up the irq and wait upon it limits the response 1189 + * rate. By busywaiting on the request completion for a short while we 1190 + * can service the high frequency waits as quick as possible. However, 1191 + * if it is a slow request, we want to sleep as quickly as possible. 1192 + * The tradeoff between waiting and sleeping is roughly the time it 1193 + * takes to sleep on a request, on the order of a microsecond. 1194 + */ 1195 + 1196 + if (req->ring->irq_refcount) 1154 1197 return -EBUSY; 1155 1198 1156 - timeout = jiffies + 1; 1199 + /* Only spin if we know the GPU is processing this request */ 1200 + if (!i915_gem_request_started(req, true)) 1201 + return -EAGAIN; 1202 + 1203 + timeout = local_clock_us(&cpu) + 5; 1157 1204 while (!need_resched()) { 1158 1205 if (i915_gem_request_completed(req, true)) 1159 1206 return 0; 1160 1207 1161 - if (time_after_eq(jiffies, timeout)) 1208 + if (signal_pending_state(state, current)) 1209 + break; 1210 + 1211 + if (busywait_stop(timeout, cpu)) 1162 1212 break; 1163 1213 1164 1214 cpu_relax_lowlatency(); 1165 1215 } 1216 + 1166 1217 if (i915_gem_request_completed(req, false)) 1167 1218 return 0; 1168 1219 ··· 1248 1197 struct drm_i915_private *dev_priv = dev->dev_private; 1249 1198 const bool irq_test_in_progress = 1250 1199 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); 1200 + int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; 1251 1201 DEFINE_WAIT(wait); 1252 1202 unsigned long timeout_expire; 1253 1203 s64 before, now; ··· 1281 1229 before = ktime_get_raw_ns(); 1282 1230 1283 1231 /* Optimistic spin for the next jiffie before touching IRQs */ 1284 - ret = __i915_spin_request(req); 1232 + ret = __i915_spin_request(req, state); 1285 1233 if (ret == 0) 1286 1234 goto out; 1287 1235 ··· 1293 1241 for (;;) { 1294 1242 struct timer_list timer; 1295 1243 1296 - prepare_to_wait(&ring->irq_queue, &wait, 1297 - interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); 1244 + prepare_to_wait(&ring->irq_queue, &wait, state); 1298 1245 1299 1246 /* We need to check whether any gpu reset happened in between 1300 1247 * the caller grabbing the seqno and now ... */ ··· 1311 1260 break; 1312 1261 } 1313 1262 1314 - if (interruptible && signal_pending(current)) { 1263 + if (signal_pending_state(state, current)) { 1315 1264 ret = -ERESTARTSYS; 1316 1265 break; 1317 1266 } ··· 2605 2554 request->batch_obj = obj; 2606 2555 2607 2556 request->emitted_jiffies = jiffies; 2557 + request->previous_seqno = ring->last_submitted_seqno; 2608 2558 ring->last_submitted_seqno = request->seqno; 2609 2559 list_add_tail(&request->list, &ring->request_list); 2610 2560 ··· 4132 4080 return false; 4133 4081 } 4134 4082 4083 + void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) 4084 + { 4085 + struct drm_i915_gem_object *obj = vma->obj; 4086 + bool mappable, fenceable; 4087 + u32 fence_size, fence_alignment; 4088 + 4089 + fence_size = i915_gem_get_gtt_size(obj->base.dev, 4090 + obj->base.size, 4091 + obj->tiling_mode); 4092 + fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, 4093 + obj->base.size, 4094 + obj->tiling_mode, 4095 + true); 4096 + 4097 + fenceable = (vma->node.size == fence_size && 4098 + (vma->node.start & (fence_alignment - 1)) == 0); 4099 + 4100 + mappable = (vma->node.start + fence_size <= 4101 + to_i915(obj->base.dev)->gtt.mappable_end); 4102 + 4103 + obj->map_and_fenceable = mappable && fenceable; 4104 + } 4105 + 4135 4106 static int 4136 4107 i915_gem_object_do_pin(struct drm_i915_gem_object *obj, 4137 4108 struct i915_address_space *vm, ··· 4222 4147 4223 4148 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && 4224 4149 (bound ^ vma->bound) & GLOBAL_BIND) { 4225 - bool mappable, fenceable; 4226 - u32 fence_size, fence_alignment; 4227 - 4228 - fence_size = i915_gem_get_gtt_size(obj->base.dev, 4229 - obj->base.size, 4230 - obj->tiling_mode); 4231 - fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, 4232 - obj->base.size, 4233 - obj->tiling_mode, 4234 - true); 4235 - 4236 - fenceable = (vma->node.size == fence_size && 4237 - (vma->node.start & (fence_alignment - 1)) == 0); 4238 - 4239 - mappable = (vma->node.start + fence_size <= 4240 - dev_priv->gtt.mappable_end); 4241 - 4242 - obj->map_and_fenceable = mappable && fenceable; 4243 - 4150 + __i915_vma_set_map_and_fenceable(vma); 4244 4151 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); 4245 4152 } 4246 4153

+1

drivers/gpu/drm/i915/i915_gem_gtt.c

··· 2676 2676 return ret; 2677 2677 } 2678 2678 vma->bound |= GLOBAL_BIND; 2679 + __i915_vma_set_map_and_fenceable(vma); 2679 2680 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list); 2680 2681 } 2681 2682

+1

drivers/gpu/drm/i915/i915_gem_stolen.c

··· 687 687 } 688 688 689 689 vma->bound |= GLOBAL_BIND; 690 + __i915_vma_set_map_and_fenceable(vma); 690 691 list_add_tail(&vma->mm_list, &ggtt->inactive_list); 691 692 } 692 693

+44 -22

drivers/gpu/drm/i915/intel_display.c

··· 116 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); 117 117 static void ironlake_pfit_enable(struct intel_crtc *crtc); 118 118 static void intel_modeset_setup_hw_state(struct drm_device *dev); 119 + static void intel_pre_disable_primary(struct drm_crtc *crtc); 119 120 120 121 typedef struct { 121 122 int min, max; ··· 2608 2607 struct drm_i915_gem_object *obj; 2609 2608 struct drm_plane *primary = intel_crtc->base.primary; 2610 2609 struct drm_plane_state *plane_state = primary->state; 2610 + struct drm_crtc_state *crtc_state = intel_crtc->base.state; 2611 + struct intel_plane *intel_plane = to_intel_plane(primary); 2611 2612 struct drm_framebuffer *fb; 2612 2613 2613 2614 if (!plane_config->fb) ··· 2645 2642 goto valid_fb; 2646 2643 } 2647 2644 } 2645 + 2646 + /* 2647 + * We've failed to reconstruct the BIOS FB. Current display state 2648 + * indicates that the primary plane is visible, but has a NULL FB, 2649 + * which will lead to problems later if we don't fix it up. The 2650 + * simplest solution is to just disable the primary plane now and 2651 + * pretend the BIOS never had it enabled. 2652 + */ 2653 + to_intel_plane_state(plane_state)->visible = false; 2654 + crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); 2655 + intel_pre_disable_primary(&intel_crtc->base); 2656 + intel_plane->disable_plane(primary, &intel_crtc->base); 2648 2657 2649 2658 return; 2650 2659 ··· 9925 9910 return true; 9926 9911 } 9927 9912 9928 - static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 9913 + static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) 9929 9914 { 9930 9915 struct drm_device *dev = crtc->dev; 9931 9916 struct drm_i915_private *dev_priv = dev->dev_private; 9932 9917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9933 9918 uint32_t cntl = 0, size = 0; 9934 9919 9935 - if (base) { 9920 + if (on) { 9936 9921 unsigned int width = intel_crtc->base.cursor->state->crtc_w; 9937 9922 unsigned int height = intel_crtc->base.cursor->state->crtc_h; 9938 9923 unsigned int stride = roundup_pow_of_two(width) * 4; ··· 9987 9972 } 9988 9973 } 9989 9974 9990 - static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 9975 + static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) 9991 9976 { 9992 9977 struct drm_device *dev = crtc->dev; 9993 9978 struct drm_i915_private *dev_priv = dev->dev_private; 9994 9979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9995 9980 int pipe = intel_crtc->pipe; 9996 - uint32_t cntl; 9981 + uint32_t cntl = 0; 9997 9982 9998 - cntl = 0; 9999 - if (base) { 9983 + if (on) { 10000 9984 cntl = MCURSOR_GAMMA_ENABLE; 10001 9985 switch (intel_crtc->base.cursor->state->crtc_w) { 10002 9986 case 64: ··· 10046 10032 int y = cursor_state->crtc_y; 10047 10033 u32 base = 0, pos = 0; 10048 10034 10049 - if (on) 10050 - base = intel_crtc->cursor_addr; 10035 + base = intel_crtc->cursor_addr; 10051 10036 10052 10037 if (x >= intel_crtc->config->pipe_src_w) 10053 - base = 0; 10038 + on = false; 10054 10039 10055 10040 if (y >= intel_crtc->config->pipe_src_h) 10056 - base = 0; 10041 + on = false; 10057 10042 10058 10043 if (x < 0) { 10059 10044 if (x + cursor_state->crtc_w <= 0) 10060 - base = 0; 10045 + on = false; 10061 10046 10062 10047 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 10063 10048 x = -x; ··· 10065 10052 10066 10053 if (y < 0) { 10067 10054 if (y + cursor_state->crtc_h <= 0) 10068 - base = 0; 10055 + on = false; 10069 10056 10070 10057 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 10071 10058 y = -y; 10072 10059 } 10073 10060 pos |= y << CURSOR_Y_SHIFT; 10074 - 10075 - if (base == 0 && intel_crtc->cursor_base == 0) 10076 - return; 10077 10061 10078 10062 I915_WRITE(CURPOS(pipe), pos); 10079 10063 ··· 10082 10072 } 10083 10073 10084 10074 if (IS_845G(dev) || IS_I865G(dev)) 10085 - i845_update_cursor(crtc, base); 10075 + i845_update_cursor(crtc, base, on); 10086 10076 else 10087 - i9xx_update_cursor(crtc, base); 10077 + i9xx_update_cursor(crtc, base, on); 10088 10078 } 10089 10079 10090 10080 static bool cursor_size_ok(struct drm_device *dev, ··· 13728 13718 struct drm_crtc *crtc = crtc_state->base.crtc; 13729 13719 struct drm_framebuffer *fb = state->base.fb; 13730 13720 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 13721 + enum pipe pipe = to_intel_plane(plane)->pipe; 13731 13722 unsigned stride; 13732 13723 int ret; 13733 13724 ··· 13762 13751 return -EINVAL; 13763 13752 } 13764 13753 13754 + /* 13755 + * There's something wrong with the cursor on CHV pipe C. 13756 + * If it straddles the left edge of the screen then 13757 + * moving it away from the edge or disabling it often 13758 + * results in a pipe underrun, and often that can lead to 13759 + * dead pipe (constant underrun reported, and it scans 13760 + * out just a solid color). To recover from that, the 13761 + * display power well must be turned off and on again. 13762 + * Refuse the put the cursor into that compromised position. 13763 + */ 13764 + if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && 13765 + state->visible && state->base.crtc_x < 0) { 13766 + DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); 13767 + return -EINVAL; 13768 + } 13769 + 13765 13770 return 0; 13766 13771 } 13767 13772 ··· 13801 13774 crtc = crtc ? crtc : plane->crtc; 13802 13775 intel_crtc = to_intel_crtc(crtc); 13803 13776 13804 - if (intel_crtc->cursor_bo == obj) 13805 - goto update; 13806 - 13807 13777 if (!obj) 13808 13778 addr = 0; 13809 13779 else if (!INTEL_INFO(dev)->cursor_needs_physical) ··· 13809 13785 addr = obj->phys_handle->busaddr; 13810 13786 13811 13787 intel_crtc->cursor_addr = addr; 13812 - intel_crtc->cursor_bo = obj; 13813 13788 13814 - update: 13815 13789 if (crtc->state->active) 13816 13790 intel_crtc_update_cursor(crtc, state->visible); 13817 13791 }

-1

drivers/gpu/drm/i915/intel_drv.h

··· 550 550 int adjusted_x; 551 551 int adjusted_y; 552 552 553 - struct drm_i915_gem_object *cursor_bo; 554 553 uint32_t cursor_addr; 555 554 uint32_t cursor_cntl; 556 555 uint32_t cursor_size;

+4 -3

drivers/gpu/drm/i915/intel_hdmi.c

··· 1374 1374 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1375 1375 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1376 1376 bool live_status = false; 1377 - unsigned int retry = 3; 1377 + unsigned int try; 1378 1378 1379 1379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1380 1380 connector->base.id, connector->name); 1381 1381 1382 1382 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1383 1383 1384 - while (!live_status && --retry) { 1384 + for (try = 0; !live_status && try < 4; try++) { 1385 + if (try) 1386 + msleep(10); 1385 1387 live_status = intel_digital_port_connected(dev_priv, 1386 1388 hdmi_to_dig_port(intel_hdmi)); 1387 - mdelay(10); 1388 1389 } 1389 1390 1390 1391 if (!live_status)

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