Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 5033/1: Unbreak corgi_ssp by registering ssp drivers earlier.
[ARM] Orion: clean up addr-map.c after window setting code purge
[ARM] Orion: pass proper t_clk into mv643xx_eth
[ARM] Orion: use mv643xx_eth driver mbus window handling
[ARM] pxa: Fix RCSR handling
[ARM] lubbock: fix compilation
[ARM] 5032/1: Added cpufreq support for pxa27x CPU
[ARM] 5031/1: Indentation correction in cpu-pxa.c.
[ARM] 5028/1: pxafb: fix broken "backward compatibility way" in framebuffer
[ARM] 4882/2: Correction for S3C2410 clkout generation
[ARM] 5027/1: Fixed random memory corruption on pxa suspend cycle.
[ARM] 5024/1: Fix some minor clk issues in the MMCI PL18x driver
[ARM] 5023/1: Fix broken gpio interrupts on ep93xx
ns9xxx: fix sparse warning
ns9xxx: check for irq lockups
ns9xxx: fix handle_prio_irq to unmask irqs with lower priority
+289
-226
+1
-1
arch/arm/mach-ep93xx/core.c
+1
-1
arch/arm/mach-ep93xx/core.c
+15
-7
arch/arm/mach-ns9xxx/irq.c
+15
-7
arch/arm/mach-ns9xxx/irq.c
···
62
62
#if 0
63
63
#define handle_irq handle_level_irq
64
64
#else
65
-
void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
65
+
static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
66
66
{
67
67
unsigned int cpu = smp_processor_id();
68
68
struct irqaction *action;
···
70
70
71
71
spin_lock(&desc->lock);
72
72
73
-
if (unlikely(desc->status & IRQ_INPROGRESS))
74
-
goto out_unlock;
73
+
BUG_ON(desc->status & IRQ_INPROGRESS);
75
74
76
75
desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
77
76
kstat_cpu(cpu).irqs[irq]++;
78
77
79
78
action = desc->action;
80
79
if (unlikely(!action || (desc->status & IRQ_DISABLED)))
81
-
goto out_unlock;
80
+
goto out_mask;
82
81
83
82
desc->status |= IRQ_INPROGRESS;
84
83
spin_unlock(&desc->lock);
85
84
86
85
action_ret = handle_IRQ_event(irq, action);
87
86
87
+
/* XXX: There is no direct way to access noirqdebug, so check
88
+
* unconditionally for spurious irqs...
89
+
* Maybe this function should go to kernel/irq/chip.c? */
90
+
note_interrupt(irq, desc, action_ret);
91
+
88
92
spin_lock(&desc->lock);
89
93
desc->status &= ~IRQ_INPROGRESS;
90
-
if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
91
-
desc->chip->ack(irq);
92
94
93
-
out_unlock:
95
+
if (desc->status & IRQ_DISABLED)
96
+
out_mask:
97
+
desc->chip->mask(irq);
98
+
99
+
/* ack unconditionally to unmask lower prio irqs */
100
+
desc->chip->ack(irq);
101
+
94
102
spin_unlock(&desc->lock);
95
103
}
96
104
#define handle_irq handle_prio_irq
+3
-63
arch/arm/mach-orion5x/addr-map.c
+3
-63
arch/arm/mach-orion5x/addr-map.c
···
34
34
* Non-CPU Masters address decoding --
35
35
* Unlike the CPU, we setup the access from Orion's master interfaces to DDR
36
36
* banks only (the typical use case).
37
-
* Setup access for each master to DDR is issued by common.c.
38
-
*
39
-
* Note: although orion_setbits() and orion_clrbits() are not atomic
40
-
* no locking is necessary here since code in this file is only called
41
-
* at boot time when there is no concurrency issues.
37
+
* Setup access for each master to DDR is issued by platform device setup.
42
38
*/
43
39
44
40
/*
···
44
48
#define TARGET_DEV_BUS 1
45
49
#define TARGET_PCI 3
46
50
#define TARGET_PCIE 4
47
-
#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
48
-
((n) == 1) ? 0xd : \
49
-
((n) == 2) ? 0xb : \
50
-
((n) == 3) ? 0x7 : 0xf)
51
51
#define ATTR_PCIE_MEM 0x59
52
52
#define ATTR_PCIE_IO 0x51
53
53
#define ATTR_PCIE_WA 0x79
···
53
61
#define ATTR_DEV_CS1 0x1d
54
62
#define ATTR_DEV_CS2 0x1b
55
63
#define ATTR_DEV_BOOT 0xf
56
-
#define WIN_EN 1
57
64
58
65
/*
59
66
* Helpers to get DDR bank info
60
67
*/
61
-
#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8))
62
-
#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8))
63
-
#define DDR_MAX_CS 4
64
-
#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
65
-
#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
66
-
#define DDR_BANK_EN 1
68
+
#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
69
+
#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
67
70
68
71
/*
69
72
* CPU Address Decode Windows registers
···
67
80
#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
68
81
#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
69
82
#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
70
-
71
-
/*
72
-
* Gigabit Ethernet Address Decode Windows registers
73
-
*/
74
-
#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
75
-
#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
76
-
#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
77
-
#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
78
-
#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
79
-
#define ETH_MAX_WIN 6
80
-
#define ETH_MAX_REMAP_WIN 4
81
83
82
84
83
85
struct mbus_dram_target_info orion5x_mbus_dram_info;
···
177
201
void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
178
202
{
179
203
setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
180
-
}
181
-
182
-
void __init orion5x_setup_eth_wins(void)
183
-
{
184
-
int i;
185
-
186
-
/*
187
-
* First, disable and clear windows
188
-
*/
189
-
for (i = 0; i < ETH_MAX_WIN; i++) {
190
-
orion5x_write(ETH_WIN_BASE(i), 0);
191
-
orion5x_write(ETH_WIN_SIZE(i), 0);
192
-
orion5x_setbits(ETH_WIN_EN, 1 << i);
193
-
orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
194
-
if (i < ETH_MAX_REMAP_WIN)
195
-
orion5x_write(ETH_WIN_REMAP(i), 0);
196
-
}
197
-
198
-
/*
199
-
* Setup windows for DDR banks.
200
-
*/
201
-
for (i = 0; i < DDR_MAX_CS; i++) {
202
-
u32 base, size;
203
-
size = orion5x_read(DDR_SIZE_CS(i));
204
-
base = orion5x_read(DDR_BASE_CS(i));
205
-
if (size & DDR_BANK_EN) {
206
-
base = DDR_REG_TO_BASE(base);
207
-
size = DDR_REG_TO_SIZE(size);
208
-
orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
209
-
orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
210
-
(ATTR_DDR_CS(i) << 8) |
211
-
TARGET_DDR);
212
-
orion5x_clrbits(ETH_WIN_EN, 1 << i);
213
-
orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
214
-
}
215
-
}
216
204
}
+8
-1
arch/arm/mach-orion5x/common.c
+8
-1
arch/arm/mach-orion5x/common.c
···
190
190
* (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
191
191
****************************************************************************/
192
192
193
+
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
194
+
.dram = &orion5x_mbus_dram_info,
195
+
.t_clk = ORION5X_TCLK,
196
+
};
197
+
193
198
static struct resource orion5x_eth_shared_resources[] = {
194
199
{
195
200
.start = ORION5X_ETH_PHYS_BASE + 0x2000,
···
206
201
static struct platform_device orion5x_eth_shared = {
207
202
.name = MV643XX_ETH_SHARED_NAME,
208
203
.id = 0,
204
+
.dev = {
205
+
.platform_data = &orion5x_eth_shared_data,
206
+
},
209
207
.num_resources = 1,
210
208
.resource = orion5x_eth_shared_resources,
211
209
};
···
370
362
* Setup Orion address map
371
363
*/
372
364
orion5x_setup_cpu_mbus_bridge();
373
-
orion5x_setup_eth_wins();
374
365
375
366
/*
376
367
* Register devices.
-1
arch/arm/mach-orion5x/common.h
-1
arch/arm/mach-orion5x/common.h
+7
-5
arch/arm/mach-pxa/Makefile
+7
-5
arch/arm/mach-pxa/Makefile
···
5
5
# Common support (must be linked before board specific support)
6
6
obj-y += clock.o devices.o generic.o irq.o dma.o \
7
7
time.o gpio.o
8
+
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9
+
obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
10
+
11
+
# Generic drivers that other drivers may depend upon
12
+
obj-$(CONFIG_PXA_SSP) += ssp.o
13
+
14
+
# SoC-specific code
8
15
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o
9
16
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa27x.o
10
17
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o
···
54
47
led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
55
48
56
49
obj-$(CONFIG_LEDS) += $(led-y)
57
-
58
-
# Misc features
59
-
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
60
-
obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
61
-
obj-$(CONFIG_PXA_SSP) += ssp.o
62
50
63
51
ifeq ($(CONFIG_PCI),y)
64
52
obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
-4
arch/arm/mach-pxa/corgi.c
-4
arch/arm/mach-pxa/corgi.c
···
493
493
494
494
static void corgi_poweroff(void)
495
495
{
496
-
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
497
-
498
496
if (!machine_is_corgi())
499
497
/* Green LED off tells the bootloader to halt */
500
498
reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
···
501
503
502
504
static void corgi_restart(char mode)
503
505
{
504
-
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
505
-
506
506
if (!machine_is_corgi())
507
507
/* Green LED on tells the bootloader to reboot */
508
508
set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
+210
-100
arch/arm/mach-pxa/cpu-pxa.c
+210
-100
arch/arm/mach-pxa/cpu-pxa.c
···
49
49
#define freq_debug 0
50
50
#endif
51
51
52
+
static unsigned int pxa27x_maxfreq;
53
+
module_param(pxa27x_maxfreq, uint, 0);
54
+
MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
55
+
"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
56
+
52
57
typedef struct {
53
58
unsigned int khz;
54
59
unsigned int membus;
55
60
unsigned int cccr;
56
61
unsigned int div2;
62
+
unsigned int cclkcfg;
57
63
} pxa_freqs_t;
58
64
59
65
/* Define the refresh period in mSec for the SDRAM and the number of rows */
60
-
#define SDRAM_TREF 64 /* standard 64ms SDRAM */
61
-
#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
62
-
#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
66
+
#define SDRAM_TREF 64 /* standard 64ms SDRAM */
67
+
#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
63
68
64
-
#define CCLKCFG_TURBO 0x1
65
-
#define CCLKCFG_FCS 0x2
66
-
#define PXA25x_MIN_FREQ 99500
67
-
#define PXA25x_MAX_FREQ 398100
68
-
#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
69
-
#define MDREFR_DRI_MASK 0xFFF
69
+
#define CCLKCFG_TURBO 0x1
70
+
#define CCLKCFG_FCS 0x2
71
+
#define CCLKCFG_HALFTURBO 0x4
72
+
#define CCLKCFG_FASTBUS 0x8
73
+
#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
74
+
#define MDREFR_DRI_MASK 0xFFF
70
75
71
-
76
+
/*
77
+
* PXA255 definitions
78
+
*/
72
79
/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
80
+
#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
81
+
73
82
static pxa_freqs_t pxa255_run_freqs[] =
74
83
{
75
-
/* CPU MEMBUS CCCR DIV2*/
76
-
{ 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
77
-
{132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
78
-
{199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
79
-
{265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
80
-
{331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
81
-
{398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
82
-
{0,}
84
+
/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
85
+
{ 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
86
+
{132700, 132700, 0x123, 1, CCLKCFG}, /* 133, 133, 66, 66 */
87
+
{199100, 99500, 0x141, 0, CCLKCFG}, /* 199, 199, 99, 99 */
88
+
{265400, 132700, 0x143, 1, CCLKCFG}, /* 265, 265, 133, 66 */
89
+
{331800, 165900, 0x145, 1, CCLKCFG}, /* 331, 331, 166, 83 */
90
+
{398100, 99500, 0x161, 0, CCLKCFG}, /* 398, 398, 196, 99 */
83
91
};
84
-
#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
85
-
86
-
static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
87
92
88
93
/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
89
94
static pxa_freqs_t pxa255_turbo_freqs[] =
90
95
{
91
-
/* CPU MEMBUS CCCR DIV2*/
92
-
{ 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
93
-
{199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
94
-
{298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
95
-
{298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
96
-
{398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
97
-
{0,}
96
+
/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
97
+
{ 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
98
+
{199100, 99500, 0x221, 0, CCLKCFG}, /* 99, 199, 50, 99 */
99
+
{298500, 99500, 0x321, 0, CCLKCFG}, /* 99, 287, 50, 99 */
100
+
{298600, 99500, 0x1c1, 0, CCLKCFG}, /* 199, 287, 99, 99 */
101
+
{398100, 99500, 0x241, 0, CCLKCFG}, /* 199, 398, 99, 99 */
98
102
};
99
-
#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
100
103
101
-
static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
104
+
#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
105
+
#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
106
+
107
+
static struct cpufreq_frequency_table
108
+
pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
109
+
static struct cpufreq_frequency_table
110
+
pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
111
+
112
+
/*
113
+
* PXA270 definitions
114
+
*
115
+
* For the PXA27x:
116
+
* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
117
+
*
118
+
* A = 0 => memory controller clock from table 3-7,
119
+
* A = 1 => memory controller clock = system bus clock
120
+
* Run mode frequency = 13 MHz * L
121
+
* Turbo mode frequency = 13 MHz * L * N
122
+
* System bus frequency = 13 MHz * L / (B + 1)
123
+
*
124
+
* In CCCR:
125
+
* A = 1
126
+
* L = 16 oscillator to run mode ratio
127
+
* 2N = 6 2 * (turbo mode to run mode ratio)
128
+
*
129
+
* In CCLKCFG:
130
+
* B = 1 Fast bus mode
131
+
* HT = 0 Half-Turbo mode
132
+
* T = 1 Turbo mode
133
+
*
134
+
* For now, just support some of the combinations in table 3-7 of
135
+
* PXA27x Processor Family Developer's Manual to simplify frequency
136
+
* change sequences.
137
+
*/
138
+
#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
139
+
#define CCLKCFG2(B, HT, T) \
140
+
(CCLKCFG_FCS | \
141
+
((B) ? CCLKCFG_FASTBUS : 0) | \
142
+
((HT) ? CCLKCFG_HALFTURBO : 0) | \
143
+
((T) ? CCLKCFG_TURBO : 0))
144
+
145
+
static pxa_freqs_t pxa27x_freqs[] = {
146
+
{104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1)},
147
+
{156000, 104000, PXA27x_CCCR(1, 8, 6), 0, CCLKCFG2(1, 1, 1)},
148
+
{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
149
+
{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
150
+
{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
151
+
{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
152
+
{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
153
+
};
154
+
155
+
#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
156
+
static struct cpufreq_frequency_table
157
+
pxa27x_freq_table[NUM_PXA27x_FREQS+1];
102
158
103
159
extern unsigned get_clk_frequency_khz(int info);
160
+
161
+
static void find_freq_tables(struct cpufreq_policy *policy,
162
+
struct cpufreq_frequency_table **freq_table,
163
+
pxa_freqs_t **pxa_freqs)
164
+
{
165
+
if (cpu_is_pxa25x()) {
166
+
if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
167
+
*pxa_freqs = pxa255_run_freqs;
168
+
*freq_table = pxa255_run_freq_table;
169
+
} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
170
+
*pxa_freqs = pxa255_turbo_freqs;
171
+
*freq_table = pxa255_turbo_freq_table;
172
+
} else {
173
+
printk("CPU PXA: Unknown policy found. "
174
+
"Using CPUFREQ_POLICY_PERFORMANCE\n");
175
+
*pxa_freqs = pxa255_run_freqs;
176
+
*freq_table = pxa255_run_freq_table;
177
+
}
178
+
}
179
+
if (cpu_is_pxa27x()) {
180
+
*pxa_freqs = pxa27x_freqs;
181
+
*freq_table = pxa27x_freq_table;
182
+
}
183
+
}
184
+
185
+
static void pxa27x_guess_max_freq(void)
186
+
{
187
+
if (!pxa27x_maxfreq) {
188
+
pxa27x_maxfreq = 416000;
189
+
printk(KERN_INFO "PXA CPU 27x max frequency not defined "
190
+
"(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
191
+
pxa27x_maxfreq);
192
+
} else {
193
+
pxa27x_maxfreq *= 1000;
194
+
}
195
+
}
196
+
197
+
static u32 mdrefr_dri(unsigned int freq)
198
+
{
199
+
u32 dri = 0;
200
+
201
+
if (cpu_is_pxa25x())
202
+
dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
203
+
if (cpu_is_pxa27x())
204
+
dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
205
+
return dri;
206
+
}
104
207
105
208
/* find a valid frequency point */
106
209
static int pxa_verify_policy(struct cpufreq_policy *policy)
107
210
{
108
211
struct cpufreq_frequency_table *pxa_freqs_table;
212
+
pxa_freqs_t *pxa_freqs;
109
213
int ret;
110
214
111
-
if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
112
-
pxa_freqs_table = pxa255_run_freq_table;
113
-
} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
114
-
pxa_freqs_table = pxa255_turbo_freq_table;
115
-
} else {
116
-
printk("CPU PXA: Unknown policy found. "
117
-
"Using CPUFREQ_POLICY_PERFORMANCE\n");
118
-
pxa_freqs_table = pxa255_run_freq_table;
119
-
}
120
-
215
+
find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs);
121
216
ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
122
217
123
218
if (freq_debug)
124
219
pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
125
-
policy->min, policy->max);
220
+
policy->min, policy->max);
126
221
127
222
return ret;
128
223
}
129
224
225
+
static unsigned int pxa_cpufreq_get(unsigned int cpu)
226
+
{
227
+
return get_clk_frequency_khz(0);
228
+
}
229
+
130
230
static int pxa_set_target(struct cpufreq_policy *policy,
131
-
unsigned int target_freq,
132
-
unsigned int relation)
231
+
unsigned int target_freq,
232
+
unsigned int relation)
133
233
{
134
234
struct cpufreq_frequency_table *pxa_freqs_table;
135
235
pxa_freqs_t *pxa_freq_settings;
136
236
struct cpufreq_freqs freqs;
137
237
unsigned int idx;
138
238
unsigned long flags;
139
-
unsigned int unused, preset_mdrefr, postset_mdrefr;
140
-
void *ramstart = phys_to_virt(0xa0000000);
239
+
unsigned int new_freq_cpu, new_freq_mem;
240
+
unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
141
241
142
242
/* Get the current policy */
143
-
if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
144
-
pxa_freq_settings = pxa255_run_freqs;
145
-
pxa_freqs_table = pxa255_run_freq_table;
146
-
} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
147
-
pxa_freq_settings = pxa255_turbo_freqs;
148
-
pxa_freqs_table = pxa255_turbo_freq_table;
149
-
} else {
150
-
printk("CPU PXA: Unknown policy found. "
151
-
"Using CPUFREQ_POLICY_PERFORMANCE\n");
152
-
pxa_freq_settings = pxa255_run_freqs;
153
-
pxa_freqs_table = pxa255_run_freq_table;
154
-
}
243
+
find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings);
155
244
156
245
/* Lookup the next frequency */
157
246
if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
158
-
target_freq, relation, &idx)) {
247
+
target_freq, relation, &idx)) {
159
248
return -EINVAL;
160
249
}
161
250
251
+
new_freq_cpu = pxa_freq_settings[idx].khz;
252
+
new_freq_mem = pxa_freq_settings[idx].membus;
162
253
freqs.old = policy->cur;
163
-
freqs.new = pxa_freq_settings[idx].khz;
254
+
freqs.new = new_freq_cpu;
164
255
freqs.cpu = policy->cpu;
165
256
166
257
if (freq_debug)
167
-
pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
168
-
freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
169
-
(pxa_freq_settings[idx].membus / 2000) :
170
-
(pxa_freq_settings[idx].membus / 1000));
258
+
pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
259
+
"(SDRAM %d Mhz)\n",
260
+
freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
261
+
(new_freq_mem / 2000) : (new_freq_mem / 1000));
171
262
172
263
/*
173
264
* Tell everyone what we're about to do...
···
268
177
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
269
178
270
179
/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
271
-
* we need to preset the smaller DRI before the change. If we're speeding
272
-
* up we need to set the larger DRI value after the change.
180
+
* we need to preset the smaller DRI before the change. If we're
181
+
* speeding up we need to set the larger DRI value after the change.
273
182
*/
274
183
preset_mdrefr = postset_mdrefr = MDREFR;
275
-
if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
276
-
preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
277
-
MDREFR_DRI(pxa_freq_settings[idx].membus);
184
+
if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
185
+
preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
186
+
preset_mdrefr |= mdrefr_dri(new_freq_mem);
278
187
}
279
-
postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
280
-
MDREFR_DRI(pxa_freq_settings[idx].membus);
188
+
postset_mdrefr =
189
+
(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
281
190
282
191
/* If we're dividing the memory clock by two for the SDRAM clock, this
283
192
* must be set prior to the change. Clearing the divide must be done
···
292
201
293
202
local_irq_save(flags);
294
203
295
-
/* Set new the CCCR */
204
+
/* Set new the CCCR and prepare CCLKCFG */
296
205
CCCR = pxa_freq_settings[idx].cccr;
206
+
cclkcfg = pxa_freq_settings[idx].cclkcfg;
297
207
298
208
asm volatile(" \n\
299
209
ldr r4, [%1] /* load MDREFR */ \n\
300
210
b 2f \n\
301
-
.align 5 \n\
211
+
.align 5 \n\
302
212
1: \n\
303
-
str %4, [%1] /* preset the MDREFR */ \n\
213
+
str %3, [%1] /* preset the MDREFR */ \n\
304
214
mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
305
-
str %5, [%1] /* postset the MDREFR */ \n\
215
+
str %4, [%1] /* postset the MDREFR */ \n\
306
216
\n\
307
217
b 3f \n\
308
218
2: b 1b \n\
309
219
3: nop \n\
310
220
"
311
-
: "=&r" (unused)
312
-
: "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
313
-
"r" (preset_mdrefr), "r" (postset_mdrefr)
314
-
: "r4", "r5");
221
+
: "=&r" (unused)
222
+
: "r" (&MDREFR), "r" (cclkcfg),
223
+
"r" (preset_mdrefr), "r" (postset_mdrefr)
224
+
: "r4", "r5");
315
225
local_irq_restore(flags);
316
226
317
227
/*
···
325
233
return 0;
326
234
}
327
235
328
-
static unsigned int pxa_cpufreq_get(unsigned int cpu)
329
-
{
330
-
return get_clk_frequency_khz(0);
331
-
}
332
-
333
-
static int pxa_cpufreq_init(struct cpufreq_policy *policy)
236
+
static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
334
237
{
335
238
int i;
239
+
unsigned int freq;
240
+
241
+
/* try to guess pxa27x cpu */
242
+
if (cpu_is_pxa27x())
243
+
pxa27x_guess_max_freq();
336
244
337
245
/* set default policy and cpuinfo */
338
246
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
339
-
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
340
-
policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
341
-
policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
247
+
if (cpu_is_pxa25x())
248
+
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
342
249
policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
343
-
policy->cur = get_clk_frequency_khz(0); /* current freq */
250
+
policy->cur = get_clk_frequency_khz(0); /* current freq */
344
251
policy->min = policy->max = policy->cur;
345
252
346
-
/* Generate the run cpufreq_frequency_table struct */
347
-
for (i = 0; i < NUM_RUN_FREQS; i++) {
253
+
/* Generate pxa25x the run cpufreq_frequency_table struct */
254
+
for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
348
255
pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
349
256
pxa255_run_freq_table[i].index = i;
350
257
}
351
-
352
258
pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
353
-
/* Generate the turbo cpufreq_frequency_table struct */
354
-
for (i = 0; i < NUM_TURBO_FREQS; i++) {
355
-
pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
259
+
260
+
/* Generate pxa25x the turbo cpufreq_frequency_table struct */
261
+
for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
262
+
pxa255_turbo_freq_table[i].frequency =
263
+
pxa255_turbo_freqs[i].khz;
356
264
pxa255_turbo_freq_table[i].index = i;
357
265
}
358
266
pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
267
+
268
+
/* Generate the pxa27x cpufreq_frequency_table struct */
269
+
for (i = 0; i < NUM_PXA27x_FREQS; i++) {
270
+
freq = pxa27x_freqs[i].khz;
271
+
if (freq > pxa27x_maxfreq)
272
+
break;
273
+
pxa27x_freq_table[i].frequency = freq;
274
+
pxa27x_freq_table[i].index = i;
275
+
}
276
+
pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
277
+
278
+
/*
279
+
* Set the policy's minimum and maximum frequencies from the tables
280
+
* just constructed. This sets cpuinfo.mxx_freq, min and max.
281
+
*/
282
+
if (cpu_is_pxa25x())
283
+
cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table);
284
+
else if (cpu_is_pxa27x())
285
+
cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
359
286
360
287
printk(KERN_INFO "PXA CPU frequency change support initialized\n");
361
288
···
386
275
.target = pxa_set_target,
387
276
.init = pxa_cpufreq_init,
388
277
.get = pxa_cpufreq_get,
389
-
.name = "PXA25x",
278
+
.name = "PXA2xx",
390
279
};
391
280
392
281
static int __init pxa_cpu_init(void)
393
282
{
394
283
int ret = -ENODEV;
395
-
if (cpu_is_pxa25x())
284
+
if (cpu_is_pxa25x() || cpu_is_pxa27x())
396
285
ret = cpufreq_register_driver(&pxa_cpufreq_driver);
397
286
return ret;
398
287
}
399
288
400
289
static void __exit pxa_cpu_exit(void)
401
290
{
402
-
if (cpu_is_pxa25x())
403
-
cpufreq_unregister_driver(&pxa_cpufreq_driver);
291
+
cpufreq_unregister_driver(&pxa_cpufreq_driver);
404
292
}
405
293
406
294
407
-
MODULE_AUTHOR ("Intrinsyc Software Inc.");
408
-
MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
295
+
MODULE_AUTHOR("Intrinsyc Software Inc.");
296
+
MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
409
297
MODULE_LICENSE("GPL");
410
298
module_init(pxa_cpu_init);
411
299
module_exit(pxa_cpu_exit);
+1
-1
arch/arm/mach-pxa/lubbock.c
+1
-1
arch/arm/mach-pxa/lubbock.c
+4
-6
arch/arm/mach-pxa/pm.c
+4
-6
arch/arm/mach-pxa/pm.c
···
42
42
if (state != PM_SUSPEND_STANDBY) {
43
43
pxa_cpu_pm_fns->save(sleep_save);
44
44
/* before sleeping, calculate and save a checksum */
45
-
for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
45
+
for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
46
46
sleep_save_checksum += sleep_save[i];
47
47
}
48
-
49
-
/* Clear reset status */
50
-
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
51
48
52
49
/* *** go zzz *** */
53
50
pxa_cpu_pm_fns->enter(state);
···
52
55
53
56
if (state != PM_SUSPEND_STANDBY) {
54
57
/* after sleeping, validate the checksum */
55
-
for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
58
+
for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
56
59
checksum += sleep_save[i];
57
60
58
61
/* if invalid, display message and wait for a hardware reset */
···
98
101
return -EINVAL;
99
102
}
100
103
101
-
sleep_save = kmalloc(pxa_cpu_pm_fns->save_size, GFP_KERNEL);
104
+
sleep_save = kmalloc(pxa_cpu_pm_fns->save_count * sizeof(unsigned long),
105
+
GFP_KERNEL);
102
106
if (!sleep_save) {
103
107
printk(KERN_ERR "failed to alloc memory for pm save\n");
104
108
return -ENOMEM;
-2
arch/arm/mach-pxa/poodle.c
-2
arch/arm/mach-pxa/poodle.c
···
326
326
327
327
static void poodle_poweroff(void)
328
328
{
329
-
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
330
329
arm_machine_restart('h');
331
330
}
332
331
333
332
static void poodle_restart(char mode)
334
333
{
335
-
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
336
334
arm_machine_restart('h');
337
335
}
338
336
+6
-5
arch/arm/mach-pxa/pxa25x.c
+6
-5
arch/arm/mach-pxa/pxa25x.c
···
150
150
* More ones like CP and general purpose register values are preserved
151
151
* with the stack pointer in sleep.S.
152
152
*/
153
-
enum { SLEEP_SAVE_START = 0,
154
-
155
-
SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
153
+
enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
156
154
157
155
SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
158
156
SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
···
160
162
161
163
SLEEP_SAVE_CKEN,
162
164
163
-
SLEEP_SAVE_SIZE
165
+
SLEEP_SAVE_COUNT
164
166
};
165
167
166
168
···
198
200
199
201
static void pxa25x_cpu_pm_enter(suspend_state_t state)
200
202
{
203
+
/* Clear reset status */
204
+
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
205
+
201
206
switch (state) {
202
207
case PM_SUSPEND_MEM:
203
208
/* set resume return address */
···
211
210
}
212
211
213
212
static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
214
-
.save_size = SLEEP_SAVE_SIZE,
213
+
.save_count = SLEEP_SAVE_COUNT,
215
214
.valid = suspend_valid_only_mem,
216
215
.save = pxa25x_cpu_pm_save,
217
216
.restore = pxa25x_cpu_pm_restore,
+6
-5
arch/arm/mach-pxa/pxa27x.c
+6
-5
arch/arm/mach-pxa/pxa27x.c
···
181
181
* More ones like CP and general purpose register values are preserved
182
182
* with the stack pointer in sleep.S.
183
183
*/
184
-
enum { SLEEP_SAVE_START = 0,
185
-
186
-
SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
184
+
enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
187
185
188
186
SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
189
187
SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
···
196
198
SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
197
199
SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
198
200
199
-
SLEEP_SAVE_SIZE
201
+
SLEEP_SAVE_COUNT
200
202
};
201
203
202
204
void pxa27x_cpu_pm_save(unsigned long *sleep_save)
···
249
251
/* Clear edge-detect status register. */
250
252
PEDR = 0xDF12FE1B;
251
253
254
+
/* Clear reset status */
255
+
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
256
+
252
257
switch (state) {
253
258
case PM_SUSPEND_STANDBY:
254
259
pxa_cpu_standby();
···
270
269
}
271
270
272
271
static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
273
-
.save_size = SLEEP_SAVE_SIZE,
272
+
.save_count = SLEEP_SAVE_COUNT,
274
273
.save = pxa27x_cpu_pm_save,
275
274
.restore = pxa27x_cpu_pm_restore,
276
275
.valid = pxa27x_cpu_pm_valid,
+3
-4
arch/arm/mach-pxa/pxa3xx.c
+3
-4
arch/arm/mach-pxa/pxa3xx.c
···
256
256
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
257
257
#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
258
258
259
-
enum { SLEEP_SAVE_START = 0,
260
-
SLEEP_SAVE_CKENA,
259
+
enum { SLEEP_SAVE_CKENA,
261
260
SLEEP_SAVE_CKENB,
262
261
SLEEP_SAVE_ACCR,
263
262
264
-
SLEEP_SAVE_SIZE,
263
+
SLEEP_SAVE_COUNT,
265
264
};
266
265
267
266
static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
···
375
376
}
376
377
377
378
static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
378
-
.save_size = SLEEP_SAVE_SIZE,
379
+
.save_count = SLEEP_SAVE_COUNT,
379
380
.save = pxa3xx_cpu_pm_save,
380
381
.restore = pxa3xx_cpu_pm_restore,
381
382
.valid = pxa3xx_cpu_pm_valid,
-2
arch/arm/mach-pxa/spitz.c
-2
arch/arm/mach-pxa/spitz.c
-3
arch/arm/mach-pxa/spitz_pm.c
-3
arch/arm/mach-pxa/spitz_pm.c
-2
arch/arm/mach-pxa/tosa.c
-2
arch/arm/mach-pxa/tosa.c
+3
-5
arch/arm/mach-sa1100/pm.c
+3
-5
arch/arm/mach-sa1100/pm.c
···
43
43
* More ones like CP and general purpose register values are preserved
44
44
* on the stack and then the stack pointer is stored last in sleep.S.
45
45
*/
46
-
enum { SLEEP_SAVE_SP = 0,
47
-
48
-
SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
46
+
enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
49
47
SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
50
48
51
49
SLEEP_SAVE_Ser1SDCR0,
52
50
53
-
SLEEP_SAVE_SIZE
51
+
SLEEP_SAVE_COUNT
54
52
};
55
53
56
54
57
55
static int sa11x0_pm_enter(suspend_state_t state)
58
56
{
59
-
unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE];
57
+
unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
60
58
61
59
gpio = GPLR;
62
60
+2
-2
arch/arm/plat-s3c24xx/clock.c
+2
-2
arch/arm/plat-s3c24xx/clock.c
···
411
411
412
412
clk->parent = parent;
413
413
414
-
if (clk == &s3c24xx_dclk0)
414
+
if (clk == &s3c24xx_clkout0)
415
415
mask = S3C2410_MISCCR_CLK0_MASK;
416
416
else {
417
417
source <<= 4;
···
437
437
struct clk s3c24xx_dclk1 = {
438
438
.name = "dclk1",
439
439
.id = -1,
440
-
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
440
+
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
441
441
.enable = s3c24xx_dclk_enable,
442
442
.set_parent = s3c24xx_dclk_setparent,
443
443
.set_rate = s3c24xx_set_dclk_rate,
+13
-1
drivers/mmc/host/mmci.c
+13
-1
drivers/mmc/host/mmci.c
···
425
425
host->cclk = host->mclk;
426
426
} else {
427
427
clk = host->mclk / (2 * ios->clock) - 1;
428
-
if (clk > 256)
428
+
if (clk >= 256)
429
429
clk = 255;
430
430
host->cclk = host->mclk / (2 * (clk + 1));
431
431
}
···
512
512
513
513
host->plat = plat;
514
514
host->mclk = clk_get_rate(host->clk);
515
+
/*
516
+
* According to the spec, mclk is max 100 MHz,
517
+
* so we try to adjust the clock down to this,
518
+
* (if possible).
519
+
*/
520
+
if (host->mclk > 100000000) {
521
+
ret = clk_set_rate(host->clk, 100000000);
522
+
if (ret < 0)
523
+
goto clk_disable;
524
+
host->mclk = clk_get_rate(host->clk);
525
+
DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
526
+
}
515
527
host->mmc = mmc;
516
528
host->base = ioremap(dev->res.start, SZ_4K);
517
529
if (!host->base) {
+4
-4
drivers/video/pxafb.c
+4
-4
drivers/video/pxafb.c
···
1301
1301
}
1302
1302
}
1303
1303
1304
-
static int pxafb_decode_mach_info(struct pxafb_info *fbi,
1305
-
struct pxafb_mach_info *inf)
1304
+
static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1305
+
struct pxafb_mach_info *inf)
1306
1306
{
1307
1307
unsigned int lcd_conn = inf->lcd_conn;
1308
1308
···
1333
1333
fbi->lccr0 = inf->lccr0;
1334
1334
fbi->lccr3 = inf->lccr3;
1335
1335
fbi->lccr4 = inf->lccr4;
1336
-
return -EINVAL;
1336
+
goto decode_mode;
1337
1337
}
1338
1338
1339
1339
if (lcd_conn == LCD_MONO_STN_8BPP)
···
1343
1343
fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1344
1344
fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1345
1345
1346
+
decode_mode:
1346
1347
pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1347
-
return 0;
1348
1348
}
1349
1349
1350
1350
static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
+1
-1
include/asm-arm/arch-pxa/pm.h
+1
-1
include/asm-arm/arch-pxa/pm.h
+2
-1
include/asm-arm/arch-pxa/system.h
+2
-1
include/asm-arm/arch-pxa/system.h