Merge tag 'hyperv-fixes-signed-20221110' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux

-1

MAINTAINERS

··· 9507 9507 Hyper-V/Azure CORE AND DRIVERS 9508 9508 M: "K. Y. Srinivasan" <kys@microsoft.com> 9509 9509 M: Haiyang Zhang <haiyangz@microsoft.com> 9510 - M: Stephen Hemminger <sthemmin@microsoft.com> 9511 9510 M: Wei Liu <wei.liu@kernel.org> 9512 9511 M: Dexuan Cui <decui@microsoft.com> 9513 9512 L: linux-hyperv@vger.kernel.org

+10 -9

arch/x86/hyperv/hv_init.c

··· 444 444 445 445 if (hv_root_partition) { 446 446 struct page *pg; 447 - void *src, *dst; 447 + void *src; 448 448 449 449 /* 450 450 * For the root partition, the hypervisor will set up its ··· 459 459 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 460 460 461 461 pg = vmalloc_to_page(hv_hypercall_pg); 462 - dst = kmap_local_page(pg); 463 462 src = memremap(hypercall_msr.guest_physical_address << PAGE_SHIFT, PAGE_SIZE, 464 463 MEMREMAP_WB); 465 - BUG_ON(!(src && dst)); 466 - memcpy(dst, src, HV_HYP_PAGE_SIZE); 464 + BUG_ON(!src); 465 + memcpy_to_page(pg, 0, src, HV_HYP_PAGE_SIZE); 467 466 memunmap(src); 468 - kunmap_local(dst); 469 467 } else { 470 468 hypercall_msr.guest_physical_address = vmalloc_to_pfn(hv_hypercall_pg); 471 469 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); ··· 535 537 void hyperv_cleanup(void) 536 538 { 537 539 union hv_x64_msr_hypercall_contents hypercall_msr; 540 + union hv_reference_tsc_msr tsc_msr; 538 541 539 542 unregister_syscore_ops(&hv_syscore_ops); 540 543 ··· 551 552 hv_hypercall_pg = NULL; 552 553 553 554 /* Reset the hypercall page */ 554 - hypercall_msr.as_uint64 = 0; 555 - wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 555 + hypercall_msr.as_uint64 = hv_get_register(HV_X64_MSR_HYPERCALL); 556 + hypercall_msr.enable = 0; 557 + hv_set_register(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 556 558 557 559 /* Reset the TSC page */ 558 - hypercall_msr.as_uint64 = 0; 559 - wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64); 560 + tsc_msr.as_uint64 = hv_get_register(HV_X64_MSR_REFERENCE_TSC); 561 + tsc_msr.enable = 0; 562 + hv_set_register(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64); 560 563 } 561 564 562 565 void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)

+15 -14

drivers/clocksource/hyperv_timer.c

··· 21 21 #include <linux/interrupt.h> 22 22 #include <linux/irq.h> 23 23 #include <linux/acpi.h> 24 + #include <linux/hyperv.h> 24 25 #include <clocksource/hyperv_timer.h> 25 26 #include <asm/hyperv-tlfs.h> 26 27 #include <asm/mshyperv.h> ··· 396 395 397 396 static void suspend_hv_clock_tsc(struct clocksource *arg) 398 397 { 399 - u64 tsc_msr; 398 + union hv_reference_tsc_msr tsc_msr; 400 399 401 400 /* Disable the TSC page */ 402 - tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC); 403 - tsc_msr &= ~BIT_ULL(0); 404 - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr); 401 + tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC); 402 + tsc_msr.enable = 0; 403 + hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); 405 404 } 406 405 407 406 408 407 static void resume_hv_clock_tsc(struct clocksource *arg) 409 408 { 410 409 phys_addr_t phys_addr = virt_to_phys(&tsc_pg); 411 - u64 tsc_msr; 410 + union hv_reference_tsc_msr tsc_msr; 412 411 413 412 /* Re-enable the TSC page */ 414 - tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC); 415 - tsc_msr &= GENMASK_ULL(11, 0); 416 - tsc_msr |= BIT_ULL(0) | (u64)phys_addr; 417 - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr); 413 + tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC); 414 + tsc_msr.enable = 1; 415 + tsc_msr.pfn = HVPFN_DOWN(phys_addr); 416 + hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); 418 417 } 419 418 420 419 #ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK ··· 496 495 497 496 static bool __init hv_init_tsc_clocksource(void) 498 497 { 499 - u64 tsc_msr; 498 + union hv_reference_tsc_msr tsc_msr; 500 499 phys_addr_t phys_addr; 501 500 502 501 if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE)) ··· 531 530 * (which already has at least the low 12 bits set to zero since 532 531 * it is page aligned). Also set the "enable" bit, which is bit 0. 533 532 */ 534 - tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC); 535 - tsc_msr &= GENMASK_ULL(11, 0); 536 - tsc_msr = tsc_msr | 0x1 | (u64)phys_addr; 537 - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr); 533 + tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC); 534 + tsc_msr.enable = 1; 535 + tsc_msr.pfn = HVPFN_DOWN(phys_addr); 536 + hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); 538 537 539 538 clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100); 540 539

+1 -1

drivers/hv/hv_balloon.c

··· 905 905 * We have some residual hot add range 906 906 * that needs to be hot added; hot add 907 907 * it now. Hot add a multiple of 908 - * of HA_CHUNK that fully covers the pages 908 + * HA_CHUNK that fully covers the pages 909 909 * we have. 910 910 */ 911 911 size = (has->end_pfn - has->ha_end_pfn);

+16 -6

drivers/pci/controller/pci-hyperv.c

··· 1614 1614 1615 1615 static u32 hv_compose_msi_req_v1( 1616 1616 struct pci_create_interrupt *int_pkt, const struct cpumask *affinity, 1617 - u32 slot, u8 vector, u8 vector_count) 1617 + u32 slot, u8 vector, u16 vector_count) 1618 1618 { 1619 1619 int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE; 1620 1620 int_pkt->wslot.slot = slot; ··· 1642 1642 1643 1643 static u32 hv_compose_msi_req_v2( 1644 1644 struct pci_create_interrupt2 *int_pkt, const struct cpumask *affinity, 1645 - u32 slot, u8 vector, u8 vector_count) 1645 + u32 slot, u8 vector, u16 vector_count) 1646 1646 { 1647 1647 int cpu; 1648 1648 ··· 1661 1661 1662 1662 static u32 hv_compose_msi_req_v3( 1663 1663 struct pci_create_interrupt3 *int_pkt, const struct cpumask *affinity, 1664 - u32 slot, u32 vector, u8 vector_count) 1664 + u32 slot, u32 vector, u16 vector_count) 1665 1665 { 1666 1666 int cpu; 1667 1667 ··· 1701 1701 struct compose_comp_ctxt comp; 1702 1702 struct tran_int_desc *int_desc; 1703 1703 struct msi_desc *msi_desc; 1704 - u8 vector, vector_count; 1704 + /* 1705 + * vector_count should be u16: see hv_msi_desc, hv_msi_desc2 1706 + * and hv_msi_desc3. vector must be u32: see hv_msi_desc3. 1707 + */ 1708 + u16 vector_count; 1709 + u32 vector; 1705 1710 struct { 1706 1711 struct pci_packet pci_pkt; 1707 1712 union { ··· 1772 1767 vector_count = 1; 1773 1768 } 1774 1769 1770 + /* 1771 + * hv_compose_msi_req_v1 and v2 are for x86 only, meaning 'vector' 1772 + * can't exceed u8. Cast 'vector' down to u8 for v1/v2 explicitly 1773 + * for better readability. 1774 + */ 1775 1775 memset(&ctxt, 0, sizeof(ctxt)); 1776 1776 init_completion(&comp.comp_pkt.host_event); 1777 1777 ctxt.pci_pkt.completion_func = hv_pci_compose_compl; ··· 1787 1777 size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1, 1788 1778 dest, 1789 1779 hpdev->desc.win_slot.slot, 1790 - vector, 1780 + (u8)vector, 1791 1781 vector_count); 1792 1782 break; 1793 1783 ··· 1796 1786 size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2, 1797 1787 dest, 1798 1788 hpdev->desc.win_slot.slot, 1799 - vector, 1789 + (u8)vector, 1800 1790 vector_count); 1801 1791 break; 1802 1792

+9

include/asm-generic/hyperv-tlfs.h

··· 102 102 volatile s64 tsc_offset; 103 103 } __packed; 104 104 105 + union hv_reference_tsc_msr { 106 + u64 as_uint64; 107 + struct { 108 + u64 enable:1; 109 + u64 reserved:11; 110 + u64 pfn:52; 111 + } __packed; 112 + }; 113 + 105 114 /* 106 115 * The guest OS needs to register the guest ID with the hypervisor. 107 116 * The guest ID is a 64 bit entity and the structure of this ID is

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