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clk: qcom: gcc-ipq6018: remove alpha values from NSS Crypto PLL's config

Since both the 'alpha' and 'alpha_hi' members of the configuration is
initialized with zero values, the output rate of the PLL will be the
same whether alpha mode is enabled or not.

Remove the initialization of the alpha* members to make it clear that
alpha mode is not required to get the desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the clk_alpha_pll_set_rate()
function will get reset the ALPHA_EN bit when the PLL's rate changes,
so dropping 'alpha_en_mask' is safe.

While at it, also add a comment to indicate the frequency the PLL runs
at with the current configuration.

No functional changes, the PLL runs at 1.2 GHz both before and after
the change.

Tested on Xiaomi Mi Router AX1800 (IPQ6018, out-of-tree board).

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-3-9bc6d712bd76@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Gabor Juhos and committed by
Bjorn Andersson
5d11fd2a 41c5ebfb

+1 -3
+1 -3
drivers/clk/qcom/gcc-ipq6018.c
··· 4194 4194 .test_ctl_hi_val = 0x4000, 4195 4195 }; 4196 4196 4197 + /* 1200 MHz configuration */ 4197 4198 static const struct alpha_pll_config nss_crypto_pll_config = { 4198 4199 .l = 0x32, 4199 - .alpha = 0x0, 4200 - .alpha_hi = 0x0, 4201 4200 .config_ctl_val = 0x4001055b, 4202 4201 .main_output_mask = BIT(0), 4203 4202 .pre_div_val = 0x0, ··· 4205 4206 .post_div_mask = GENMASK(11, 8), 4206 4207 .vco_mask = GENMASK(21, 20), 4207 4208 .vco_val = 0x0, 4208 - .alpha_en_mask = BIT(24), 4209 4209 }; 4210 4210 4211 4211 static struct clk_hw *gcc_ipq6018_hws[] = {