Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/dp: convert interfaces to struct intel_display
Convert the intel_dp.[ch] external interfaces to struct intel_display.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7d55f5fd9fc0619be3113098a49259d5374013c6.1734083244.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+39
-57
+3
-3
drivers/gpu/drm/i915/display/intel_display.c
+3
-3
drivers/gpu/drm/i915/display/intel_display.c
···
8156
8156
intel_lvds_init(dev_priv);
8157
8157
intel_crt_init(display);
8158
8158
8159
-
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8159
+
dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
8160
8160
8161
8161
if (ilk_has_edp_a(dev_priv))
8162
8162
g4x_dp_init(dev_priv, DP_A, PORT_A);
···
8202
8202
* trust the port type the VBT declares as we've seen at least
8203
8203
* HDMI ports that the VBT claim are DP or eDP.
8204
8204
*/
8205
-
has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8205
+
has_edp = intel_dp_is_port_edp(display, PORT_B);
8206
8206
has_port = intel_bios_is_port_present(display, PORT_B);
8207
8207
if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8208
8208
has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8209
8209
if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8210
8210
g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8211
8211
8212
-
has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8212
+
has_edp = intel_dp_is_port_edp(display, PORT_C);
8213
8213
has_port = intel_bios_is_port_present(display, PORT_C);
8214
8214
if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8215
8215
has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
+3
-6
drivers/gpu/drm/i915/display/intel_display_driver.c
+3
-6
drivers/gpu/drm/i915/display/intel_display_driver.c
···
573
573
/* part #1: call before irq uninstall */
574
574
void intel_display_driver_remove(struct intel_display *display)
575
575
{
576
-
struct drm_i915_private *i915 = to_i915(display->drm);
577
-
578
576
if (!HAS_DISPLAY(display))
579
577
return;
580
578
···
585
587
* fbdev after it's finalized. MST will be destroyed later as part of
586
588
* drm_mode_config_cleanup()
587
589
*/
588
-
intel_dp_mst_suspend(i915);
590
+
intel_dp_mst_suspend(display);
589
591
}
590
592
591
593
/* part #2: call after irq uninstall */
···
670
672
*/
671
673
int intel_display_driver_suspend(struct intel_display *display)
672
674
{
673
-
struct drm_i915_private *i915 = to_i915(display->drm);
674
675
struct drm_atomic_state *state;
675
676
int ret;
676
677
···
687
690
/* ensure all DPT VMAs have been unpinned for intel_dpt_suspend() */
688
691
flush_workqueue(display->wq.cleanup);
689
692
690
-
intel_dp_mst_suspend(i915);
693
+
intel_dp_mst_suspend(display);
691
694
692
695
return ret;
693
696
}
···
744
747
return;
745
748
746
749
/* MST sideband requires HPD interrupts enabled */
747
-
intel_dp_mst_resume(i915);
750
+
intel_dp_mst_resume(display);
748
751
749
752
display->restore.modeset_state = NULL;
750
753
if (state)
+12
-24
drivers/gpu/drm/i915/display/intel_dp.c
+12
-24
drivers/gpu/drm/i915/display/intel_dp.c
···
828
828
return 6144 * 8;
829
829
}
830
830
831
-
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
831
+
u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
832
832
{
833
-
struct intel_display *display = &i915->display;
834
833
u32 bits_per_pixel = bpp;
835
834
int i;
836
835
···
936
937
return max_bpp;
937
938
}
938
939
939
-
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
940
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
940
941
u32 link_clock, u32 lane_count,
941
942
u32 mode_clock, u32 mode_hdisplay,
942
943
int num_joined_pipes,
···
944
945
u32 pipe_bpp,
945
946
u32 timeslots)
946
947
{
947
-
struct intel_display *display = &i915->display;
948
948
u32 bits_per_pixel, joiner_max_bpp;
949
949
950
950
/*
···
988
990
mode_hdisplay, num_joined_pipes);
989
991
bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
990
992
991
-
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
993
+
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);
992
994
993
995
return bits_per_pixel;
994
996
}
···
1468
1470
true);
1469
1471
} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1470
1472
dsc_max_compressed_bpp =
1471
-
intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1473
+
intel_dp_dsc_get_max_compressed_bpp(display,
1472
1474
max_link_clock,
1473
1475
max_lanes,
1474
1476
target_clock,
···
1486
1488
dsc = dsc_max_compressed_bpp && dsc_slice_count;
1487
1489
}
1488
1490
1489
-
if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc)
1491
+
if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
1490
1492
return MODE_CLOCK_HIGH;
1491
1493
1492
1494
if (mode_rate > max_rate && !dsc)
···
1499
1501
return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
1500
1502
}
1501
1503
1502
-
bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1504
+
bool intel_dp_source_supports_tps3(struct intel_display *display)
1503
1505
{
1504
-
struct intel_display *display = &i915->display;
1505
-
1506
1506
return DISPLAY_VER(display) >= 9 ||
1507
1507
display->platform.broadwell || display->platform.haswell;
1508
1508
}
1509
1509
1510
-
bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1510
+
bool intel_dp_source_supports_tps4(struct intel_display *display)
1511
1511
{
1512
-
struct intel_display *display = &i915->display;
1513
-
1514
1512
return DISPLAY_VER(display) >= 10;
1515
1513
}
1516
1514
···
2584
2590
return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2585
2591
}
2586
2592
2587
-
bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
2593
+
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
2588
2594
int num_joined_pipes)
2589
2595
{
2590
-
struct intel_display *display = &i915->display;
2591
-
2592
2596
/*
2593
2597
* Pipe joiner needs compression up to display 12 due to bandwidth
2594
2598
* limitation. DG2 onwards pipe joiner can be enabled without
···
2604
2612
bool respect_downstream_limits)
2605
2613
{
2606
2614
struct intel_display *display = to_intel_display(encoder);
2607
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2608
2615
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2609
2616
struct intel_connector *connector =
2610
2617
to_intel_connector(conn_state->connector);
···
2625
2634
if (num_joined_pipes > 1)
2626
2635
pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2627
2636
2628
-
joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, num_joined_pipes);
2637
+
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2629
2638
2630
2639
dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2631
2640
!intel_dp_compute_config_limits(intel_dp, pipe_config,
···
6222
6231
return devdata && intel_bios_encoder_supports_edp(devdata);
6223
6232
}
6224
6233
6225
-
bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6234
+
bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
6226
6235
{
6227
-
struct intel_display *display = &i915->display;
6228
6236
const struct intel_bios_encoder_data *devdata =
6229
6237
intel_bios_encoder_data_lookup(display, port);
6230
6238
···
6623
6633
return false;
6624
6634
}
6625
6635
6626
-
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6636
+
void intel_dp_mst_suspend(struct intel_display *display)
6627
6637
{
6628
-
struct intel_display *display = &dev_priv->display;
6629
6638
struct intel_encoder *encoder;
6630
6639
6631
6640
if (!HAS_DISPLAY(display))
···
6646
6657
}
6647
6658
}
6648
6659
6649
-
void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6660
+
void intel_dp_mst_resume(struct intel_display *display)
6650
6661
{
6651
-
struct intel_display *display = &dev_priv->display;
6652
6662
struct intel_encoder *encoder;
6653
6663
6654
6664
if (!HAS_DISPLAY(display))
+11
-11
drivers/gpu/drm/i915/display/intel_dp.h
+11
-11
drivers/gpu/drm/i915/display/intel_dp.h
···
12
12
enum pipe;
13
13
enum port;
14
14
struct drm_connector_state;
15
-
struct drm_encoder;
16
-
struct drm_i915_private;
17
-
struct drm_modeset_acquire_ctx;
18
15
struct drm_dp_vsc_sdp;
16
+
struct drm_encoder;
17
+
struct drm_modeset_acquire_ctx;
19
18
struct intel_atomic_state;
20
19
struct intel_connector;
21
20
struct intel_crtc_state;
22
21
struct intel_digital_port;
22
+
struct intel_display;
23
23
struct intel_dp;
24
24
struct intel_encoder;
25
25
···
87
87
bool intel_dp_has_dsc(const struct intel_connector *connector);
88
88
int intel_dp_link_symbol_size(int rate);
89
89
int intel_dp_link_symbol_clock(int rate);
90
-
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
90
+
bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
91
91
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
92
92
bool long_hpd);
93
93
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
94
94
const struct drm_connector_state *conn_state);
95
95
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
96
96
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
97
-
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
98
-
void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
97
+
void intel_dp_mst_suspend(struct intel_display *display);
98
+
void intel_dp_mst_resume(struct intel_display *display);
99
99
int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
100
100
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
101
101
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
···
112
112
113
113
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
114
114
u8 *link_bw, u8 *rate_select);
115
-
bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
116
-
bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
115
+
bool intel_dp_source_supports_tps3(struct intel_display *display);
116
+
bool intel_dp_source_supports_tps4(struct intel_display *display);
117
117
118
118
int intel_dp_link_required(int pixel_clock, int bpp);
119
119
int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
120
120
int bw_overhead);
121
121
int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
122
122
int max_dprx_rate, int max_dprx_lanes);
123
-
bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
123
+
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
124
124
int num_joined_pipes);
125
125
bool intel_dp_has_joiner(struct intel_dp *intel_dp);
126
126
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
···
137
137
bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
138
138
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
139
139
u8 dsc_max_bpc);
140
-
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
140
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
141
141
u32 link_clock, u32 lane_count,
142
142
u32 mode_clock, u32 mode_hdisplay,
143
143
int num_joined_pipes,
···
173
173
bool intel_dp_supports_dsc(const struct intel_connector *connector,
174
174
const struct intel_crtc_state *crtc_state);
175
175
176
-
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
176
+
u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp);
177
177
178
178
void intel_ddi_update_pipe(struct intel_atomic_state *state,
179
179
struct intel_encoder *encoder,
+2
-3
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+2
-3
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
959
959
enum drm_dp_phy dp_phy)
960
960
{
961
961
struct intel_display *display = to_intel_display(intel_dp);
962
-
struct drm_i915_private *i915 = to_i915(display->drm);
963
962
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
964
963
965
964
/* UHBR+ use separate 128b/132b TPS2 */
···
971
972
* TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
972
973
* LTTPRs must support TPS4.
973
974
*/
974
-
source_tps4 = intel_dp_source_supports_tps4(i915);
975
+
source_tps4 = intel_dp_source_supports_tps4(display);
975
976
sink_tps4 = dp_phy != DP_PHY_DPRX ||
976
977
drm_dp_tps4_supported(intel_dp->dpcd);
977
978
if (source_tps4 && sink_tps4) {
···
989
990
* TPS3 support is mandatory for downstream devices that
990
991
* support HBR2. However, not all sinks follow the spec.
991
992
*/
992
-
source_tps3 = intel_dp_source_supports_tps3(i915);
993
+
source_tps3 = intel_dp_source_supports_tps3(display);
993
994
sink_tps3 = dp_phy != DP_PHY_DPRX ||
994
995
drm_dp_tps3_supported(intel_dp->dpcd);
995
996
if (source_tps3 && sink_tps3) {
+5
-7
drivers/gpu/drm/i915/display/intel_dp_mst.c
+5
-7
drivers/gpu/drm/i915/display/intel_dp_mst.c
···
392
392
{
393
393
struct intel_display *display = to_intel_display(intel_dp);
394
394
struct intel_connector *connector = to_intel_connector(conn_state->connector);
395
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
396
395
int slots = -EINVAL;
397
396
int i, num_bpc;
398
397
u8 dsc_bpc[3] = {};
···
449
450
min_compressed_bpp, max_compressed_bpp);
450
451
451
452
/* Align compressed bpps according to our own constraints */
452
-
max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
453
+
max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, max_compressed_bpp,
453
454
crtc_state->pipe_bpp);
454
-
min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
455
+
min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp,
455
456
crtc_state->pipe_bpp);
456
457
457
458
slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
···
599
600
struct drm_connector_state *conn_state)
600
601
{
601
602
struct intel_display *display = to_intel_display(encoder);
602
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603
603
struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
604
604
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
605
605
struct intel_dp *intel_dp = to_primary_dp(encoder);
···
628
630
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
629
631
pipe_config->has_pch_encoder = false;
630
632
631
-
joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes);
633
+
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
632
634
633
635
dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
634
636
!mst_stream_compute_config_limits(intel_dp, connector,
···
1499
1501
1500
1502
if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1501
1503
dsc_max_compressed_bpp =
1502
-
intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1504
+
intel_dp_dsc_get_max_compressed_bpp(display,
1503
1505
max_link_clock,
1504
1506
max_lanes,
1505
1507
target_clock,
···
1517
1519
dsc = dsc_max_compressed_bpp && dsc_slice_count;
1518
1520
}
1519
1521
1520
-
if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc) {
1522
+
if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
1521
1523
*status = MODE_CLOCK_HIGH;
1522
1524
return 0;
1523
1525
}
+1
-1
drivers/gpu/drm/i915/display/intel_psr.c
+1
-1
drivers/gpu/drm/i915/display/intel_psr.c
+1
-1
drivers/gpu/drm/i915/i915_driver.c
+1
-1
drivers/gpu/drm/i915/i915_driver.c