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clk: renesas: r9a07g043: Add WDT clock and reset entries

Add WDT{0,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven 5d33481f 6c05648b

+10
+10
drivers/clk/renesas/r9a07g043-cpg.c
··· 135 135 0x534, 1), 136 136 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 137 137 0x534, 2), 138 + DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 139 + 0x548, 0), 140 + DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 141 + 0x548, 1), 142 + DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, 143 + 0x548, 4), 144 + DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, 145 + 0x548, 5), 138 146 DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 139 147 0x554, 0), 140 148 DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, ··· 228 220 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), 229 221 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), 230 222 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), 223 + DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), 224 + DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), 231 225 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 232 226 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 233 227 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),