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clk: renesas: r9a07g043: Add OSTM clock and reset entries

Add OSTM{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven 6c05648b 1cbda377

+9
+9
drivers/clk/renesas/r9a07g043-cpg.c
··· 129 129 0x52c, 0), 130 130 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 131 131 0x52c, 1), 132 + DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, 133 + 0x534, 0), 134 + DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, 135 + 0x534, 1), 136 + DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 137 + 0x534, 2), 132 138 DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 133 139 0x554, 0), 134 140 DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, ··· 217 211 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), 218 212 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), 219 213 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 214 + DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), 215 + DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), 216 + DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), 220 217 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 221 218 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 222 219 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),