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drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer

The stage contains configuration for a mixer pair. Currently the plane
supports just one stage and 2 pipes. Quad-pipe support will require
handling 2 stages and 4 pipes at the same time. In preparation for that
add a separate define, PIPES_PER_PLANE, to denote number of pipes that
can be used by the plane.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/675408/
Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-5-ff6232e3472f@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Jun Nie and committed by
Dmitry Baryshkov 5d45171e fb4c972b

+15 -16
+3 -4
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
··· 472 472 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 473 473 bg_alpha_enable = true; 474 474 475 - 476 - for (i = 0; i < PIPES_PER_STAGE; i++) { 475 + for (i = 0; i < PIPES_PER_PLANE; i++) { 477 476 if (!pstate->pipe[i].sspp) 478 477 continue; 479 478 set_bit(pstate->pipe[i].sspp->idx, active_fetch); ··· 1304 1305 return ret; 1305 1306 } 1306 1307 1307 - #define MAX_CHANNELS_PER_CRTC 2 1308 + #define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE 1308 1309 #define MAX_HDISPLAY_SPLIT 1080 1309 1310 1310 1311 static struct msm_display_topology dpu_crtc_get_topology( ··· 1677 1678 state->crtc_x, state->crtc_y, state->crtc_w, 1678 1679 state->crtc_h); 1679 1680 1680 - for (i = 0; i < PIPES_PER_STAGE; i++) { 1681 + for (i = 0; i < PIPES_PER_PLANE; i++) { 1681 1682 if (!pstate->pipe[i].sspp) 1682 1683 continue; 1683 1684 seq_printf(s, "\tsspp[%d]:%s\n",
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
··· 34 34 #define DPU_MAX_PLANES 4 35 35 #endif 36 36 37 + #define PIPES_PER_PLANE 2 37 38 #define PIPES_PER_STAGE 2 38 39 #ifndef DPU_MAX_DE_CURVES 39 40 #define DPU_MAX_DE_CURVES 3
+9 -10
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
··· 636 636 return; 637 637 638 638 /* update sspp */ 639 - for (i = 0; i < PIPES_PER_STAGE; i++) { 639 + for (i = 0; i < PIPES_PER_PLANE; i++) { 640 640 if (!pstate->pipe[i].sspp) 641 641 continue; 642 642 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], ··· 1159 1159 * resources are freed by dpu_crtc_assign_plane_resources(), 1160 1160 * but clean them here. 1161 1161 */ 1162 - for (i = 0; i < PIPES_PER_STAGE; i++) 1162 + for (i = 0; i < PIPES_PER_PLANE; i++) 1163 1163 pstate->pipe[i].sspp = NULL; 1164 1164 1165 1165 return 0; ··· 1213 1213 pipe_cfg = &pstate->pipe_cfg[0]; 1214 1214 r_pipe_cfg = &pstate->pipe_cfg[1]; 1215 1215 1216 - for (i = 0; i < PIPES_PER_STAGE; i++) 1216 + for (i = 0; i < PIPES_PER_PLANE; i++) 1217 1217 pstate->pipe[i].sspp = NULL; 1218 1218 1219 1219 if (!plane_state->fb) ··· 1346 1346 /* force 100% alpha */ 1347 1347 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1348 1348 else { 1349 - for (i = 0; i < PIPES_PER_STAGE; i++) 1349 + for (i = 0; i < PIPES_PER_PLANE; i++) 1350 1350 dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); 1351 1351 } 1352 1352 ··· 1468 1468 crtc->base.id, DRM_RECT_ARG(&state->dst), 1469 1469 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); 1470 1470 1471 - /* move the assignment here, to ease handling to another pairs later */ 1472 - for (i = 0; i < PIPES_PER_STAGE; i++) { 1471 + for (i = 0; i < PIPES_PER_PLANE; i++) { 1473 1472 if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect)) 1474 1473 continue; 1475 1474 dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], ··· 1482 1483 1483 1484 pstate->plane_fetch_bw = 0; 1484 1485 pstate->plane_clk = 0; 1485 - for (i = 0; i < PIPES_PER_STAGE; i++) { 1486 + for (i = 0; i < PIPES_PER_PLANE; i++) { 1486 1487 if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect)) 1487 1488 continue; 1488 1489 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, ··· 1501 1502 struct dpu_sw_pipe *pipe; 1502 1503 int i; 1503 1504 1504 - for (i = 0; i < PIPES_PER_STAGE; i += 1) { 1505 + for (i = 0; i < PIPES_PER_PLANE; i += 1) { 1505 1506 pipe = &pstate->pipe[i]; 1506 1507 if (!pipe->sspp) 1507 1508 continue; ··· 1620 1621 1621 1622 drm_printf(p, "\tstage=%d\n", pstate->stage); 1622 1623 1623 - for (i = 0; i < PIPES_PER_STAGE; i++) { 1624 + for (i = 0; i < PIPES_PER_PLANE; i++) { 1624 1625 pipe = &pstate->pipe[i]; 1625 1626 if (!pipe->sspp) 1626 1627 continue; ··· 1677 1678 return; 1678 1679 1679 1680 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1680 - for (i = 0; i < PIPES_PER_STAGE; i++) { 1681 + for (i = 0; i < PIPES_PER_PLANE; i++) { 1681 1682 if (!pstate->pipe[i].sspp) 1682 1683 continue; 1683 1684 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable);
+2 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
··· 31 31 */ 32 32 struct dpu_plane_state { 33 33 struct drm_plane_state base; 34 - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; 35 - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; 34 + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; 35 + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; 36 36 enum dpu_stage stage; 37 37 bool needs_qos_remap; 38 38 bool pending;