+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 1156 1156 /* 1157 1157 * Writeback 1158 1158 */ 1159 1159 - #define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */ 1159 1159 + #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 1160 1160 1161 1161 struct amdgpu_wb { 1162 1162 struct amdgpu_bo *wb_obj;

+10 -16

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 492 492 memset(&adev->wb.used, 0, sizeof(adev->wb.used)); 493 493 494 494 /* clear wb memory */ 495 495 - memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); 495 495 + memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); 496 496 } 497 497 498 498 return 0; ··· 530 530 */ 531 531 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) 532 532 { 533 533 + wb >>= 3; 533 534 if (wb < adev->wb.num_wb) 534 534 - __clear_bit(wb >> 3, adev->wb.used); 535 535 + __clear_bit(wb, adev->wb.used); 535 536 } 536 537 537 538 /** ··· 1456 1455 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1457 1456 if (!adev->ip_blocks[i].status.hw) 1458 1457 continue; 1459 1459 - if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { 1460 1460 - amdgpu_free_static_csa(adev); 1461 1461 - amdgpu_device_wb_fini(adev); 1462 1462 - amdgpu_device_vram_scratch_fini(adev); 1463 1463 - } 1464 1458 1465 1459 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && 1466 1460 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { ··· 1482 1486 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1483 1487 if (!adev->ip_blocks[i].status.sw) 1484 1488 continue; 1489 1489 + 1490 1490 + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { 1491 1491 + amdgpu_free_static_csa(adev); 1492 1492 + amdgpu_device_wb_fini(adev); 1493 1493 + amdgpu_device_vram_scratch_fini(adev); 1494 1494 + } 1495 1495 + 1485 1496 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); 1486 1497 /* XXX handle errors */ 1487 1498 if (r) { ··· 2287 2284 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 2288 2285 } 2289 2286 drm_modeset_unlock_all(dev); 2290 2290 - } else { 2291 2291 - /* 2292 2292 - * There is no equivalent atomic helper to turn on 2293 2293 - * display, so we defined our own function for this, 2294 2294 - * once suspend resume is supported by the atomic 2295 2295 - * framework this will be reworked 2296 2296 - */ 2297 2297 - amdgpu_dm_display_resume(adev); 2298 2287 } 2299 2288 } 2300 2289 ··· 2721 2726 if (amdgpu_device_has_dc_support(adev)) { 2722 2727 if (drm_atomic_helper_resume(adev->ddev, state)) 2723 2728 dev_info(adev->dev, "drm resume failed:%d\n", r); 2724 2724 - amdgpu_dm_display_resume(adev); 2725 2729 } else { 2726 2730 drm_helper_resume_force_mode(adev->ddev); 2727 2731 }

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c

reviewed

··· 75 75 static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) 76 76 { 77 77 struct amdgpu_gtt_mgr *mgr = man->priv; 78 78 - 78 78 + spin_lock(&mgr->lock); 79 79 drm_mm_takedown(&mgr->mm); 80 80 spin_unlock(&mgr->lock); 81 81 kfree(mgr);

+4 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

reviewed

··· 257 257 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); 258 258 if (r) { 259 259 adev->irq.installed = false; 260 260 - flush_work(&adev->hotplug_work); 260 260 + if (!amdgpu_device_has_dc_support(adev)) 261 261 + flush_work(&adev->hotplug_work); 261 262 cancel_work_sync(&adev->reset_work); 262 263 return r; 263 264 } ··· 283 282 adev->irq.installed = false; 284 283 if (adev->irq.msi_enabled) 285 284 pci_disable_msi(adev->pdev); 286 286 - flush_work(&adev->hotplug_work); 285 285 + if (!amdgpu_device_has_dc_support(adev)) 286 286 + flush_work(&adev->hotplug_work); 287 287 cancel_work_sync(&adev->reset_work); 288 288 } 289 289

+5 -2

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

reviewed

··· 634 634 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 635 635 BUG_ON(vm_inv_eng[i] > 16); 636 636 637 637 - if (adev->asic_type == CHIP_VEGA10) { 637 637 + if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) { 638 638 r = gmc_v9_0_ecc_available(adev); 639 639 if (r == 1) { 640 640 DRM_INFO("ECC is active.\n"); ··· 682 682 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 683 683 if (!adev->mc.vram_width) { 684 684 /* hbm memory channel size */ 685 685 - chansize = 128; 685 685 + if (adev->flags & AMD_IS_APU) 686 686 + chansize = 64; 687 687 + else 688 688 + chansize = 128; 686 689 687 690 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); 688 691 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;

+7 -11

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

reviewed

··· 238 238 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 239 239 { 240 240 struct amdgpu_device *adev = ring->adev; 241 241 - u64 *wptr = NULL; 242 242 - uint64_t local_wptr = 0; 241 241 + u64 wptr; 243 242 244 243 if (ring->use_doorbell) { 245 244 /* XXX check if swapping is necessary on BE */ 246 246 - wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 247 247 - DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 248 248 - *wptr = (*wptr) >> 2; 249 249 - DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 245 245 + wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 246 246 + DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 250 247 } else { 251 248 u32 lowbit, highbit; 252 249 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 253 250 254 254 - wptr = &local_wptr; 255 251 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; 256 252 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 257 253 258 254 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 259 255 me, highbit, lowbit); 260 260 - *wptr = highbit; 261 261 - *wptr = (*wptr) << 32; 262 262 - *wptr |= lowbit; 256 256 + wptr = highbit; 257 257 + wptr = wptr << 32; 258 258 + wptr |= lowbit; 263 259 } 264 260 265 265 - return *wptr; 261 261 + return wptr >> 2; 266 262 } 267 263 268 264 /**

+1 -1

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

reviewed

··· 1618 1618 .set_wptr = uvd_v6_0_enc_ring_set_wptr, 1619 1619 .emit_frame_size = 1620 1620 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ 1621 1621 - 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */ 1621 1621 + 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */ 1622 1622 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ 1623 1623 1, /* uvd_v6_0_enc_ring_insert_end */ 1624 1624 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */

+3 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

reviewed

··· 629 629 { 630 630 struct amdgpu_device *adev = handle; 631 631 struct amdgpu_display_manager *dm = &adev->dm; 632 632 + int ret = 0; 632 633 633 634 /* power on hardware */ 634 635 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 635 636 636 636 - return 0; 637 637 + ret = amdgpu_dm_display_resume(adev); 638 638 + return ret; 637 639 } 638 640 639 641 int amdgpu_dm_display_resume(struct amdgpu_device *adev)

+1 -1

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

reviewed

··· 1465 1465 /* MST doesn't perform link training for now 1466 1466 * TODO: add MST specific link training routine 1467 1467 */ 1468 1468 - if (is_mst_supported(link)) { 1468 1468 + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1469 1469 *link_setting = link->verified_link_cap; 1470 1470 return; 1471 1471 }

+4 -2

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

reviewed

··· 197 197 for (i = 0; i < MAX_PIPES; i++) { 198 198 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 199 199 200 200 - if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp)) 200 200 + if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && 201 201 + !pipe_ctx->plane_res.dpp) || !pipe_ctx->plane_res.ipp) 201 202 continue; 202 203 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 203 204 continue; ··· 274 273 if (pipe_ctx->stream != stream || 275 274 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 276 275 !pipe_ctx->plane_state || 277 277 - (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp)) 276 276 + (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 277 277 + !pipe_ctx->plane_res.ipp) 278 278 continue; 279 279 280 280 if (pipe_ctx->plane_state->address.type

+7 -11

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

reviewed

··· 2756 2756 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 2757 2757 2758 2758 2759 2759 - disable_mclk_switching = ((1 < info.display_count) || 2760 2760 - disable_mclk_switching_for_frame_lock || 2761 2761 - smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) || 2762 2762 - (mode_info.refresh_rate > 120)); 2759 2759 + if (info.display_count == 0) 2760 2760 + disable_mclk_switching = false; 2761 2761 + else 2762 2762 + disable_mclk_switching = ((1 < info.display_count) || 2763 2763 + disable_mclk_switching_for_frame_lock || 2764 2764 + smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) || 2765 2765 + (mode_info.refresh_rate > 120)); 2763 2766 2764 2767 sclk = smu7_ps->performance_levels[0].engine_clock; 2765 2768 mclk = smu7_ps->performance_levels[0].memory_clock; ··· 4536 4533 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4537 4534 int tmp_result, result = 0; 4538 4535 uint32_t sclk_mask = 0, mclk_mask = 0; 4539 4539 - 4540 4540 - if (hwmgr->chip_id == CHIP_FIJI) { 4541 4541 - if (request->type == AMD_PP_GFX_PROFILE) 4542 4542 - smu7_enable_power_containment(hwmgr); 4543 4543 - else if (request->type == AMD_PP_COMPUTE_PROFILE) 4544 4544 - smu7_disable_power_containment(hwmgr); 4545 4545 - } 4546 4536 4547 4537 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) 4548 4538 return -EINVAL;

+7 -4

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

reviewed

··· 3168 3168 disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); 3169 3169 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); 3170 3170 3171 3171 - disable_mclk_switching = (info.display_count > 1) || 3172 3172 - disable_mclk_switching_for_frame_lock || 3173 3173 - disable_mclk_switching_for_vr || 3174 3174 - force_mclk_high; 3171 3171 + if (info.display_count == 0) 3172 3172 + disable_mclk_switching = false; 3173 3173 + else 3174 3174 + disable_mclk_switching = (info.display_count > 1) || 3175 3175 + disable_mclk_switching_for_frame_lock || 3176 3176 + disable_mclk_switching_for_vr || 3177 3177 + force_mclk_high; 3175 3178 3176 3179 sclk = vega10_ps->performance_levels[0].gfx_clock; 3177 3180 mclk = vega10_ps->performance_levels[0].mem_clock;

+4

drivers/gpu/drm/drm_framebuffer.c

reviewed

··· 121 121 r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth); 122 122 r.handles[0] = or->handle; 123 123 124 124 + if (r.pixel_format == DRM_FORMAT_XRGB2101010 && 125 125 + dev->driver->driver_features & DRIVER_PREFER_XBGR_30BPP) 126 126 + r.pixel_format = DRM_FORMAT_XBGR2101010; 127 127 + 124 128 ret = drm_mode_addfb2(dev, &r, file_priv); 125 129 if (ret) 126 130 return ret;

+3 -1

drivers/gpu/drm/i915/i915_gem_execbuffer.c

reviewed

··· 505 505 list_add_tail(&vma->exec_link, &eb->unbound); 506 506 if (drm_mm_node_allocated(&vma->node)) 507 507 err = i915_vma_unbind(vma); 508 508 + if (unlikely(err)) 509 509 + vma->exec_flags = NULL; 508 510 } 509 511 return err; 510 512 } ··· 2412 2410 if (out_fence) { 2413 2411 if (err == 0) { 2414 2412 fd_install(out_fence_fd, out_fence->file); 2415 2415 - args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */ 2413 2413 + args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */ 2416 2414 args->rsvd2 |= (u64)out_fence_fd << 32; 2417 2415 out_fence_fd = -1; 2418 2416 } else {

+2 -2

drivers/gpu/drm/i915/i915_gem_request.c

reviewed

··· 476 476 GEM_BUG_ON(!irqs_disabled()); 477 477 lockdep_assert_held(&engine->timeline->lock); 478 478 479 479 - trace_i915_gem_request_execute(request); 480 480 - 481 479 /* Transfer from per-context onto the global per-engine timeline */ 482 480 timeline = engine->timeline; 483 481 GEM_BUG_ON(timeline == request->timeline); ··· 498 500 spin_lock(&request->timeline->lock); 499 501 list_move_tail(&request->link, &timeline->requests); 500 502 spin_unlock(&request->timeline->lock); 503 503 + 504 504 + trace_i915_gem_request_execute(request); 501 505 502 506 wake_up_all(&request->execute); 503 507 }

+2 -2

drivers/gpu/drm/i915/i915_reg.h

reviewed

··· 2027 2027 #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 2028 2028 #define _CNL_PORT_TX_DW5_LN0_B 0x162654 2029 2029 #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 2030 2030 - #define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 2030 2030 + #define _CNL_PORT_TX_DW5_LN0_D 0x162E54 2031 2031 #define _CNL_PORT_TX_DW5_LN0_F 0x162854 2032 2032 #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ 2033 2033 _CNL_PORT_TX_DW5_GRP_AE, \ ··· 2058 2058 #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C 2059 2059 #define _CNL_PORT_TX_DW7_LN0_B 0x16265C 2060 2060 #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C 2061 2061 - #define _CNL_PORT_TX_DW7_LN0_D 0x162EDC 2061 2061 + #define _CNL_PORT_TX_DW7_LN0_D 0x162E5C 2062 2062 #define _CNL_PORT_TX_DW7_LN0_F 0x16285C 2063 2063 #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ 2064 2064 _CNL_PORT_TX_DW7_GRP_AE, \

+3 -3

drivers/gpu/drm/i915/intel_audio.c

reviewed

··· 779 779 { 780 780 struct intel_encoder *encoder; 781 781 782 782 - if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 783 783 - return NULL; 784 784 - 785 782 /* MST */ 786 783 if (pipe >= 0) { 784 784 + if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 785 785 + return NULL; 786 786 + 787 787 encoder = dev_priv->av_enc_map[pipe]; 788 788 /* 789 789 * when bootup, audio driver may not know it is

+1

drivers/gpu/drm/nouveau/nv50_display.c

reviewed

··· 4477 4477 nouveau_display(dev)->fini = nv50_display_fini; 4478 4478 disp->disp = &nouveau_display(dev)->disp; 4479 4479 dev->mode_config.funcs = &nv50_disp_func; 4480 4480 + dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP; 4480 4481 if (nouveau_atomic) 4481 4482 dev->driver->driver_features |= DRIVER_ATOMIC; 4482 4483

+4

drivers/gpu/drm/radeon/radeon_device.c

reviewed

··· 1365 1365 if ((rdev->flags & RADEON_IS_PCI) && 1366 1366 (rdev->family <= CHIP_RS740)) 1367 1367 rdev->need_dma32 = true; 1368 1368 + #ifdef CONFIG_PPC64 1369 1369 + if (rdev->family == CHIP_CEDAR) 1370 1370 + rdev->need_dma32 = true; 1371 1371 + #endif 1368 1372 1369 1373 dma_bits = rdev->need_dma32 ? 32 : 40; 1370 1374 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));

+1 -5

drivers/gpu/drm/radeon/radeon_pm.c

reviewed

··· 47 47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 48 48 static void radeon_pm_update_profile(struct radeon_device *rdev); 49 49 static void radeon_pm_set_clocks(struct radeon_device *rdev); 50 50 - static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev); 51 50 52 51 int radeon_pm_get_type_index(struct radeon_device *rdev, 53 52 enum radeon_pm_state_type ps_type, ··· 79 80 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 80 81 } 81 82 mutex_unlock(&rdev->pm.mutex); 82 82 - /* allow new DPM state to be picked */ 83 83 - radeon_pm_compute_clocks_dpm(rdev); 84 83 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 85 84 if (rdev->pm.profile == PM_PROFILE_AUTO) { 86 85 mutex_lock(&rdev->pm.mutex); ··· 882 885 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 883 886 /* balanced states don't exist at the moment */ 884 887 if (dpm_state == POWER_STATE_TYPE_BALANCED) 885 885 - dpm_state = rdev->pm.dpm.ac_power ? 886 886 - POWER_STATE_TYPE_PERFORMANCE : POWER_STATE_TYPE_BATTERY; 888 888 + dpm_state = POWER_STATE_TYPE_PERFORMANCE; 887 889 888 890 restart_search: 889 891 /* Pick the best power state based on current conditions */

+5 -2

drivers/gpu/drm/sun4i/sun4i_tcon.c

reviewed

··· 260 260 const struct drm_display_mode *mode) 261 261 { 262 262 /* Configure the dot clock */ 263 263 - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); 263 263 + clk_set_rate_exclusive(tcon->dclk, mode->crtc_clock * 1000); 264 264 265 265 /* Set the resolution */ 266 266 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, ··· 335 335 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 336 336 SUN4I_TCON_GCTL_IOMAP_MASK, 337 337 SUN4I_TCON_GCTL_IOMAP_TCON0); 338 338 + 339 339 + /* Enable the output on the pins */ 340 340 + regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); 338 341 } 339 342 340 343 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, ··· 421 418 WARN_ON(!tcon->quirks->has_channel_1); 422 419 423 420 /* Configure the dot clock */ 424 424 - clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); 421 421 + clk_set_rate_exclusive(tcon->sclk1, mode->crtc_clock * 1000); 425 422 426 423 /* Adjust clock delay */ 427 424 clk_delay = sun4i_tcon_get_clk_delay(mode, 1);

+11 -6

drivers/gpu/drm/virtio/virtgpu_ioctl.c

reviewed

··· 197 197 case VIRTGPU_PARAM_3D_FEATURES: 198 198 value = vgdev->has_virgl_3d == true ? 1 : 0; 199 199 break; 200 200 + case VIRTGPU_PARAM_CAPSET_QUERY_FIX: 201 201 + value = 1; 202 202 + break; 200 203 default: 201 204 return -EINVAL; 202 205 } ··· 475 472 { 476 473 struct virtio_gpu_device *vgdev = dev->dev_private; 477 474 struct drm_virtgpu_get_caps *args = data; 478 478 - int size; 475 475 + unsigned size, host_caps_size; 479 476 int i; 480 477 int found_valid = -1; 481 478 int ret; ··· 483 480 void *ptr; 484 481 if (vgdev->num_capsets == 0) 485 482 return -ENOSYS; 483 483 + 484 484 + /* don't allow userspace to pass 0 */ 485 485 + if (args->size == 0) 486 486 + return -EINVAL; 486 487 487 488 spin_lock(&vgdev->display_info_lock); 488 489 for (i = 0; i < vgdev->num_capsets; i++) { ··· 503 496 return -EINVAL; 504 497 } 505 498 506 506 - size = vgdev->capsets[found_valid].max_size; 507 507 - if (args->size > size) { 508 508 - spin_unlock(&vgdev->display_info_lock); 509 509 - return -EINVAL; 510 510 - } 499 499 + host_caps_size = vgdev->capsets[found_valid].max_size; 500 500 + /* only copy to user the minimum of the host caps size or the guest caps size */ 501 501 + size = min(args->size, host_caps_size); 511 502 512 503 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { 513 504 if (cache_ent->id == args->cap_set_id &&

+1

include/drm/drm_drv.h

reviewed

··· 56 56 #define DRIVER_ATOMIC 0x10000 57 57 #define DRIVER_KMS_LEGACY_CONTEXT 0x20000 58 58 #define DRIVER_SYNCOBJ 0x40000 59 59 + #define DRIVER_PREFER_XBGR_30BPP 0x80000 59 60 60 61 /** 61 62 * struct drm_driver - DRM driver structure

+1

include/uapi/drm/virtgpu_drm.h

reviewed

··· 63 63 }; 64 64 65 65 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ 66 66 + #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ 66 67 67 68 struct drm_virtgpu_getparam { 68 69 __u64 param;