Merge tag 'pwm/for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux

+9 -2

Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml

··· 23 23 const: 3 24 24 25 25 compatible: 26 - enum: 27 - - fsl,imx7ulp-pwm 26 + oneOf: 27 + - enum: 28 + - fsl,imx7ulp-pwm 29 + - items: 30 + - enum: 31 + - fsl,imx93-pwm 32 + - fsl,imx94-pwm 33 + - fsl,imx95-pwm 34 + - const: fsl,imx7ulp-pwm 28 35 29 36 reg: 30 37 maxItems: 1

+65

Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/pwm-nexus-node.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: PWM Nexus node properties 8 + 9 + description: > 10 + Platforms can have a standardized connector/expansion slot that exposes PWMs 11 + signals to expansion boards. 12 + 13 + A nexus node allows to remap a phandle list in a consumer node through a 14 + connector node in a generic way. With this remapping, the consumer node needs 15 + to know only about the nexus node. Resources behind the nexus node are 16 + decoupled by the nexus node itself. 17 + 18 + maintainers: 19 + - Herve Codina <herve.codina@bootlin.com> 20 + 21 + select: true 22 + 23 + properties: 24 + '#pwm-cells': true 25 + 26 + pwm-map: 27 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 28 + 29 + pwm-map-mask: 30 + $ref: /schemas/types.yaml#/definitions/uint32-array 31 + 32 + pwm-map-pass-thru: 33 + $ref: /schemas/types.yaml#/definitions/uint32-array 34 + 35 + dependentRequired: 36 + pwm-map: ['#pwm-cells'] 37 + pwm-map-mask: [ pwm-map ] 38 + pwm-map-pass-thru: [ pwm-map ] 39 + 40 + additionalProperties: true 41 + 42 + examples: 43 + - | 44 + pwm1: pwm@100 { 45 + reg = <0x100 0x10>; 46 + #pwm-cells = <3>; 47 + }; 48 + 49 + pwm2: pwm@200 { 50 + reg = <0x200 0x10>; 51 + #pwm-cells = <3>; 52 + }; 53 + 54 + connector: connector { 55 + #pwm-cells = <3>; 56 + pwm-map = <0 0 0 &pwm1 1 0 0>, 57 + <1 0 0 &pwm2 4 0 0>, 58 + <2 0 0 &pwm1 3 0 0>; 59 + pwm-map-mask = <0xffffffff 0x0 0x0>; 60 + pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; 61 + }; 62 + 63 + device { 64 + pwms = <&connector 1 57000 0>; 65 + };

+2

Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml

··· 30 30 - enum: 31 31 - rockchip,px30-pwm 32 32 - rockchip,rk3308-pwm 33 + - rockchip,rk3528-pwm 34 + - rockchip,rk3562-pwm 33 35 - rockchip,rk3568-pwm 34 36 - rockchip,rk3588-pwm 35 37 - rockchip,rv1126-pwm

+58

Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Sophgo SG2042 PWM controller 8 + 9 + maintainers: 10 + - Chen Wang <unicorn_wang@outlook.com> 11 + 12 + description: 13 + This controller contains 4 channels which can generate PWM waveforms. 14 + 15 + allOf: 16 + - $ref: pwm.yaml# 17 + 18 + properties: 19 + compatible: 20 + const: sophgo,sg2042-pwm 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + clocks: 26 + maxItems: 1 27 + 28 + clock-names: 29 + items: 30 + - const: apb 31 + 32 + resets: 33 + maxItems: 1 34 + 35 + "#pwm-cells": 36 + const: 3 37 + 38 + required: 39 + - compatible 40 + - reg 41 + - clocks 42 + - clock-names 43 + - resets 44 + 45 + unevaluatedProperties: false 46 + 47 + examples: 48 + - | 49 + #include <dt-bindings/reset/sophgo,sg2042-reset.h> 50 + 51 + pwm@7f006000 { 52 + compatible = "sophgo,sg2042-pwm"; 53 + reg = <0x7f006000 0x1000>; 54 + #pwm-cells = <3>; 55 + clocks = <&clock 67>; 56 + clock-names = "apb"; 57 + resets = <&rstgen RST_PWM>; 58 + };

+12 -2

drivers/pwm/Kconfig

··· 567 567 tristate "SiFive PWM support" 568 568 depends on OF 569 569 depends on COMMON_CLK && HAS_IOMEM 570 - depends on RISCV || COMPILE_TEST 570 + depends on ARCH_SIFIVE || COMPILE_TEST 571 571 help 572 572 Generic PWM framework driver for SiFive SoCs. 573 573 ··· 583 583 584 584 To compile this driver as a module, choose M here: the module 585 585 will be called pwm-sl28cpld. 586 + 587 + config PWM_SOPHGO_SG2042 588 + tristate "Sophgo SG2042 PWM support" 589 + depends on ARCH_SOPHGO || COMPILE_TEST 590 + help 591 + PWM driver for the PWM controller on Sophgo SG2042 SoC. The PWM 592 + controller supports outputing 4 channels of PWM waveforms. 593 + 594 + To compile this driver as a module, choose M here: the module 595 + will be called pwm_sophgo_sg2042. 586 596 587 597 config PWM_SPEAR 588 598 tristate "STMicroelectronics SPEAr PWM support" ··· 646 636 will be called pwm-stm32-lp. 647 637 648 638 config PWM_STMPE 649 - bool "STMPE expander PWM export" 639 + tristate "STMPE expander PWM export" 650 640 depends on MFD_STMPE 651 641 help 652 642 This enables support for the PWMs found in the STMPE I/O

+1

drivers/pwm/Makefile

··· 53 53 obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o 54 54 obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o 55 55 obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o 56 + obj-$(CONFIG_PWM_SOPHGO_SG2042) += pwm-sophgo-sg2042.o 56 57 obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o 57 58 obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o 58 59 obj-$(CONFIG_PWM_STI) += pwm-sti.o

+17 -2

drivers/pwm/core.c

··· 1000 1000 } 1001 1001 EXPORT_SYMBOL_GPL(of_pwm_xlate_with_flags); 1002 1002 1003 + /* 1004 + * This callback is used for PXA PWM chips that only have a single PWM line. 1005 + * For such chips you could argue that passing the line number (i.e. the first 1006 + * parameter in the common case) is useless as it's always zero. So compared to 1007 + * the default xlate function of_pwm_xlate_with_flags() the first parameter is 1008 + * the default period and the second are flags. 1009 + * 1010 + * Note that if #pwm-cells = <3>, the semantic is the same as for 1011 + * of_pwm_xlate_with_flags() to allow converting the affected driver to 1012 + * #pwm-cells = <3> without breaking the legacy binding. 1013 + * 1014 + * Don't use for new drivers. 1015 + */ 1003 1016 struct pwm_device * 1004 1017 of_pwm_single_xlate(struct pwm_chip *chip, const struct of_phandle_args *args) 1005 1018 { 1006 1019 struct pwm_device *pwm; 1020 + 1021 + if (args->args_count >= 3) 1022 + return of_pwm_xlate_with_flags(chip, args); 1007 1023 1008 1024 pwm = pwm_request_from_chip(chip, 0, NULL); 1009 1025 if (IS_ERR(pwm)) ··· 1732 1716 return ERR_PTR(index); 1733 1717 } 1734 1718 1735 - err = of_parse_phandle_with_args(np, "pwms", "#pwm-cells", index, 1736 - &args); 1719 + err = of_parse_phandle_with_args_map(np, "pwms", "pwm", index, &args); 1737 1720 if (err) { 1738 1721 pr_err("%s(): can't parse \"pwms\" property\n", __func__); 1739 1722 return ERR_PTR(err);

+2 -2

drivers/pwm/pwm-clps711x.c

··· 98 98 return devm_pwmchip_add(&pdev->dev, chip); 99 99 } 100 100 101 - static const struct of_device_id __maybe_unused clps711x_pwm_dt_ids[] = { 101 + static const struct of_device_id clps711x_pwm_dt_ids[] = { 102 102 { .compatible = "cirrus,ep7209-pwm", }, 103 103 { } 104 104 }; ··· 107 107 static struct platform_driver clps711x_pwm_driver = { 108 108 .driver = { 109 109 .name = "clps711x-pwm", 110 - .of_match_table = of_match_ptr(clps711x_pwm_dt_ids), 110 + .of_match_table = clps711x_pwm_dt_ids, 111 111 }, 112 112 .probe = clps711x_pwm_probe, 113 113 };

+2 -3

drivers/pwm/pwm-gpio.c

··· 207 207 chip->ops = &pwm_gpio_ops; 208 208 chip->atomic = true; 209 209 210 - hrtimer_init(&gpwm->gpio_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 210 + hrtimer_setup(&gpwm->gpio_timer, pwm_gpio_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 211 + 211 212 ret = devm_add_action_or_reset(dev, pwm_gpio_disable_hrtimer, gpwm); 212 213 if (ret) 213 214 return ret; 214 - 215 - gpwm->gpio_timer.function = pwm_gpio_timer; 216 215 217 216 ret = pwmchip_add(chip); 218 217 if (ret < 0)

+1

drivers/pwm/pwm-lpss.c

··· 17 17 #include <linux/kernel.h> 18 18 #include <linux/module.h> 19 19 #include <linux/pm_runtime.h> 20 + #include <linux/pwm.h> 20 21 #include <linux/time.h> 21 22 22 23 #define DEFAULT_SYMBOL_NAMESPACE "PWM_LPSS"

-1

drivers/pwm/pwm-lpss.h

··· 10 10 #ifndef __PWM_LPSS_H 11 11 #define __PWM_LPSS_H 12 12 13 - #include <linux/pwm.h> 14 13 #include <linux/types.h> 15 14 16 15 #include <linux/platform_data/x86/pwm-lpss.h>

+2 -7

drivers/pwm/pwm-pca9685.c

··· 8 8 * based on the pwm-twl-led.c driver 9 9 */ 10 10 11 - #include <linux/acpi.h> 12 11 #include <linux/gpio/driver.h> 13 12 #include <linux/i2c.h> 14 13 #include <linux/module.h> ··· 638 639 }; 639 640 MODULE_DEVICE_TABLE(i2c, pca9685_id); 640 641 641 - #ifdef CONFIG_ACPI 642 642 static const struct acpi_device_id pca9685_acpi_ids[] = { 643 643 { "INT3492", 0 }, 644 644 { /* sentinel */ }, 645 645 }; 646 646 MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); 647 - #endif 648 647 649 - #ifdef CONFIG_OF 650 648 static const struct of_device_id pca9685_dt_ids[] = { 651 649 { .compatible = "nxp,pca9685-pwm", }, 652 650 { /* sentinel */ } 653 651 }; 654 652 MODULE_DEVICE_TABLE(of, pca9685_dt_ids); 655 - #endif 656 653 657 654 static const struct dev_pm_ops pca9685_pwm_pm = { 658 655 SET_RUNTIME_PM_OPS(pca9685_pwm_runtime_suspend, ··· 658 663 static struct i2c_driver pca9685_i2c_driver = { 659 664 .driver = { 660 665 .name = "pca9685-pwm", 661 - .acpi_match_table = ACPI_PTR(pca9685_acpi_ids), 662 - .of_match_table = of_match_ptr(pca9685_dt_ids), 666 + .acpi_match_table = pca9685_acpi_ids, 667 + .of_match_table = pca9685_dt_ids, 663 668 .pm = &pca9685_pwm_pm, 664 669 }, 665 670 .probe = pca9685_pwm_probe,

+194

drivers/pwm/pwm-sophgo-sg2042.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Sophgo SG2042 PWM Controller Driver 4 + * 5 + * Copyright (C) 2024 Sophgo Technology Inc. 6 + * Copyright (C) 2024 Chen Wang <unicorn_wang@outlook.com> 7 + * 8 + * Limitations: 9 + * - After reset, the output of the PWM channel is always high. 10 + * The value of HLPERIOD/PERIOD is 0. 11 + * - When HLPERIOD or PERIOD is reconfigured, PWM will start to 12 + * output waveforms with the new configuration after completing 13 + * the running period. 14 + * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will 15 + * be stopped and the output is pulled to high. 16 + * See the datasheet [1] for more details. 17 + * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM 18 + */ 19 + 20 + #include <linux/clk.h> 21 + #include <linux/err.h> 22 + #include <linux/io.h> 23 + #include <linux/math64.h> 24 + #include <linux/module.h> 25 + #include <linux/platform_device.h> 26 + #include <linux/pwm.h> 27 + #include <linux/reset.h> 28 + 29 + /* 30 + * Offset RegisterName 31 + * 0x0000 HLPERIOD0 32 + * 0x0004 PERIOD0 33 + * 0x0008 HLPERIOD1 34 + * 0x000C PERIOD1 35 + * 0x0010 HLPERIOD2 36 + * 0x0014 PERIOD2 37 + * 0x0018 HLPERIOD3 38 + * 0x001C PERIOD3 39 + * Four groups and every group is composed of HLPERIOD & PERIOD 40 + */ 41 + #define SG2042_PWM_HLPERIOD(chan) ((chan) * 8 + 0) 42 + #define SG2042_PWM_PERIOD(chan) ((chan) * 8 + 4) 43 + 44 + #define SG2042_PWM_CHANNELNUM 4 45 + 46 + /** 47 + * struct sg2042_pwm_ddata - private driver data 48 + * @base: base address of mapped PWM registers 49 + * @clk_rate_hz: rate of base clock in HZ 50 + */ 51 + struct sg2042_pwm_ddata { 52 + void __iomem *base; 53 + unsigned long clk_rate_hz; 54 + }; 55 + 56 + /* 57 + * period_ticks: PERIOD 58 + * hlperiod_ticks: HLPERIOD 59 + */ 60 + static void pwm_sg2042_config(struct sg2042_pwm_ddata *ddata, unsigned int chan, 61 + u32 period_ticks, u32 hlperiod_ticks) 62 + { 63 + void __iomem *base = ddata->base; 64 + 65 + writel(period_ticks, base + SG2042_PWM_PERIOD(chan)); 66 + writel(hlperiod_ticks, base + SG2042_PWM_HLPERIOD(chan)); 67 + } 68 + 69 + static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm, 70 + const struct pwm_state *state) 71 + { 72 + struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip); 73 + u32 hlperiod_ticks; 74 + u32 period_ticks; 75 + 76 + if (state->polarity == PWM_POLARITY_INVERSED) 77 + return -EINVAL; 78 + 79 + if (!state->enabled) { 80 + pwm_sg2042_config(ddata, pwm->hwpwm, 0, 0); 81 + return 0; 82 + } 83 + 84 + /* 85 + * Duration of High level (duty_cycle) = HLPERIOD x Period_of_input_clk 86 + * Duration of One Cycle (period) = PERIOD x Period_of_input_clk 87 + */ 88 + period_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSEC_PER_SEC), U32_MAX); 89 + hlperiod_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->duty_cycle, NSEC_PER_SEC), U32_MAX); 90 + 91 + dev_dbg(pwmchip_parent(chip), "chan[%u]: PERIOD=%u, HLPERIOD=%u\n", 92 + pwm->hwpwm, period_ticks, hlperiod_ticks); 93 + 94 + pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks); 95 + 96 + return 0; 97 + } 98 + 99 + static int pwm_sg2042_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 100 + struct pwm_state *state) 101 + { 102 + struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip); 103 + unsigned int chan = pwm->hwpwm; 104 + u32 hlperiod_ticks; 105 + u32 period_ticks; 106 + 107 + period_ticks = readl(ddata->base + SG2042_PWM_PERIOD(chan)); 108 + hlperiod_ticks = readl(ddata->base + SG2042_PWM_HLPERIOD(chan)); 109 + 110 + if (!period_ticks) { 111 + state->enabled = false; 112 + return 0; 113 + } 114 + 115 + if (hlperiod_ticks > period_ticks) 116 + hlperiod_ticks = period_ticks; 117 + 118 + state->enabled = true; 119 + state->period = DIV_ROUND_UP_ULL((u64)period_ticks * NSEC_PER_SEC, ddata->clk_rate_hz); 120 + state->duty_cycle = DIV_ROUND_UP_ULL((u64)hlperiod_ticks * NSEC_PER_SEC, ddata->clk_rate_hz); 121 + state->polarity = PWM_POLARITY_NORMAL; 122 + 123 + return 0; 124 + } 125 + 126 + static const struct pwm_ops pwm_sg2042_ops = { 127 + .apply = pwm_sg2042_apply, 128 + .get_state = pwm_sg2042_get_state, 129 + }; 130 + 131 + static const struct of_device_id sg2042_pwm_ids[] = { 132 + { .compatible = "sophgo,sg2042-pwm" }, 133 + { } 134 + }; 135 + MODULE_DEVICE_TABLE(of, sg2042_pwm_ids); 136 + 137 + static int pwm_sg2042_probe(struct platform_device *pdev) 138 + { 139 + struct device *dev = &pdev->dev; 140 + struct sg2042_pwm_ddata *ddata; 141 + struct reset_control *rst; 142 + struct pwm_chip *chip; 143 + struct clk *clk; 144 + int ret; 145 + 146 + chip = devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata)); 147 + if (IS_ERR(chip)) 148 + return PTR_ERR(chip); 149 + ddata = pwmchip_get_drvdata(chip); 150 + 151 + ddata->base = devm_platform_ioremap_resource(pdev, 0); 152 + if (IS_ERR(ddata->base)) 153 + return PTR_ERR(ddata->base); 154 + 155 + clk = devm_clk_get_enabled(dev, "apb"); 156 + if (IS_ERR(clk)) 157 + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get base clk\n"); 158 + 159 + ret = devm_clk_rate_exclusive_get(dev, clk); 160 + if (ret) 161 + return dev_err_probe(dev, ret, "Failed to get exclusive rate\n"); 162 + 163 + ddata->clk_rate_hz = clk_get_rate(clk); 164 + /* period = PERIOD * NSEC_PER_SEC / clk_rate_hz */ 165 + if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) 166 + return dev_err_probe(dev, -EINVAL, 167 + "Invalid clock rate: %lu\n", ddata->clk_rate_hz); 168 + 169 + rst = devm_reset_control_get_optional_shared_deasserted(dev, NULL); 170 + if (IS_ERR(rst)) 171 + return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n"); 172 + 173 + chip->ops = &pwm_sg2042_ops; 174 + chip->atomic = true; 175 + 176 + ret = devm_pwmchip_add(dev, chip); 177 + if (ret < 0) 178 + return dev_err_probe(dev, ret, "Failed to register PWM chip\n"); 179 + 180 + return 0; 181 + } 182 + 183 + static struct platform_driver pwm_sg2042_driver = { 184 + .driver = { 185 + .name = "sg2042-pwm", 186 + .of_match_table = sg2042_pwm_ids, 187 + }, 188 + .probe = pwm_sg2042_probe, 189 + }; 190 + module_platform_driver(pwm_sg2042_driver); 191 + 192 + MODULE_AUTHOR("Chen Wang"); 193 + MODULE_DESCRIPTION("Sophgo SG2042 PWM driver"); 194 + MODULE_LICENSE("GPL");

+23 -2

drivers/pwm/pwm-stmpe.c

··· 326 326 return ret; 327 327 } 328 328 329 + platform_set_drvdata(pdev, chip); 330 + 329 331 return 0; 330 332 } 331 333 332 - static struct platform_driver stmpe_pwm_driver = { 334 + static void __exit stmpe_pwm_remove(struct platform_device *pdev) 335 + { 336 + struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 337 + struct pwm_chip *chip = platform_get_drvdata(pdev); 338 + 339 + pwmchip_remove(chip); 340 + stmpe_disable(stmpe, STMPE_BLOCK_PWM); 341 + } 342 + 343 + /* 344 + * stmpe_pwm_remove() lives in .exit.text. For drivers registered via 345 + * module_platform_driver_probe() this is ok because they cannot get unbound at 346 + * runtime. So mark the driver struct with __refdata to prevent modpost 347 + * triggering a section mismatch warning. 348 + */ 349 + static struct platform_driver stmpe_pwm_driver __refdata = { 333 350 .driver = { 334 351 .name = "stmpe-pwm", 335 352 }, 353 + .remove = __exit_p(stmpe_pwm_remove), 336 354 }; 337 - builtin_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe); 355 + module_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe); 356 + 357 + MODULE_DESCRIPTION("STMPE expander PWM"); 358 + MODULE_LICENSE("GPL");

+2 -2

include/linux/pwm.h

··· 379 379 dev_set_drvdata(&chip->dev, data); 380 380 } 381 381 382 - #if IS_ENABLED(CONFIG_PWM) 382 + #if IS_REACHABLE(CONFIG_PWM) 383 383 384 384 /* PWM consumer APIs */ 385 385 int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf); ··· 661 661 PWM_LOOKUP_WITH_MODULE(_provider, _index, _dev_id, _con_id, _period, \ 662 662 _polarity, NULL) 663 663 664 - #if IS_ENABLED(CONFIG_PWM) 664 + #if IS_REACHABLE(CONFIG_PWM) 665 665 void pwm_add_table(struct pwm_lookup *table, size_t num); 666 666 void pwm_remove_table(struct pwm_lookup *table, size_t num); 667 667 #else

Configure Feed

Configure Feed