Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mediatek-drm-next-5.20' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
Mediatek DRM Next for Linux 5.20
1. Add Mediatek Soc DRM (vdosys0) support for mt8195
2. Cooperate with DSI RX devices to modify dsi funcs and delay mipi high to cooperate with panel sequence
3. Add mt8186 dsi compatible and convert dsi_dtbinding to .yaml
4. Add MediaTek SoC DRM (vdosys1) support for mt8195
5. Add MT8195 dp_intf driver
Signed-off-by: Dave Airlie <airlied@redhat.com>
[airlied: fix drm_edid.h include]
From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220709142021.24260-1-chunkuang.hu@kernel.org
+1423
-186
+6
-5
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+6
-5
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
···
4
4
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: mediatek DPI Controller Device Tree Bindings
7
+
title: MediaTek DPI and DP_INTF Controller
8
8
9
9
maintainers:
10
10
- CK Hu <ck.hu@mediatek.com>
11
11
- Jitao shi <jitao.shi@mediatek.com>
12
12
13
13
description: |
14
-
The Mediatek DPI function block is a sink of the display subsystem and
15
-
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
16
-
output bus.
14
+
The MediaTek DPI and DP_INTF function blocks are a sink of the display
15
+
subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
16
+
parallel output bus.
17
17
18
18
properties:
19
19
compatible:
···
24
24
- mediatek,mt8183-dpi
25
25
- mediatek,mt8186-dpi
26
26
- mediatek,mt8192-dpi
27
+
- mediatek,mt8195-dp-intf
27
28
28
29
reg:
29
30
maxItems: 1
···
56
55
$ref: /schemas/graph.yaml#/properties/port
57
56
description:
58
57
Output port node. This port should be connected to the input port of an
59
-
attached HDMI or LVDS encoder chip.
58
+
attached HDMI, LVDS or DisplayPort encoder chip.
60
59
61
60
required:
62
61
- compatible
-62
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
-62
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
···
1
-
Mediatek DSI Device
2
-
===================
3
-
4
-
The Mediatek DSI function block is a sink of the display subsystem and can
5
-
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
6
-
channel output.
7
-
8
-
Required properties:
9
-
- compatible: "mediatek,<chip>-dsi"
10
-
- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
11
-
- reg: Physical base address and length of the controller's registers
12
-
- interrupts: The interrupt signal from the function block.
13
-
- clocks: device clocks
14
-
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15
-
- clock-names: must contain "engine", "digital", and "hs"
16
-
- phys: phandle link to the MIPI D-PHY controller.
17
-
- phy-names: must contain "dphy"
18
-
- port: Output port node with endpoint definitions as described in
19
-
Documentation/devicetree/bindings/graph.txt. This port should be connected
20
-
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
21
-
22
-
Optional properties:
23
-
- resets: list of phandle + reset specifier pair, as described in [1].
24
-
25
-
[1] Documentation/devicetree/bindings/reset/reset.txt
26
-
27
-
MIPI TX Configuration Module
28
-
============================
29
-
30
-
See phy/mediatek,dsi-phy.yaml
31
-
32
-
Example:
33
-
34
-
mipi_tx0: mipi-dphy@10215000 {
35
-
compatible = "mediatek,mt8173-mipi-tx";
36
-
reg = <0 0x10215000 0 0x1000>;
37
-
clocks = <&clk26m>;
38
-
clock-output-names = "mipi_tx0_pll";
39
-
#clock-cells = <0>;
40
-
#phy-cells = <0>;
41
-
drive-strength-microamp = <4600>;
42
-
nvmem-cells= <&mipi_tx_calibration>;
43
-
nvmem-cell-names = "calibration-data";
44
-
};
45
-
46
-
dsi0: dsi@1401b000 {
47
-
compatible = "mediatek,mt8173-dsi";
48
-
reg = <0 0x1401b000 0 0x1000>;
49
-
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
50
-
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
51
-
<&mipi_tx0>;
52
-
clock-names = "engine", "digital", "hs";
53
-
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
54
-
phys = <&mipi_tx0>;
55
-
phy-names = "dphy";
56
-
57
-
port {
58
-
dsi0_out: endpoint {
59
-
remote-endpoint = <&panel_in>;
60
-
};
61
-
};
62
-
};
+116
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+116
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek DSI Controller Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
11
+
- Philipp Zabel <p.zabel@pengutronix.de>
12
+
- Jitao Shi <jitao.shi@mediatek.com>
13
+
- Xinlei Lee <xinlei.lee@mediatek.com>
14
+
15
+
description: |
16
+
The MediaTek DSI function block is a sink of the display subsystem and can
17
+
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
18
+
channel output.
19
+
20
+
allOf:
21
+
- $ref: /schemas/display/dsi-controller.yaml#
22
+
23
+
properties:
24
+
compatible:
25
+
enum:
26
+
- mediatek,mt2701-dsi
27
+
- mediatek,mt7623-dsi
28
+
- mediatek,mt8167-dsi
29
+
- mediatek,mt8173-dsi
30
+
- mediatek,mt8183-dsi
31
+
- mediatek,mt8186-dsi
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
interrupts:
37
+
maxItems: 1
38
+
39
+
power-domains:
40
+
maxItems: 1
41
+
42
+
clocks:
43
+
items:
44
+
- description: Engine Clock
45
+
- description: Digital Clock
46
+
- description: HS Clock
47
+
48
+
clock-names:
49
+
items:
50
+
- const: engine
51
+
- const: digital
52
+
- const: hs
53
+
54
+
resets:
55
+
maxItems: 1
56
+
57
+
phys:
58
+
maxItems: 1
59
+
60
+
phy-names:
61
+
items:
62
+
- const: dphy
63
+
64
+
port:
65
+
$ref: /schemas/graph.yaml#/properties/port
66
+
description:
67
+
Output port node. This port should be connected to the input
68
+
port of an attached DSI panel or DSI-to-eDP encoder chip.
69
+
70
+
required:
71
+
- compatible
72
+
- reg
73
+
- interrupts
74
+
- power-domains
75
+
- clocks
76
+
- clock-names
77
+
- phys
78
+
- phy-names
79
+
- port
80
+
81
+
unevaluatedProperties: false
82
+
83
+
examples:
84
+
- |
85
+
#include <dt-bindings/clock/mt8183-clk.h>
86
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87
+
#include <dt-bindings/interrupt-controller/irq.h>
88
+
#include <dt-bindings/power/mt8183-power.h>
89
+
#include <dt-bindings/phy/phy.h>
90
+
#include <dt-bindings/reset/mt8183-resets.h>
91
+
92
+
soc {
93
+
#address-cells = <2>;
94
+
#size-cells = <2>;
95
+
96
+
dsi0: dsi@14014000 {
97
+
compatible = "mediatek,mt8183-dsi";
98
+
reg = <0 0x14014000 0 0x1000>;
99
+
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
100
+
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
101
+
clocks = <&mmsys CLK_MM_DSI0_MM>,
102
+
<&mmsys CLK_MM_DSI0_IF>,
103
+
<&mipi_tx0>;
104
+
clock-names = "engine", "digital", "hs";
105
+
resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
106
+
phys = <&mipi_tx0>;
107
+
phy-names = "dphy";
108
+
port {
109
+
dsi0_out: endpoint {
110
+
remote-endpoint = <&panel_in>;
111
+
};
112
+
};
113
+
};
114
+
};
115
+
116
+
...
+88
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+88
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MDP RDMA
8
+
9
+
maintainers:
10
+
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
11
+
- Philipp Zabel <p.zabel@pengutronix.de>
12
+
13
+
description:
14
+
The MediaTek MDP RDMA stands for Read Direct Memory Access.
15
+
It provides real time data to the back-end panel driver, such as DSI,
16
+
DPI and DP_INTF.
17
+
It contains one line buffer to store the sufficient pixel data.
18
+
RDMA device node must be siblings to the central MMSYS_CONFIG node.
19
+
For a description of the MMSYS_CONFIG binding, see
20
+
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
21
+
22
+
properties:
23
+
compatible:
24
+
const: mediatek,mt8195-vdo1-rdma
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
power-domains:
33
+
maxItems: 1
34
+
35
+
clocks:
36
+
items:
37
+
- description: RDMA Clock
38
+
39
+
iommus:
40
+
maxItems: 1
41
+
42
+
mediatek,gce-client-reg:
43
+
description:
44
+
The register of display function block to be set by gce. There are 4 arguments,
45
+
such as gce node, subsys id, offset and register size. The subsys id that is
46
+
mapping to the register of display function blocks is defined in the gce header
47
+
include/dt-bindings/gce/<chip>-gce.h of each chips.
48
+
$ref: /schemas/types.yaml#/definitions/phandle-array
49
+
items:
50
+
items:
51
+
- description: phandle of GCE
52
+
- description: GCE subsys id
53
+
- description: register offset
54
+
- description: register size
55
+
maxItems: 1
56
+
57
+
required:
58
+
- compatible
59
+
- reg
60
+
- power-domains
61
+
- clocks
62
+
- iommus
63
+
- mediatek,gce-client-reg
64
+
65
+
additionalProperties: false
66
+
67
+
examples:
68
+
- |
69
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
70
+
#include <dt-bindings/clock/mt8195-clk.h>
71
+
#include <dt-bindings/power/mt8195-power.h>
72
+
#include <dt-bindings/gce/mt8195-gce.h>
73
+
#include <dt-bindings/memory/mt8195-memory-port.h>
74
+
75
+
soc {
76
+
#address-cells = <2>;
77
+
#size-cells = <2>;
78
+
79
+
rdma@1c104000 {
80
+
compatible = "mediatek,mt8195-vdo1-rdma";
81
+
reg = <0 0x1c104000 0 0x1000>;
82
+
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
83
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
84
+
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
85
+
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
86
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
87
+
};
88
+
};
+3
-1
drivers/gpu/drm/mediatek/Makefile
+3
-1
drivers/gpu/drm/mediatek/Makefile
···
4
4
mtk_disp_ccorr.o \
5
5
mtk_disp_color.o \
6
6
mtk_disp_gamma.o \
7
+
mtk_disp_merge.o \
7
8
mtk_disp_ovl.o \
8
9
mtk_disp_rdma.o \
9
10
mtk_drm_crtc.o \
···
13
12
mtk_drm_gem.o \
14
13
mtk_drm_plane.o \
15
14
mtk_dsi.o \
16
-
mtk_dpi.o
15
+
mtk_dpi.o \
16
+
mtk_mdp_rdma.o
17
17
18
18
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
19
19
+20
drivers/gpu/drm/mediatek/mtk_disp_drv.h
+20
drivers/gpu/drm/mediatek/mtk_disp_drv.h
···
8
8
9
9
#include <linux/soc/mediatek/mtk-cmdq.h>
10
10
#include "mtk_drm_plane.h"
11
+
#include "mtk_mdp_rdma.h"
11
12
12
13
int mtk_aal_clk_enable(struct device *dev);
13
14
void mtk_aal_clk_disable(struct device *dev);
···
55
54
void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff);
56
55
void mtk_gamma_start(struct device *dev);
57
56
void mtk_gamma_stop(struct device *dev);
57
+
58
+
int mtk_merge_clk_enable(struct device *dev);
59
+
void mtk_merge_clk_disable(struct device *dev);
60
+
void mtk_merge_config(struct device *dev, unsigned int width,
61
+
unsigned int height, unsigned int vrefresh,
62
+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
63
+
void mtk_merge_start(struct device *dev);
64
+
void mtk_merge_stop(struct device *dev);
65
+
void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
66
+
unsigned int h, unsigned int vrefresh, unsigned int bpc,
67
+
struct cmdq_pkt *cmdq_pkt);
68
+
void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
69
+
void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
58
70
59
71
void mtk_ovl_bgclr_in_on(struct device *dev);
60
72
void mtk_ovl_bgclr_in_off(struct device *dev);
···
116
102
void mtk_rdma_enable_vblank(struct device *dev);
117
103
void mtk_rdma_disable_vblank(struct device *dev);
118
104
105
+
int mtk_mdp_rdma_clk_enable(struct device *dev);
106
+
void mtk_mdp_rdma_clk_disable(struct device *dev);
107
+
void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
108
+
void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
109
+
void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
110
+
struct cmdq_pkt *cmdq_pkt);
119
111
#endif
+320
drivers/gpu/drm/mediatek/mtk_disp_merge.c
+320
drivers/gpu/drm/mediatek/mtk_disp_merge.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
*/
5
+
6
+
#include <linux/clk.h>
7
+
#include <linux/component.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/of_irq.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/reset.h>
12
+
#include <linux/soc/mediatek/mtk-cmdq.h>
13
+
14
+
#include "mtk_drm_ddp_comp.h"
15
+
#include "mtk_drm_drv.h"
16
+
#include "mtk_disp_drv.h"
17
+
18
+
#define DISP_REG_MERGE_CTRL 0x000
19
+
#define MERGE_EN 1
20
+
#define DISP_REG_MERGE_CFG_0 0x010
21
+
#define DISP_REG_MERGE_CFG_1 0x014
22
+
#define DISP_REG_MERGE_CFG_4 0x020
23
+
#define DISP_REG_MERGE_CFG_10 0x038
24
+
/* no swap */
25
+
#define SWAP_MODE 0
26
+
#define FLD_SWAP_MODE GENMASK(4, 0)
27
+
#define DISP_REG_MERGE_CFG_12 0x040
28
+
#define CFG_10_10_1PI_2PO_BUF_MODE 6
29
+
#define CFG_10_10_2PI_2PO_BUF_MODE 8
30
+
#define CFG_11_10_1PI_2PO_MERGE 18
31
+
#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
32
+
#define DISP_REG_MERGE_CFG_24 0x070
33
+
#define DISP_REG_MERGE_CFG_25 0x074
34
+
#define DISP_REG_MERGE_CFG_26 0x078
35
+
#define DISP_REG_MERGE_CFG_27 0x07c
36
+
#define DISP_REG_MERGE_CFG_36 0x0a0
37
+
#define ULTRA_EN BIT(0)
38
+
#define PREULTRA_EN BIT(4)
39
+
#define DISP_REG_MERGE_CFG_37 0x0a4
40
+
/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
41
+
#define BUFFER_MODE 3
42
+
#define FLD_BUFFER_MODE GENMASK(1, 0)
43
+
/*
44
+
* For the ultra and preultra settings, 6us ~ 9us is experience value
45
+
* and the maximum frequency of mmsys clock is 594MHz.
46
+
*/
47
+
#define DISP_REG_MERGE_CFG_40 0x0b0
48
+
/* 6 us, 594M pixel/sec */
49
+
#define ULTRA_TH_LOW (6 * 594)
50
+
/* 8 us, 594M pixel/sec */
51
+
#define ULTRA_TH_HIGH (8 * 594)
52
+
#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
53
+
#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
54
+
#define DISP_REG_MERGE_CFG_41 0x0b4
55
+
/* 8 us, 594M pixel/sec */
56
+
#define PREULTRA_TH_LOW (8 * 594)
57
+
/* 9 us, 594M pixel/sec */
58
+
#define PREULTRA_TH_HIGH (9 * 594)
59
+
#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
60
+
#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
61
+
62
+
#define DISP_REG_MERGE_MUTE_0 0xf00
63
+
64
+
struct mtk_disp_merge {
65
+
void __iomem *regs;
66
+
struct clk *clk;
67
+
struct clk *async_clk;
68
+
struct cmdq_client_reg cmdq_reg;
69
+
bool fifo_en;
70
+
bool mute_support;
71
+
struct reset_control *reset_ctl;
72
+
};
73
+
74
+
void mtk_merge_start(struct device *dev)
75
+
{
76
+
mtk_merge_start_cmdq(dev, NULL);
77
+
}
78
+
79
+
void mtk_merge_stop(struct device *dev)
80
+
{
81
+
mtk_merge_stop_cmdq(dev, NULL);
82
+
}
83
+
84
+
void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
85
+
{
86
+
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
87
+
88
+
if (priv->mute_support)
89
+
mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
90
+
DISP_REG_MERGE_MUTE_0);
91
+
92
+
mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
93
+
DISP_REG_MERGE_CTRL);
94
+
}
95
+
96
+
void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
97
+
{
98
+
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
99
+
100
+
if (priv->mute_support)
101
+
mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs,
102
+
DISP_REG_MERGE_MUTE_0);
103
+
104
+
mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
105
+
DISP_REG_MERGE_CTRL);
106
+
107
+
if (priv->async_clk)
108
+
reset_control_reset(priv->reset_ctl);
109
+
}
110
+
111
+
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
112
+
struct cmdq_pkt *cmdq_pkt)
113
+
{
114
+
mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
115
+
&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
116
+
117
+
mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
118
+
&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
119
+
FLD_BUFFER_MODE);
120
+
121
+
mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
122
+
&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
123
+
FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
124
+
125
+
mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
126
+
&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
127
+
FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
128
+
}
129
+
130
+
void mtk_merge_config(struct device *dev, unsigned int w,
131
+
unsigned int h, unsigned int vrefresh,
132
+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
133
+
{
134
+
mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
135
+
}
136
+
137
+
void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
138
+
unsigned int h, unsigned int vrefresh, unsigned int bpc,
139
+
struct cmdq_pkt *cmdq_pkt)
140
+
{
141
+
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
142
+
unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
143
+
144
+
if (!h || !l_w) {
145
+
dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
146
+
return;
147
+
}
148
+
149
+
if (priv->fifo_en) {
150
+
mtk_merge_fifo_setting(priv, cmdq_pkt);
151
+
mode = CFG_10_10_2PI_2PO_BUF_MODE;
152
+
}
153
+
154
+
if (r_w)
155
+
mode = CFG_11_10_1PI_2PO_MERGE;
156
+
157
+
mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
158
+
DISP_REG_MERGE_CFG_0);
159
+
mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
160
+
DISP_REG_MERGE_CFG_1);
161
+
mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
162
+
DISP_REG_MERGE_CFG_4);
163
+
/*
164
+
* DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
165
+
* DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
166
+
* If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
167
+
* the input0 goes to SRAM0, and input1 goes to SRAM1.
168
+
* If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
169
+
* then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
170
+
*/
171
+
mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
172
+
DISP_REG_MERGE_CFG_24);
173
+
if (r_w)
174
+
mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
175
+
DISP_REG_MERGE_CFG_25);
176
+
else
177
+
mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
178
+
DISP_REG_MERGE_CFG_25);
179
+
180
+
/*
181
+
* DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
182
+
* Only take effect when the merge is setting to merge mode.
183
+
*/
184
+
mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
185
+
DISP_REG_MERGE_CFG_26);
186
+
mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
187
+
DISP_REG_MERGE_CFG_27);
188
+
189
+
mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
190
+
DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
191
+
mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
192
+
DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
193
+
}
194
+
195
+
int mtk_merge_clk_enable(struct device *dev)
196
+
{
197
+
int ret = 0;
198
+
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
199
+
200
+
ret = clk_prepare_enable(priv->clk);
201
+
if (ret) {
202
+
dev_err(dev, "merge clk prepare enable failed\n");
203
+
return ret;
204
+
}
205
+
206
+
ret = clk_prepare_enable(priv->async_clk);
207
+
if (ret) {
208
+
/* should clean up the state of priv->clk */
209
+
clk_disable_unprepare(priv->clk);
210
+
211
+
dev_err(dev, "async clk prepare enable failed\n");
212
+
return ret;
213
+
}
214
+
215
+
return ret;
216
+
}
217
+
218
+
void mtk_merge_clk_disable(struct device *dev)
219
+
{
220
+
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
221
+
222
+
clk_disable_unprepare(priv->async_clk);
223
+
clk_disable_unprepare(priv->clk);
224
+
}
225
+
226
+
static int mtk_disp_merge_bind(struct device *dev, struct device *master,
227
+
void *data)
228
+
{
229
+
return 0;
230
+
}
231
+
232
+
static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
233
+
void *data)
234
+
{
235
+
}
236
+
237
+
static const struct component_ops mtk_disp_merge_component_ops = {
238
+
.bind = mtk_disp_merge_bind,
239
+
.unbind = mtk_disp_merge_unbind,
240
+
};
241
+
242
+
static int mtk_disp_merge_probe(struct platform_device *pdev)
243
+
{
244
+
struct device *dev = &pdev->dev;
245
+
struct resource *res;
246
+
struct mtk_disp_merge *priv;
247
+
int ret;
248
+
249
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
250
+
if (!priv)
251
+
return -ENOMEM;
252
+
253
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
254
+
priv->regs = devm_ioremap_resource(dev, res);
255
+
if (IS_ERR(priv->regs)) {
256
+
dev_err(dev, "failed to ioremap merge\n");
257
+
return PTR_ERR(priv->regs);
258
+
}
259
+
260
+
priv->clk = devm_clk_get(dev, NULL);
261
+
if (IS_ERR(priv->clk)) {
262
+
dev_err(dev, "failed to get merge clk\n");
263
+
return PTR_ERR(priv->clk);
264
+
}
265
+
266
+
priv->async_clk = devm_clk_get_optional(dev, "merge_async");
267
+
if (IS_ERR(priv->async_clk)) {
268
+
dev_err(dev, "failed to get merge async clock\n");
269
+
return PTR_ERR(priv->async_clk);
270
+
}
271
+
272
+
if (priv->async_clk) {
273
+
priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL);
274
+
if (IS_ERR(priv->reset_ctl))
275
+
return PTR_ERR(priv->reset_ctl);
276
+
}
277
+
278
+
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
279
+
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
280
+
if (ret)
281
+
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
282
+
#endif
283
+
284
+
priv->fifo_en = of_property_read_bool(dev->of_node,
285
+
"mediatek,merge-fifo-en");
286
+
287
+
priv->mute_support = of_property_read_bool(dev->of_node,
288
+
"mediatek,merge-mute");
289
+
platform_set_drvdata(pdev, priv);
290
+
291
+
ret = component_add(dev, &mtk_disp_merge_component_ops);
292
+
if (ret != 0)
293
+
dev_err(dev, "Failed to add component: %d\n", ret);
294
+
295
+
return ret;
296
+
}
297
+
298
+
static int mtk_disp_merge_remove(struct platform_device *pdev)
299
+
{
300
+
component_del(&pdev->dev, &mtk_disp_merge_component_ops);
301
+
302
+
return 0;
303
+
}
304
+
305
+
static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
306
+
{ .compatible = "mediatek,mt8195-disp-merge", },
307
+
{},
308
+
};
309
+
310
+
MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
311
+
312
+
struct platform_driver mtk_disp_merge_driver = {
313
+
.probe = mtk_disp_merge_probe,
314
+
.remove = mtk_disp_merge_remove,
315
+
.driver = {
316
+
.name = "mediatek-disp-merge",
317
+
.owner = THIS_MODULE,
318
+
.of_match_table = mtk_disp_merge_driver_dt_match,
319
+
},
320
+
};
+4
-4
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+4
-4
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
···
370
370
.fifo_size = 5 * SZ_1K,
371
371
};
372
372
373
-
static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
374
-
.fifo_size = 5 * SZ_1K,
373
+
static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
374
+
.fifo_size = 1920,
375
375
};
376
376
377
377
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
···
381
381
.data = &mt8173_rdma_driver_data},
382
382
{ .compatible = "mediatek,mt8183-disp-rdma",
383
383
.data = &mt8183_rdma_driver_data},
384
-
{ .compatible = "mediatek,mt8192-disp-rdma",
385
-
.data = &mt8192_rdma_driver_data},
384
+
{ .compatible = "mediatek,mt8195-disp-rdma",
385
+
.data = &mt8195_rdma_driver_data},
386
386
{},
387
387
};
388
388
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
+200
-60
drivers/gpu/drm/mediatek/mtk_dpi.c
+200
-60
drivers/gpu/drm/mediatek/mtk_dpi.c
···
23
23
#include <drm/drm_bridge.h>
24
24
#include <drm/drm_bridge_connector.h>
25
25
#include <drm/drm_crtc.h>
26
+
#include <drm/drm_edid.h>
26
27
#include <drm/drm_of.h>
27
28
#include <drm/drm_simple_kms_helper.h>
28
29
···
57
56
58
57
enum mtk_dpi_out_color_format {
59
58
MTK_DPI_COLOR_FORMAT_RGB,
60
-
MTK_DPI_COLOR_FORMAT_RGB_FULL,
61
-
MTK_DPI_COLOR_FORMAT_YCBCR_444,
62
-
MTK_DPI_COLOR_FORMAT_YCBCR_422,
63
-
MTK_DPI_COLOR_FORMAT_XV_YCC,
64
-
MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL,
65
-
MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
59
+
MTK_DPI_COLOR_FORMAT_YCBCR_422
66
60
};
67
61
68
62
struct mtk_dpi {
···
115
119
u16 c_bottom;
116
120
};
117
121
122
+
/**
123
+
* struct mtk_dpi_conf - Configuration of mediatek dpi.
124
+
* @cal_factor: Callback function to calculate factor value.
125
+
* @reg_h_fre_con: Register address of frequency control.
126
+
* @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
127
+
* @edge_sel_en: Enable of edge selection.
128
+
* @output_fmts: Array of supported output formats.
129
+
* @num_output_fmts: Quantity of supported output formats.
130
+
* @is_ck_de_pol: Support CK/DE polarity.
131
+
* @swap_input_support: Support input swap function.
132
+
* @support_direct_pin: IP supports direct connection to dpi panels.
133
+
* @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
134
+
* config to enable this feature.
135
+
* @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
136
+
* (no shift).
137
+
* @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
138
+
* @channel_swap_shift: Shift value of channel swap.
139
+
* @yuv422_en_bit: Enable bit of yuv422.
140
+
* @csc_enable_bit: Enable bit of CSC.
141
+
* @pixels_per_iter: Quantity of transferred pixels per iteration.
142
+
*/
118
143
struct mtk_dpi_conf {
119
144
unsigned int (*cal_factor)(int clock);
120
145
u32 reg_h_fre_con;
···
143
126
bool edge_sel_en;
144
127
const u32 *output_fmts;
145
128
u32 num_output_fmts;
129
+
bool is_ck_de_pol;
130
+
bool swap_input_support;
131
+
bool support_direct_pin;
132
+
bool input_2pixel;
133
+
u32 dimension_mask;
134
+
u32 hvsize_mask;
135
+
u32 channel_swap_shift;
136
+
u32 yuv422_en_bit;
137
+
u32 csc_enable_bit;
138
+
u32 pixels_per_iter;
146
139
};
147
140
148
141
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
···
181
154
static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
182
155
struct mtk_dpi_sync_param *sync)
183
156
{
184
-
mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
185
-
sync->sync_width << HPW, HPW_MASK);
186
-
mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
187
-
sync->back_porch << HBP, HBP_MASK);
157
+
mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW,
158
+
dpi->conf->dimension_mask << HPW);
159
+
mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP,
160
+
dpi->conf->dimension_mask << HBP);
188
161
mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
189
-
HFP_MASK);
162
+
dpi->conf->dimension_mask << HFP);
190
163
}
191
164
192
165
static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
···
194
167
u32 width_addr, u32 porch_addr)
195
168
{
196
169
mtk_dpi_mask(dpi, width_addr,
197
-
sync->sync_width << VSYNC_WIDTH_SHIFT,
198
-
VSYNC_WIDTH_MASK);
199
-
mtk_dpi_mask(dpi, width_addr,
200
170
sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
201
171
VSYNC_HALF_LINE_MASK);
172
+
mtk_dpi_mask(dpi, width_addr,
173
+
sync->sync_width << VSYNC_WIDTH_SHIFT,
174
+
dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT);
202
175
mtk_dpi_mask(dpi, porch_addr,
203
176
sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
204
-
VSYNC_BACK_PORCH_MASK);
177
+
dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT);
205
178
mtk_dpi_mask(dpi, porch_addr,
206
179
sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
207
-
VSYNC_FRONT_PORCH_MASK);
180
+
dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT);
208
181
}
209
182
210
183
static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
···
238
211
struct mtk_dpi_polarities *dpi_pol)
239
212
{
240
213
unsigned int pol;
214
+
unsigned int mask;
241
215
242
-
pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) |
243
-
(dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) |
244
-
(dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
216
+
mask = HSYNC_POL | VSYNC_POL;
217
+
pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
245
218
(dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
246
-
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
247
-
CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
219
+
if (dpi->conf->is_ck_de_pol) {
220
+
mask |= CK_POL | DE_POL;
221
+
pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?
222
+
0 : CK_POL) |
223
+
(dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?
224
+
0 : DE_POL);
225
+
}
226
+
227
+
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
248
228
}
249
229
250
230
static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
···
266
232
267
233
static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
268
234
{
269
-
mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
270
-
mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
235
+
mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
236
+
dpi->conf->hvsize_mask << HSIZE);
237
+
mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
238
+
dpi->conf->hvsize_mask << VSIZE);
271
239
}
272
240
273
-
static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
274
-
struct mtk_dpi_yc_limit *limit)
241
+
static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
275
242
{
276
-
mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT,
243
+
struct mtk_dpi_yc_limit limit;
244
+
245
+
if (drm_default_rgb_quant_range(&dpi->mode) ==
246
+
HDMI_QUANTIZATION_RANGE_LIMITED) {
247
+
limit.y_bottom = 0x10;
248
+
limit.y_top = 0xfe0;
249
+
limit.c_bottom = 0x10;
250
+
limit.c_top = 0xfe0;
251
+
} else {
252
+
limit.y_bottom = 0;
253
+
limit.y_top = 0xfff;
254
+
limit.c_bottom = 0;
255
+
limit.c_top = 0xfff;
256
+
}
257
+
258
+
mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT,
277
259
Y_LIMINT_BOT_MASK);
278
-
mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP,
260
+
mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP,
279
261
Y_LIMINT_TOP_MASK);
280
-
mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT,
262
+
mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT,
281
263
C_LIMIT_BOT_MASK);
282
-
mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP,
264
+
mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP,
283
265
C_LIMIT_TOP_MASK);
284
266
}
285
267
···
383
333
break;
384
334
}
385
335
386
-
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK);
336
+
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
337
+
val << dpi->conf->channel_swap_shift,
338
+
CH_SWAP_MASK << dpi->conf->channel_swap_shift);
387
339
}
388
340
389
341
static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
390
342
{
391
-
mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
343
+
mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0,
344
+
dpi->conf->yuv422_en_bit);
392
345
}
393
346
394
347
static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
395
348
{
396
-
mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE);
349
+
mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0,
350
+
dpi->conf->csc_enable_bit);
397
351
}
398
352
399
353
static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
···
419
365
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
420
366
enum mtk_dpi_out_color_format format)
421
367
{
422
-
if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) ||
423
-
(format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) {
424
-
mtk_dpi_config_yuv422_enable(dpi, false);
425
-
mtk_dpi_config_csc_enable(dpi, true);
426
-
mtk_dpi_config_swap_input(dpi, false);
427
-
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR);
428
-
} else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) ||
429
-
(format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) {
368
+
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
369
+
370
+
if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) {
430
371
mtk_dpi_config_yuv422_enable(dpi, true);
431
372
mtk_dpi_config_csc_enable(dpi, true);
432
-
mtk_dpi_config_swap_input(dpi, true);
433
-
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
373
+
374
+
/*
375
+
* If height is smaller than 720, we need to use RGB_TO_BT601
376
+
* to transfer to yuv422. Otherwise, we use RGB_TO_JPEG.
377
+
*/
378
+
mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ?
379
+
MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG,
380
+
INT_MATRIX_SEL_MASK);
434
381
} else {
435
382
mtk_dpi_config_yuv422_enable(dpi, false);
436
383
mtk_dpi_config_csc_enable(dpi, false);
437
-
mtk_dpi_config_swap_input(dpi, false);
438
-
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
384
+
if (dpi->conf->swap_input_support)
385
+
mtk_dpi_config_swap_input(dpi, false);
439
386
}
440
387
}
441
388
···
492
437
if (dpi->pinctrl && dpi->pins_dpi)
493
438
pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
494
439
495
-
mtk_dpi_enable(dpi);
496
440
return 0;
497
441
498
442
err_pixel:
···
504
450
static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
505
451
struct drm_display_mode *mode)
506
452
{
507
-
struct mtk_dpi_yc_limit limit;
508
453
struct mtk_dpi_polarities dpi_pol;
509
454
struct mtk_dpi_sync_param hsync;
510
455
struct mtk_dpi_sync_param vsync_lodd = { 0 };
···
525
472
clk_set_rate(dpi->tvd_clk, pll_rate);
526
473
pll_rate = clk_get_rate(dpi->tvd_clk);
527
474
475
+
/*
476
+
* Depending on the IP version, we may output a different amount of
477
+
* pixels for each iteration: divide the clock by this number and
478
+
* adjust the display porches accordingly.
479
+
*/
528
480
vm.pixelclock = pll_rate / factor;
481
+
vm.pixelclock /= dpi->conf->pixels_per_iter;
482
+
529
483
if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
530
484
(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
531
485
clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
···
545
485
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
546
486
pll_rate, vm.pixelclock);
547
487
548
-
limit.c_bottom = 0x0010;
549
-
limit.c_top = 0x0FE0;
550
-
limit.y_bottom = 0x0010;
551
-
limit.y_top = 0x0FE0;
552
-
553
488
dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
554
489
dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
555
490
dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
556
491
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
557
492
dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
558
493
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
559
-
hsync.sync_width = vm.hsync_len;
560
-
hsync.back_porch = vm.hback_porch;
561
-
hsync.front_porch = vm.hfront_porch;
494
+
495
+
/*
496
+
* Depending on the IP version, we may output a different amount of
497
+
* pixels for each iteration: divide the clock by this number and
498
+
* adjust the display porches accordingly.
499
+
*/
500
+
hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter;
501
+
hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter;
502
+
hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter;
503
+
562
504
hsync.shift_half_line = false;
563
505
vsync_lodd.sync_width = vm.vsync_len;
564
506
vsync_lodd.back_porch = vm.vback_porch;
···
599
537
else
600
538
mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
601
539
602
-
mtk_dpi_config_channel_limit(dpi, &limit);
540
+
mtk_dpi_config_channel_limit(dpi);
603
541
mtk_dpi_config_bit_num(dpi, dpi->bit_num);
604
542
mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
605
-
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
606
543
mtk_dpi_config_color_format(dpi, dpi->color_format);
607
-
mtk_dpi_config_2n_h_fre(dpi);
608
-
mtk_dpi_dual_edge(dpi);
609
-
mtk_dpi_config_disable_edge(dpi);
544
+
if (dpi->conf->support_direct_pin) {
545
+
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
546
+
mtk_dpi_config_2n_h_fre(dpi);
547
+
mtk_dpi_dual_edge(dpi);
548
+
mtk_dpi_config_disable_edge(dpi);
549
+
}
550
+
if (dpi->conf->input_2pixel) {
551
+
mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
552
+
DPINTF_INPUT_2P_EN);
553
+
}
610
554
mtk_dpi_sw_reset(dpi, false);
611
555
612
556
return 0;
···
691
623
dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
692
624
dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
693
625
dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
694
-
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
626
+
if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
627
+
dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422;
628
+
else
629
+
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
695
630
696
631
return 0;
697
632
}
···
730
659
731
660
mtk_dpi_power_on(dpi);
732
661
mtk_dpi_set_display_mode(dpi, &dpi->mode);
662
+
mtk_dpi_enable(dpi);
733
663
}
734
664
735
665
static enum drm_mode_status
···
854
782
return 2;
855
783
}
856
784
785
+
static unsigned int mt8195_dpintf_calculate_factor(int clock)
786
+
{
787
+
if (clock < 70000)
788
+
return 4;
789
+
else if (clock < 200000)
790
+
return 2;
791
+
else
792
+
return 1;
793
+
}
794
+
857
795
static const u32 mt8173_output_fmts[] = {
858
796
MEDIA_BUS_FMT_RGB888_1X24,
859
797
};
···
873
791
MEDIA_BUS_FMT_RGB888_2X12_BE,
874
792
};
875
793
794
+
static const u32 mt8195_output_fmts[] = {
795
+
MEDIA_BUS_FMT_RGB888_1X24,
796
+
MEDIA_BUS_FMT_YUYV8_1X16,
797
+
};
798
+
876
799
static const struct mtk_dpi_conf mt8173_conf = {
877
800
.cal_factor = mt8173_calculate_factor,
878
801
.reg_h_fre_con = 0xe0,
879
802
.max_clock_khz = 300000,
880
803
.output_fmts = mt8173_output_fmts,
881
804
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
805
+
.pixels_per_iter = 1,
806
+
.is_ck_de_pol = true,
807
+
.swap_input_support = true,
808
+
.support_direct_pin = true,
809
+
.dimension_mask = HPW_MASK,
810
+
.hvsize_mask = HSIZE_MASK,
811
+
.channel_swap_shift = CH_SWAP,
812
+
.yuv422_en_bit = YUV422_EN,
813
+
.csc_enable_bit = CSC_ENABLE,
882
814
};
883
815
884
816
static const struct mtk_dpi_conf mt2701_conf = {
···
902
806
.max_clock_khz = 150000,
903
807
.output_fmts = mt8173_output_fmts,
904
808
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
809
+
.pixels_per_iter = 1,
810
+
.is_ck_de_pol = true,
811
+
.swap_input_support = true,
812
+
.support_direct_pin = true,
813
+
.dimension_mask = HPW_MASK,
814
+
.hvsize_mask = HSIZE_MASK,
815
+
.channel_swap_shift = CH_SWAP,
816
+
.yuv422_en_bit = YUV422_EN,
817
+
.csc_enable_bit = CSC_ENABLE,
905
818
};
906
819
907
820
static const struct mtk_dpi_conf mt8183_conf = {
···
919
814
.max_clock_khz = 100000,
920
815
.output_fmts = mt8183_output_fmts,
921
816
.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
817
+
.pixels_per_iter = 1,
818
+
.is_ck_de_pol = true,
819
+
.swap_input_support = true,
820
+
.support_direct_pin = true,
821
+
.dimension_mask = HPW_MASK,
822
+
.hvsize_mask = HSIZE_MASK,
823
+
.channel_swap_shift = CH_SWAP,
824
+
.yuv422_en_bit = YUV422_EN,
825
+
.csc_enable_bit = CSC_ENABLE,
922
826
};
923
827
924
828
static const struct mtk_dpi_conf mt8192_conf = {
···
936
822
.max_clock_khz = 150000,
937
823
.output_fmts = mt8183_output_fmts,
938
824
.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
825
+
.pixels_per_iter = 1,
826
+
.is_ck_de_pol = true,
827
+
.swap_input_support = true,
828
+
.support_direct_pin = true,
829
+
.dimension_mask = HPW_MASK,
830
+
.hvsize_mask = HSIZE_MASK,
831
+
.channel_swap_shift = CH_SWAP,
832
+
.yuv422_en_bit = YUV422_EN,
833
+
.csc_enable_bit = CSC_ENABLE,
834
+
};
835
+
836
+
static const struct mtk_dpi_conf mt8195_dpintf_conf = {
837
+
.cal_factor = mt8195_dpintf_calculate_factor,
838
+
.max_clock_khz = 600000,
839
+
.output_fmts = mt8195_output_fmts,
840
+
.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
841
+
.pixels_per_iter = 4,
842
+
.input_2pixel = true,
843
+
.dimension_mask = DPINTF_HPW_MASK,
844
+
.hvsize_mask = DPINTF_HSIZE_MASK,
845
+
.channel_swap_shift = DPINTF_CH_SWAP,
846
+
.yuv422_en_bit = DPINTF_YUV422_EN,
847
+
.csc_enable_bit = DPINTF_CSC_ENABLE,
939
848
};
940
849
941
850
static int mtk_dpi_probe(struct platform_device *pdev)
···
1082
945
},
1083
946
{ .compatible = "mediatek,mt8192-dpi",
1084
947
.data = &mt8192_conf,
948
+
},
949
+
{ .compatible = "mediatek,mt8195-dp-intf",
950
+
.data = &mt8195_dpintf_conf,
1085
951
},
1086
952
{ },
1087
953
};
+18
drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+18
drivers/gpu/drm/mediatek/mtk_dpi_regs.h
···
40
40
#define FAKE_DE_LEVEN BIT(21)
41
41
#define FAKE_DE_RODD BIT(22)
42
42
#define FAKE_DE_REVEN BIT(23)
43
+
#define DPINTF_YUV422_EN BIT(24)
44
+
#define DPINTF_CSC_ENABLE BIT(26)
45
+
#define DPINTF_INPUT_2P_EN BIT(29)
43
46
44
47
#define DPI_OUTPUT_SETTING 0x14
45
48
#define CH_SWAP 0
49
+
#define DPINTF_CH_SWAP 1
46
50
#define CH_SWAP_MASK (0x7 << 0)
47
51
#define SWAP_RGB 0x00
48
52
#define SWAP_GBR 0x01
···
84
80
#define DPI_SIZE 0x18
85
81
#define HSIZE 0
86
82
#define HSIZE_MASK (0x1FFF << 0)
83
+
#define DPINTF_HSIZE_MASK (0xFFFF << 0)
87
84
#define VSIZE 16
88
85
#define VSIZE_MASK (0x1FFF << 16)
86
+
#define DPINTF_VSIZE_MASK (0xFFFF << 16)
89
87
90
88
#define DPI_DDR_SETTING 0x1C
91
89
#define DDR_EN BIT(0)
···
99
93
#define DPI_TGEN_HWIDTH 0x20
100
94
#define HPW 0
101
95
#define HPW_MASK (0xFFF << 0)
96
+
#define DPINTF_HPW_MASK (0xFFFF << 0)
102
97
103
98
#define DPI_TGEN_HPORCH 0x24
104
99
#define HBP 0
105
100
#define HBP_MASK (0xFFF << 0)
101
+
#define DPINTF_HBP_MASK (0xFFFF << 0)
106
102
#define HFP 16
107
103
#define HFP_MASK (0xFFF << 16)
104
+
#define DPINTF_HFP_MASK (0xFFFF << 16)
108
105
109
106
#define DPI_TGEN_VWIDTH 0x28
110
107
#define DPI_TGEN_VPORCH 0x2C
111
108
112
109
#define VSYNC_WIDTH_SHIFT 0
113
110
#define VSYNC_WIDTH_MASK (0xFFF << 0)
111
+
#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0)
114
112
#define VSYNC_HALF_LINE_SHIFT 16
115
113
#define VSYNC_HALF_LINE_MASK BIT(16)
116
114
#define VSYNC_BACK_PORCH_SHIFT 0
117
115
#define VSYNC_BACK_PORCH_MASK (0xFFF << 0)
116
+
#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0)
118
117
#define VSYNC_FRONT_PORCH_SHIFT 16
119
118
#define VSYNC_FRONT_PORCH_MASK (0xFFF << 16)
119
+
#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16)
120
120
121
121
#define DPI_BG_HCNTL 0x30
122
122
#define BG_RIGHT (0x1FFF << 0)
···
229
217
230
218
#define EDGE_SEL_EN BIT(5)
231
219
#define H_FRE_2N BIT(25)
220
+
221
+
#define DPI_MATRIX_SET 0xB4
222
+
#define INT_MATRIX_SEL_MASK GENMASK(4, 0)
223
+
#define MATRIX_SEL_RGB_TO_JPEG 0
224
+
#define MATRIX_SEL_RGB_TO_BT601 2
225
+
232
226
#endif /* __MTK_DPI_REGS_H */
+68
-1
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+68
-1
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
···
40
40
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
41
41
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
42
42
43
+
#define DISP_REG_DSC_CON 0x0000
44
+
#define DSC_EN BIT(0)
45
+
#define DSC_DUAL_INOUT BIT(2)
46
+
#define DSC_BYPASS BIT(4)
47
+
#define DSC_UFOE_SEL BIT(16)
48
+
43
49
#define DISP_REG_OD_EN 0x0000
44
50
#define DISP_REG_OD_CFG 0x0020
45
51
#define OD_RELAYMODE BIT(0)
···
187
181
DISP_DITHERING, cmdq_pkt);
188
182
}
189
183
184
+
static void mtk_dsc_config(struct device *dev, unsigned int w,
185
+
unsigned int h, unsigned int vrefresh,
186
+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
187
+
{
188
+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
189
+
190
+
/* dsc bypass mode */
191
+
mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
192
+
DISP_REG_DSC_CON, DSC_BYPASS);
193
+
mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
194
+
DISP_REG_DSC_CON, DSC_UFOE_SEL);
195
+
mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
196
+
DISP_REG_DSC_CON, DSC_DUAL_INOUT);
197
+
}
198
+
199
+
static void mtk_dsc_start(struct device *dev)
200
+
{
201
+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
202
+
203
+
/* write with mask to reserve the value set in mtk_dsc_config */
204
+
mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
205
+
}
206
+
207
+
static void mtk_dsc_stop(struct device *dev)
208
+
{
209
+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
210
+
211
+
writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
212
+
}
213
+
190
214
static void mtk_od_config(struct device *dev, unsigned int w,
191
215
unsigned int h, unsigned int vrefresh,
192
216
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
···
306
270
.stop = mtk_dpi_stop,
307
271
};
308
272
273
+
static const struct mtk_ddp_comp_funcs ddp_dsc = {
274
+
.clk_enable = mtk_ddp_clk_enable,
275
+
.clk_disable = mtk_ddp_clk_disable,
276
+
.config = mtk_dsc_config,
277
+
.start = mtk_dsc_start,
278
+
.stop = mtk_dsc_stop,
279
+
};
280
+
309
281
static const struct mtk_ddp_comp_funcs ddp_dsi = {
310
282
.start = mtk_dsi_ddp_start,
311
283
.stop = mtk_dsi_ddp_stop,
···
326
282
.config = mtk_gamma_config,
327
283
.start = mtk_gamma_start,
328
284
.stop = mtk_gamma_stop,
285
+
};
286
+
287
+
static const struct mtk_ddp_comp_funcs ddp_merge = {
288
+
.clk_enable = mtk_merge_clk_enable,
289
+
.clk_disable = mtk_merge_clk_disable,
290
+
.start = mtk_merge_start,
291
+
.stop = mtk_merge_stop,
292
+
.config = mtk_merge_config,
329
293
};
330
294
331
295
static const struct mtk_ddp_comp_funcs ddp_od = {
···
395
343
[MTK_DISP_CCORR] = "ccorr",
396
344
[MTK_DISP_COLOR] = "color",
397
345
[MTK_DISP_DITHER] = "dither",
346
+
[MTK_DISP_DSC] = "dsc",
398
347
[MTK_DISP_GAMMA] = "gamma",
348
+
[MTK_DISP_MERGE] = "merge",
399
349
[MTK_DISP_MUTEX] = "mutex",
400
350
[MTK_DISP_OD] = "od",
401
351
[MTK_DISP_OVL] = "ovl",
···
407
353
[MTK_DISP_RDMA] = "rdma",
408
354
[MTK_DISP_UFOE] = "ufoe",
409
355
[MTK_DISP_WDMA] = "wdma",
356
+
[MTK_DP_INTF] = "dp-intf",
410
357
[MTK_DPI] = "dpi",
411
358
[MTK_DSI] = "dsi",
412
359
};
···
425
370
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
426
371
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
427
372
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
428
-
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
373
+
[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
374
+
[DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
375
+
[DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
429
376
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
430
377
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
378
+
[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
379
+
[DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
431
380
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
432
381
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
433
382
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
434
383
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
435
384
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
385
+
[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
386
+
[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
387
+
[DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
388
+
[DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
389
+
[DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
390
+
[DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
436
391
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
437
392
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
438
393
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
···
545
480
type == MTK_DISP_CCORR ||
546
481
type == MTK_DISP_COLOR ||
547
482
type == MTK_DISP_GAMMA ||
483
+
type == MTK_DISP_MERGE ||
548
484
type == MTK_DISP_OVL ||
549
485
type == MTK_DISP_OVL_2L ||
550
486
type == MTK_DISP_PWM ||
551
487
type == MTK_DISP_RDMA ||
552
488
type == MTK_DPI ||
489
+
type == MTK_DP_INTF ||
553
490
type == MTK_DSI)
554
491
return 0;
555
492
+3
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+3
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
···
23
23
MTK_DISP_CCORR,
24
24
MTK_DISP_COLOR,
25
25
MTK_DISP_DITHER,
26
+
MTK_DISP_DSC,
26
27
MTK_DISP_GAMMA,
28
+
MTK_DISP_MERGE,
27
29
MTK_DISP_MUTEX,
28
30
MTK_DISP_OD,
29
31
MTK_DISP_OVL,
···
36
34
MTK_DISP_UFOE,
37
35
MTK_DISP_WDMA,
38
36
MTK_DPI,
37
+
MTK_DP_INTF,
39
38
MTK_DSI,
40
39
MTK_DDP_COMP_TYPE_MAX,
41
40
};
+161
-23
drivers/gpu/drm/mediatek/mtk_drm_drv.c
+161
-23
drivers/gpu/drm/mediatek/mtk_drm_drv.c
···
4
4
* Author: YT SHEN <yt.shen@mediatek.com>
5
5
*/
6
6
7
+
#include <linux/clk.h>
8
+
#include <linux/clk-provider.h>
7
9
#include <linux/component.h>
8
10
#include <linux/iommu.h>
9
11
#include <linux/module.h>
···
118
116
DDP_COMPONENT_CCORR,
119
117
DDP_COMPONENT_AAL0,
120
118
DDP_COMPONENT_GAMMA,
121
-
DDP_COMPONENT_DITHER,
119
+
DDP_COMPONENT_DITHER0,
122
120
DDP_COMPONENT_RDMA0,
123
121
DDP_COMPONENT_DSI0,
124
122
};
···
150
148
DDP_COMPONENT_CCORR,
151
149
DDP_COMPONENT_AAL0,
152
150
DDP_COMPONENT_GAMMA,
153
-
DDP_COMPONENT_DITHER,
151
+
DDP_COMPONENT_DITHER0,
154
152
DDP_COMPONENT_DSI0,
155
153
};
156
154
···
168
166
DDP_COMPONENT_AAL0,
169
167
DDP_COMPONENT_GAMMA,
170
168
DDP_COMPONENT_POSTMASK0,
171
-
DDP_COMPONENT_DITHER,
169
+
DDP_COMPONENT_DITHER0,
172
170
DDP_COMPONENT_DSI0,
173
171
};
174
172
···
187
185
DDP_COMPONENT_AAL0,
188
186
DDP_COMPONENT_GAMMA,
189
187
DDP_COMPONENT_POSTMASK0,
190
-
DDP_COMPONENT_DITHER,
188
+
DDP_COMPONENT_DITHER0,
191
189
DDP_COMPONENT_DSI0,
192
190
};
193
191
···
195
193
DDP_COMPONENT_OVL_2L2,
196
194
DDP_COMPONENT_RDMA4,
197
195
DDP_COMPONENT_DPI0,
196
+
};
197
+
198
+
static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
199
+
DDP_COMPONENT_OVL0,
200
+
DDP_COMPONENT_RDMA0,
201
+
DDP_COMPONENT_COLOR0,
202
+
DDP_COMPONENT_CCORR,
203
+
DDP_COMPONENT_AAL0,
204
+
DDP_COMPONENT_GAMMA,
205
+
DDP_COMPONENT_DITHER0,
206
+
DDP_COMPONENT_DSC0,
207
+
DDP_COMPONENT_MERGE0,
208
+
DDP_COMPONENT_DP_INTF0,
198
209
};
199
210
200
211
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
···
218
203
.shadow_register = true,
219
204
};
220
205
206
+
static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
207
+
.num_drv_data = 1,
208
+
.drv_data = {
209
+
&mt2701_mmsys_driver_data,
210
+
},
211
+
};
212
+
221
213
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
222
214
.main_path = mt7623_mtk_ddp_main,
223
215
.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
224
216
.ext_path = mt7623_mtk_ddp_ext,
225
217
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
226
218
.shadow_register = true,
219
+
};
220
+
221
+
static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
222
+
.num_drv_data = 1,
223
+
.drv_data = {
224
+
&mt7623_mmsys_driver_data,
225
+
},
227
226
};
228
227
229
228
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
···
249
220
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
250
221
};
251
222
223
+
static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
224
+
.num_drv_data = 1,
225
+
.drv_data = {
226
+
&mt2712_mmsys_driver_data,
227
+
},
228
+
};
229
+
252
230
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
253
231
.main_path = mt8167_mtk_ddp_main,
254
232
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
233
+
};
234
+
235
+
static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
236
+
.num_drv_data = 1,
237
+
.drv_data = {
238
+
&mt8167_mmsys_driver_data,
239
+
},
255
240
};
256
241
257
242
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
···
275
232
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
276
233
};
277
234
235
+
static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
236
+
.num_drv_data = 1,
237
+
.drv_data = {
238
+
&mt8173_mmsys_driver_data,
239
+
},
240
+
};
241
+
278
242
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
279
243
.main_path = mt8183_mtk_ddp_main,
280
244
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
281
245
.ext_path = mt8183_mtk_ddp_ext,
282
246
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
247
+
};
248
+
249
+
static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
250
+
.num_drv_data = 1,
251
+
.drv_data = {
252
+
&mt8183_mmsys_driver_data,
253
+
},
283
254
};
284
255
285
256
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
···
303
246
.ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
304
247
};
305
248
249
+
static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
250
+
.num_drv_data = 1,
251
+
.drv_data = {
252
+
&mt8186_mmsys_driver_data,
253
+
},
254
+
};
255
+
306
256
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
307
257
.main_path = mt8192_mtk_ddp_main,
308
258
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
309
259
.ext_path = mt8192_mtk_ddp_ext,
310
260
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
261
+
};
262
+
263
+
static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
264
+
.num_drv_data = 1,
265
+
.drv_data = {
266
+
&mt8192_mmsys_driver_data,
267
+
},
268
+
};
269
+
270
+
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
271
+
.io_start = 0x1c01a000,
272
+
.main_path = mt8195_mtk_ddp_main,
273
+
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
274
+
};
275
+
276
+
static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
277
+
.io_start = 0x1c100000,
278
+
};
279
+
280
+
static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
281
+
.num_drv_data = 1,
282
+
.drv_data = {
283
+
&mt8195_vdosys0_driver_data,
284
+
&mt8195_vdosys1_driver_data,
285
+
},
311
286
};
312
287
313
288
static int mtk_drm_kms_init(struct drm_device *drm)
···
559
470
.data = (void *)MTK_DISP_DITHER },
560
471
{ .compatible = "mediatek,mt8183-disp-dither",
561
472
.data = (void *)MTK_DISP_DITHER },
473
+
{ .compatible = "mediatek,mt8195-disp-dsc",
474
+
.data = (void *)MTK_DISP_DSC },
562
475
{ .compatible = "mediatek,mt8167-disp-gamma",
563
476
.data = (void *)MTK_DISP_GAMMA, },
564
477
{ .compatible = "mediatek,mt8173-disp-gamma",
565
478
.data = (void *)MTK_DISP_GAMMA, },
566
479
{ .compatible = "mediatek,mt8183-disp-gamma",
567
480
.data = (void *)MTK_DISP_GAMMA, },
481
+
{ .compatible = "mediatek,mt8195-disp-merge",
482
+
.data = (void *)MTK_DISP_MERGE },
568
483
{ .compatible = "mediatek,mt2701-disp-mutex",
569
484
.data = (void *)MTK_DISP_MUTEX },
570
485
{ .compatible = "mediatek,mt2712-disp-mutex",
···
582
489
{ .compatible = "mediatek,mt8186-disp-mutex",
583
490
.data = (void *)MTK_DISP_MUTEX },
584
491
{ .compatible = "mediatek,mt8192-disp-mutex",
492
+
.data = (void *)MTK_DISP_MUTEX },
493
+
{ .compatible = "mediatek,mt8195-disp-mutex",
585
494
.data = (void *)MTK_DISP_MUTEX },
586
495
{ .compatible = "mediatek,mt8173-disp-od",
587
496
.data = (void *)MTK_DISP_OD },
···
617
522
.data = (void *)MTK_DISP_RDMA },
618
523
{ .compatible = "mediatek,mt8183-disp-rdma",
619
524
.data = (void *)MTK_DISP_RDMA },
620
-
{ .compatible = "mediatek,mt8192-disp-rdma",
525
+
{ .compatible = "mediatek,mt8195-disp-rdma",
621
526
.data = (void *)MTK_DISP_RDMA },
622
527
{ .compatible = "mediatek,mt8173-disp-ufoe",
623
528
.data = (void *)MTK_DISP_UFOE },
···
633
538
.data = (void *)MTK_DPI },
634
539
{ .compatible = "mediatek,mt8192-dpi",
635
540
.data = (void *)MTK_DPI },
541
+
{ .compatible = "mediatek,mt8195-dp-intf",
542
+
.data = (void *)MTK_DP_INTF },
636
543
{ .compatible = "mediatek,mt2701-dsi",
637
544
.data = (void *)MTK_DSI },
638
545
{ .compatible = "mediatek,mt8173-dsi",
639
546
.data = (void *)MTK_DSI },
640
547
{ .compatible = "mediatek,mt8183-dsi",
641
548
.data = (void *)MTK_DSI },
549
+
{ .compatible = "mediatek,mt8186-dsi",
550
+
.data = (void *)MTK_DSI },
642
551
{ }
643
552
};
644
553
645
554
static const struct of_device_id mtk_drm_of_ids[] = {
646
555
{ .compatible = "mediatek,mt2701-mmsys",
647
-
.data = &mt2701_mmsys_driver_data},
556
+
.data = &mt2701_mmsys_match_data},
648
557
{ .compatible = "mediatek,mt7623-mmsys",
649
-
.data = &mt7623_mmsys_driver_data},
558
+
.data = &mt7623_mmsys_match_data},
650
559
{ .compatible = "mediatek,mt2712-mmsys",
651
-
.data = &mt2712_mmsys_driver_data},
560
+
.data = &mt2712_mmsys_match_data},
652
561
{ .compatible = "mediatek,mt8167-mmsys",
653
-
.data = &mt8167_mmsys_driver_data},
562
+
.data = &mt8167_mmsys_match_data},
654
563
{ .compatible = "mediatek,mt8173-mmsys",
655
-
.data = &mt8173_mmsys_driver_data},
564
+
.data = &mt8173_mmsys_match_data},
656
565
{ .compatible = "mediatek,mt8183-mmsys",
657
-
.data = &mt8183_mmsys_driver_data},
566
+
.data = &mt8183_mmsys_match_data},
658
567
{ .compatible = "mediatek,mt8186-mmsys",
659
-
.data = &mt8186_mmsys_driver_data},
568
+
.data = &mt8186_mmsys_match_data},
660
569
{ .compatible = "mediatek,mt8192-mmsys",
661
-
.data = &mt8192_mmsys_driver_data},
570
+
.data = &mt8192_mmsys_match_data},
571
+
{ .compatible = "mediatek,mt8195-mmsys",
572
+
.data = &mt8195_mmsys_match_data},
662
573
{ }
663
574
};
664
575
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
576
+
577
+
static int mtk_drm_find_match_data(struct device *dev,
578
+
const struct mtk_mmsys_match_data *match_data)
579
+
{
580
+
int i;
581
+
struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
582
+
struct resource *res;
583
+
584
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
585
+
if (!res) {
586
+
dev_err(dev, "failed to get parent resource\n");
587
+
return -EINVAL;
588
+
}
589
+
590
+
for (i = 0; i < match_data->num_drv_data; i++)
591
+
if (match_data->drv_data[i]->io_start == res->start)
592
+
return i;
593
+
594
+
return -EINVAL;
595
+
}
665
596
666
597
static int mtk_drm_probe(struct platform_device *pdev)
667
598
{
668
599
struct device *dev = &pdev->dev;
669
600
struct device_node *phandle = dev->parent->of_node;
670
601
const struct of_device_id *of_id;
602
+
const struct mtk_mmsys_match_data *match_data;
671
603
struct mtk_drm_private *private;
672
604
struct device_node *node;
673
605
struct component_match *match = NULL;
···
715
593
if (!of_id)
716
594
return -ENODEV;
717
595
718
-
private->data = of_id->data;
596
+
match_data = of_id->data;
597
+
if (match_data->num_drv_data > 1) {
598
+
/* This SoC has multiple mmsys channels */
599
+
ret = mtk_drm_find_match_data(dev, match_data);
600
+
if (ret < 0) {
601
+
dev_err(dev, "Couldn't get match driver data\n");
602
+
return ret;
603
+
}
604
+
private->data = match_data->drv_data[ret];
605
+
} else {
606
+
dev_dbg(dev, "Using single mmsys channel\n");
607
+
private->data = match_data->drv_data[0];
608
+
}
719
609
720
610
/* Iterate over sibling DISP function blocks */
721
611
for_each_child_of_node(phandle->parent, node) {
···
762
628
private->comp_node[comp_id] = of_node_get(node);
763
629
764
630
/*
765
-
* Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
631
+
* Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
766
632
* blocks have separate component platform drivers and initialize their own
767
633
* DDP component structure. The others are initialized here.
768
634
*/
···
770
636
comp_type == MTK_DISP_CCORR ||
771
637
comp_type == MTK_DISP_COLOR ||
772
638
comp_type == MTK_DISP_GAMMA ||
639
+
comp_type == MTK_DISP_MERGE ||
773
640
comp_type == MTK_DISP_OVL ||
774
641
comp_type == MTK_DISP_OVL_2L ||
775
642
comp_type == MTK_DISP_RDMA ||
643
+
comp_type == MTK_DP_INTF ||
776
644
comp_type == MTK_DPI ||
777
645
comp_type == MTK_DSI) {
778
646
dev_info(dev, "Adding component match for %pOF\n",
···
829
693
return 0;
830
694
}
831
695
832
-
#ifdef CONFIG_PM_SLEEP
833
-
static int mtk_drm_sys_suspend(struct device *dev)
696
+
static int mtk_drm_sys_prepare(struct device *dev)
834
697
{
835
698
struct mtk_drm_private *private = dev_get_drvdata(dev);
836
699
struct drm_device *drm = private->drm;
···
840
705
return ret;
841
706
}
842
707
843
-
static int mtk_drm_sys_resume(struct device *dev)
708
+
static void mtk_drm_sys_complete(struct device *dev)
844
709
{
845
710
struct mtk_drm_private *private = dev_get_drvdata(dev);
846
711
struct drm_device *drm = private->drm;
847
712
int ret;
848
713
849
714
ret = drm_mode_config_helper_resume(drm);
850
-
851
-
return ret;
715
+
if (ret)
716
+
dev_err(dev, "Failed to resume\n");
852
717
}
853
-
#endif
854
718
855
-
static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
856
-
mtk_drm_sys_resume);
719
+
static const struct dev_pm_ops mtk_drm_pm_ops = {
720
+
.prepare = mtk_drm_sys_prepare,
721
+
.complete = mtk_drm_sys_complete,
722
+
};
857
723
858
724
static struct platform_driver mtk_drm_platform_driver = {
859
725
.probe = mtk_drm_probe,
···
870
734
&mtk_disp_ccorr_driver,
871
735
&mtk_disp_color_driver,
872
736
&mtk_disp_gamma_driver,
737
+
&mtk_disp_merge_driver,
873
738
&mtk_disp_ovl_driver,
874
739
&mtk_disp_rdma_driver,
875
740
&mtk_dpi_driver,
876
741
&mtk_drm_platform_driver,
877
742
&mtk_dsi_driver,
743
+
&mtk_mdp_rdma_driver,
878
744
};
879
745
880
746
static int __init mtk_drm_init(void)
+8
drivers/gpu/drm/mediatek/mtk_drm_drv.h
+8
drivers/gpu/drm/mediatek/mtk_drm_drv.h
···
21
21
struct regmap;
22
22
23
23
struct mtk_mmsys_driver_data {
24
+
const resource_size_t io_start;
24
25
const enum mtk_ddp_comp_id *main_path;
25
26
unsigned int main_len;
26
27
const enum mtk_ddp_comp_id *ext_path;
···
30
29
unsigned int third_len;
31
30
32
31
bool shadow_register;
32
+
};
33
+
34
+
struct mtk_mmsys_match_data {
35
+
unsigned short num_drv_data;
36
+
const struct mtk_mmsys_driver_data *drv_data[];
33
37
};
34
38
35
39
struct mtk_drm_private {
···
56
50
extern struct platform_driver mtk_disp_ccorr_driver;
57
51
extern struct platform_driver mtk_disp_color_driver;
58
52
extern struct platform_driver mtk_disp_gamma_driver;
53
+
extern struct platform_driver mtk_disp_merge_driver;
59
54
extern struct platform_driver mtk_disp_ovl_driver;
60
55
extern struct platform_driver mtk_disp_rdma_driver;
61
56
extern struct platform_driver mtk_dpi_driver;
62
57
extern struct platform_driver mtk_dsi_driver;
58
+
extern struct platform_driver mtk_mdp_rdma_driver;
63
59
64
60
#endif /* MTK_DRM_DRV_H */
+1
drivers/gpu/drm/mediatek/mtk_drm_plane.c
+1
drivers/gpu/drm/mediatek/mtk_drm_plane.c
···
140
140
mtk_plane_state->pending.width = drm_rect_width(&new_state->dst);
141
141
mtk_plane_state->pending.height = drm_rect_height(&new_state->dst);
142
142
mtk_plane_state->pending.rotation = new_state->rotation;
143
+
mtk_plane_state->pending.color_encoding = new_state->color_encoding;
143
144
}
144
145
145
146
static void mtk_plane_atomic_async_update(struct drm_plane *plane,
+1
drivers/gpu/drm/mediatek/mtk_drm_plane.h
+1
drivers/gpu/drm/mediatek/mtk_drm_plane.h
+71
-30
drivers/gpu/drm/mediatek/mtk_dsi.c
+71
-30
drivers/gpu/drm/mediatek/mtk_dsi.c
···
203
203
struct mtk_phy_timing phy_timing;
204
204
int refcount;
205
205
bool enabled;
206
+
bool lanes_ready;
206
207
u32 irq_data;
207
208
wait_queue_head_t irq_wait_queue;
208
209
const struct mtk_dsi_driver_data *driver_data;
···
662
661
mtk_dsi_reset_engine(dsi);
663
662
mtk_dsi_phy_timconfig(dsi);
664
663
665
-
mtk_dsi_rxtx_control(dsi);
666
-
usleep_range(30, 100);
667
-
mtk_dsi_reset_dphy(dsi);
668
664
mtk_dsi_ps_control_vact(dsi);
669
665
mtk_dsi_set_vm_cmd(dsi);
670
666
mtk_dsi_config_vdo_timing(dsi);
671
667
mtk_dsi_set_interrupt_enable(dsi);
672
-
673
-
mtk_dsi_clk_ulp_mode_leave(dsi);
674
-
mtk_dsi_lane0_ulp_mode_leave(dsi);
675
-
mtk_dsi_clk_hs_mode(dsi, 0);
676
668
677
669
return 0;
678
670
err_disable_engine_clk:
···
685
691
if (--dsi->refcount != 0)
686
692
return;
687
693
688
-
/*
689
-
* mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
690
-
* mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
691
-
* which needs irq for vblank, and mtk_dsi_stop() will disable irq.
692
-
* mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
693
-
* after dsi is fully set.
694
-
*/
695
-
mtk_dsi_stop(dsi);
696
-
697
-
mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
698
694
mtk_dsi_reset_engine(dsi);
699
695
mtk_dsi_lane0_ulp_mode_enter(dsi);
700
696
mtk_dsi_clk_ulp_mode_enter(dsi);
697
+
/* set the lane number as 0 to pull down mipi */
698
+
writel(0, dsi->regs + DSI_TXRX_CTRL);
701
699
702
700
mtk_dsi_disable(dsi);
703
701
···
697
711
clk_disable_unprepare(dsi->digital_clk);
698
712
699
713
phy_power_off(dsi->phy);
714
+
715
+
dsi->lanes_ready = false;
716
+
}
717
+
718
+
static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
719
+
{
720
+
if (!dsi->lanes_ready) {
721
+
dsi->lanes_ready = true;
722
+
mtk_dsi_rxtx_control(dsi);
723
+
usleep_range(30, 100);
724
+
mtk_dsi_reset_dphy(dsi);
725
+
mtk_dsi_clk_ulp_mode_leave(dsi);
726
+
mtk_dsi_lane0_ulp_mode_leave(dsi);
727
+
mtk_dsi_clk_hs_mode(dsi, 0);
728
+
msleep(20);
729
+
/* The reaction time after pulling up the mipi signal for dsi_rx */
730
+
}
700
731
}
701
732
702
733
static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
703
734
{
704
-
int ret;
705
-
706
735
if (dsi->enabled)
707
736
return;
708
737
709
-
ret = mtk_dsi_poweron(dsi);
710
-
if (ret < 0) {
711
-
DRM_ERROR("failed to power on dsi\n");
712
-
return;
713
-
}
714
-
738
+
mtk_dsi_lane_ready(dsi);
715
739
mtk_dsi_set_mode(dsi);
716
740
mtk_dsi_clk_hs_mode(dsi, 1);
717
741
···
735
739
if (!dsi->enabled)
736
740
return;
737
741
738
-
mtk_dsi_poweroff(dsi);
742
+
/*
743
+
* mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
744
+
* mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
745
+
* which needs irq for vblank, and mtk_dsi_stop() will disable irq.
746
+
* mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
747
+
* after dsi is fully set.
748
+
*/
749
+
mtk_dsi_stop(dsi);
750
+
751
+
mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
739
752
740
753
dsi->enabled = false;
741
754
}
···
768
763
drm_display_mode_to_videomode(adjusted, &dsi->vm);
769
764
}
770
765
771
-
static void mtk_dsi_bridge_disable(struct drm_bridge *bridge)
766
+
static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
767
+
struct drm_bridge_state *old_bridge_state)
772
768
{
773
769
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
774
770
775
771
mtk_output_dsi_disable(dsi);
776
772
}
777
773
778
-
static void mtk_dsi_bridge_enable(struct drm_bridge *bridge)
774
+
static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
775
+
struct drm_bridge_state *old_bridge_state)
779
776
{
780
777
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
778
+
779
+
if (dsi->refcount == 0)
780
+
return;
781
781
782
782
mtk_output_dsi_enable(dsi);
783
783
}
784
784
785
+
static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
786
+
struct drm_bridge_state *old_bridge_state)
787
+
{
788
+
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
789
+
int ret;
790
+
791
+
ret = mtk_dsi_poweron(dsi);
792
+
if (ret < 0)
793
+
DRM_ERROR("failed to power on dsi\n");
794
+
}
795
+
796
+
static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
797
+
struct drm_bridge_state *old_bridge_state)
798
+
{
799
+
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
800
+
801
+
mtk_dsi_poweroff(dsi);
802
+
}
803
+
785
804
static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
786
805
.attach = mtk_dsi_bridge_attach,
787
-
.disable = mtk_dsi_bridge_disable,
788
-
.enable = mtk_dsi_bridge_enable,
806
+
.atomic_disable = mtk_dsi_bridge_atomic_disable,
807
+
.atomic_enable = mtk_dsi_bridge_atomic_enable,
808
+
.atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
809
+
.atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
789
810
.mode_set = mtk_dsi_bridge_mode_set,
790
811
};
791
812
···
1031
1000
if (MTK_DSI_HOST_IS_READ(msg->type))
1032
1001
irq_flag |= LPRX_RD_RDY_INT_FLAG;
1033
1002
1003
+
mtk_dsi_lane_ready(dsi);
1004
+
1034
1005
ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1035
1006
if (ret)
1036
1007
goto restore_dsi_mode;
···
1199
1166
.has_size_ctl = true,
1200
1167
};
1201
1168
1169
+
static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
1170
+
.reg_cmdq_off = 0xd00,
1171
+
.has_shadow_ctl = true,
1172
+
.has_size_ctl = true,
1173
+
};
1174
+
1202
1175
static const struct of_device_id mtk_dsi_of_match[] = {
1203
1176
{ .compatible = "mediatek,mt2701-dsi",
1204
1177
.data = &mt2701_dsi_driver_data },
···
1212
1173
.data = &mt8173_dsi_driver_data },
1213
1174
{ .compatible = "mediatek,mt8183-dsi",
1214
1175
.data = &mt8183_dsi_driver_data },
1176
+
{ .compatible = "mediatek,mt8186-dsi",
1177
+
.data = &mt8186_dsi_driver_data },
1215
1178
{ },
1216
1179
};
1217
1180
MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
+315
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
+315
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
*/
5
+
6
+
#include <drm/drm_fourcc.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/component.h>
9
+
#include <linux/of_address.h>
10
+
#include <linux/of_device.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/pm_runtime.h>
13
+
#include <linux/soc/mediatek/mtk-cmdq.h>
14
+
15
+
#include "mtk_disp_drv.h"
16
+
#include "mtk_drm_drv.h"
17
+
#include "mtk_mdp_rdma.h"
18
+
19
+
#define MDP_RDMA_EN 0x000
20
+
#define FLD_ROT_ENABLE BIT(0)
21
+
#define MDP_RDMA_RESET 0x008
22
+
#define MDP_RDMA_CON 0x020
23
+
#define FLD_OUTPUT_10B BIT(5)
24
+
#define FLD_SIMPLE_MODE BIT(4)
25
+
#define MDP_RDMA_GMCIF_CON 0x028
26
+
#define FLD_COMMAND_DIV BIT(0)
27
+
#define FLD_EXT_PREULTRA_EN BIT(3)
28
+
#define FLD_RD_REQ_TYPE GENMASK(7, 4)
29
+
#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
30
+
#define FLD_ULTRA_EN GENMASK(13, 12)
31
+
#define VAL_ULTRA_EN_ENABLE 1
32
+
#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
33
+
#define VAL_PRE_ULTRA_EN_ENABLE 1
34
+
#define FLD_EXT_ULTRA_EN BIT(18)
35
+
#define MDP_RDMA_SRC_CON 0x030
36
+
#define FLD_OUTPUT_ARGB BIT(25)
37
+
#define FLD_BIT_NUMBER GENMASK(19, 18)
38
+
#define FLD_SWAP BIT(14)
39
+
#define FLD_UNIFORM_CONFIG BIT(17)
40
+
#define RDMA_INPUT_10BIT BIT(18)
41
+
#define FLD_SRC_FORMAT GENMASK(3, 0)
42
+
#define MDP_RDMA_COMP_CON 0x038
43
+
#define FLD_AFBC_EN BIT(22)
44
+
#define FLD_AFBC_YUV_TRANSFORM BIT(21)
45
+
#define FLD_UFBDC_EN BIT(12)
46
+
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
47
+
#define FLD_MF_BKGD_WB GENMASK(22, 0)
48
+
#define MDP_RDMA_MF_SRC_SIZE 0x070
49
+
#define FLD_MF_SRC_H GENMASK(30, 16)
50
+
#define FLD_MF_SRC_W GENMASK(14, 0)
51
+
#define MDP_RDMA_MF_CLIP_SIZE 0x078
52
+
#define FLD_MF_CLIP_H GENMASK(30, 16)
53
+
#define FLD_MF_CLIP_W GENMASK(14, 0)
54
+
#define MDP_RDMA_SRC_OFFSET_0 0x118
55
+
#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
56
+
#define MDP_RDMA_TRANSFORM_0 0x200
57
+
#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
58
+
#define FLD_TRANS_EN BIT(16)
59
+
#define MDP_RDMA_SRC_BASE_0 0xf00
60
+
#define FLD_SRC_BASE_0 GENMASK(31, 0)
61
+
62
+
#define RDMA_CSC_FULL709_TO_RGB 5
63
+
#define RDMA_CSC_BT601_TO_RGB 6
64
+
65
+
enum rdma_format {
66
+
RDMA_INPUT_FORMAT_RGB565 = 0,
67
+
RDMA_INPUT_FORMAT_RGB888 = 1,
68
+
RDMA_INPUT_FORMAT_RGBA8888 = 2,
69
+
RDMA_INPUT_FORMAT_ARGB8888 = 3,
70
+
RDMA_INPUT_FORMAT_UYVY = 4,
71
+
RDMA_INPUT_FORMAT_YUY2 = 5,
72
+
RDMA_INPUT_FORMAT_Y8 = 7,
73
+
RDMA_INPUT_FORMAT_YV12 = 8,
74
+
RDMA_INPUT_FORMAT_UYVY_3PL = 9,
75
+
RDMA_INPUT_FORMAT_NV12 = 12,
76
+
RDMA_INPUT_FORMAT_UYVY_2PL = 13,
77
+
RDMA_INPUT_FORMAT_Y410 = 14
78
+
};
79
+
80
+
struct mtk_mdp_rdma {
81
+
void __iomem *regs;
82
+
struct clk *clk;
83
+
struct cmdq_client_reg cmdq_reg;
84
+
};
85
+
86
+
static unsigned int rdma_fmt_convert(unsigned int fmt)
87
+
{
88
+
switch (fmt) {
89
+
default:
90
+
case DRM_FORMAT_RGB565:
91
+
return RDMA_INPUT_FORMAT_RGB565;
92
+
case DRM_FORMAT_BGR565:
93
+
return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
94
+
case DRM_FORMAT_RGB888:
95
+
return RDMA_INPUT_FORMAT_RGB888;
96
+
case DRM_FORMAT_BGR888:
97
+
return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
98
+
case DRM_FORMAT_RGBX8888:
99
+
case DRM_FORMAT_RGBA8888:
100
+
return RDMA_INPUT_FORMAT_ARGB8888;
101
+
case DRM_FORMAT_BGRX8888:
102
+
case DRM_FORMAT_BGRA8888:
103
+
return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
104
+
case DRM_FORMAT_XRGB8888:
105
+
case DRM_FORMAT_ARGB8888:
106
+
return RDMA_INPUT_FORMAT_RGBA8888;
107
+
case DRM_FORMAT_XBGR8888:
108
+
case DRM_FORMAT_ABGR8888:
109
+
return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
110
+
case DRM_FORMAT_ABGR2101010:
111
+
return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
112
+
case DRM_FORMAT_ARGB2101010:
113
+
return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
114
+
case DRM_FORMAT_RGBA1010102:
115
+
return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
116
+
case DRM_FORMAT_BGRA1010102:
117
+
return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
118
+
case DRM_FORMAT_UYVY:
119
+
return RDMA_INPUT_FORMAT_UYVY;
120
+
case DRM_FORMAT_YUYV:
121
+
return RDMA_INPUT_FORMAT_YUY2;
122
+
}
123
+
}
124
+
125
+
static unsigned int rdma_color_convert(unsigned int color_encoding)
126
+
{
127
+
switch (color_encoding) {
128
+
default:
129
+
case DRM_COLOR_YCBCR_BT709:
130
+
return RDMA_CSC_FULL709_TO_RGB;
131
+
case DRM_COLOR_YCBCR_BT601:
132
+
return RDMA_CSC_BT601_TO_RGB;
133
+
}
134
+
}
135
+
136
+
static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
137
+
{
138
+
struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
139
+
140
+
mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
141
+
VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
142
+
FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
143
+
priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
144
+
FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
145
+
FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
146
+
}
147
+
148
+
void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
149
+
{
150
+
struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
151
+
152
+
mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
153
+
priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
154
+
}
155
+
156
+
void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
157
+
{
158
+
struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
159
+
160
+
mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
161
+
priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
162
+
mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
163
+
mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
164
+
}
165
+
166
+
void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
167
+
struct cmdq_pkt *cmdq_pkt)
168
+
{
169
+
struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
170
+
const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
171
+
bool csc_enable = fmt_info->is_yuv ? true : false;
172
+
unsigned int src_pitch_y = cfg->pitch;
173
+
unsigned int offset_y = 0;
174
+
175
+
mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
176
+
177
+
mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
178
+
MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
179
+
mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
180
+
MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
181
+
182
+
if (!csc_enable && fmt_info->has_alpha)
183
+
mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
184
+
priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
185
+
else
186
+
mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
187
+
MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
188
+
189
+
mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
190
+
MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
191
+
192
+
mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
193
+
MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
194
+
195
+
mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
196
+
FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
197
+
mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
198
+
MDP_RDMA_CON, FLD_OUTPUT_10B);
199
+
mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
200
+
MDP_RDMA_CON, FLD_SIMPLE_MODE);
201
+
if (csc_enable)
202
+
mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg->color_encoding) << 23,
203
+
&priv->cmdq_reg, priv->regs, MDP_RDMA_TRANSFORM_0,
204
+
FLD_INT_MATRIX_SEL);
205
+
mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
206
+
MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
207
+
208
+
offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
209
+
210
+
mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
211
+
MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
212
+
mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
213
+
MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
214
+
mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
215
+
MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
216
+
mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
217
+
MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
218
+
mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
219
+
MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
220
+
}
221
+
222
+
int mtk_mdp_rdma_clk_enable(struct device *dev)
223
+
{
224
+
struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
225
+
226
+
clk_prepare_enable(rdma->clk);
227
+
return 0;
228
+
}
229
+
230
+
void mtk_mdp_rdma_clk_disable(struct device *dev)
231
+
{
232
+
struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
233
+
234
+
clk_disable_unprepare(rdma->clk);
235
+
}
236
+
237
+
static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
238
+
void *data)
239
+
{
240
+
return 0;
241
+
}
242
+
243
+
static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
244
+
void *data)
245
+
{
246
+
}
247
+
248
+
static const struct component_ops mtk_mdp_rdma_component_ops = {
249
+
.bind = mtk_mdp_rdma_bind,
250
+
.unbind = mtk_mdp_rdma_unbind,
251
+
};
252
+
253
+
static int mtk_mdp_rdma_probe(struct platform_device *pdev)
254
+
{
255
+
struct device *dev = &pdev->dev;
256
+
struct resource *res;
257
+
struct mtk_mdp_rdma *priv;
258
+
int ret = 0;
259
+
260
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
261
+
if (!priv)
262
+
return -ENOMEM;
263
+
264
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265
+
priv->regs = devm_ioremap_resource(dev, res);
266
+
if (IS_ERR(priv->regs)) {
267
+
dev_err(dev, "failed to ioremap rdma\n");
268
+
return PTR_ERR(priv->regs);
269
+
}
270
+
271
+
priv->clk = devm_clk_get(dev, NULL);
272
+
if (IS_ERR(priv->clk)) {
273
+
dev_err(dev, "failed to get rdma clk\n");
274
+
return PTR_ERR(priv->clk);
275
+
}
276
+
277
+
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
278
+
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
279
+
if (ret)
280
+
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
281
+
#endif
282
+
platform_set_drvdata(pdev, priv);
283
+
284
+
pm_runtime_enable(dev);
285
+
286
+
ret = component_add(dev, &mtk_mdp_rdma_component_ops);
287
+
if (ret != 0) {
288
+
pm_runtime_disable(dev);
289
+
dev_err(dev, "Failed to add component: %d\n", ret);
290
+
}
291
+
return ret;
292
+
}
293
+
294
+
static int mtk_mdp_rdma_remove(struct platform_device *pdev)
295
+
{
296
+
component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
297
+
pm_runtime_disable(&pdev->dev);
298
+
return 0;
299
+
}
300
+
301
+
static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
302
+
{ .compatible = "mediatek,mt8195-vdo1-rdma", },
303
+
{},
304
+
};
305
+
MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
306
+
307
+
struct platform_driver mtk_mdp_rdma_driver = {
308
+
.probe = mtk_mdp_rdma_probe,
309
+
.remove = mtk_mdp_rdma_remove,
310
+
.driver = {
311
+
.name = "mediatek-mdp-rdma",
312
+
.owner = THIS_MODULE,
313
+
.of_match_table = mtk_mdp_rdma_driver_dt_match,
314
+
},
315
+
};
+20
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
+20
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
*/
5
+
6
+
#ifndef __MTK_MDP_RDMA_H__
7
+
#define __MTK_MDP_RDMA_H__
8
+
9
+
struct mtk_mdp_rdma_cfg {
10
+
unsigned int pitch;
11
+
unsigned int addr0;
12
+
unsigned int width;
13
+
unsigned int height;
14
+
unsigned int x_left;
15
+
unsigned int y_top;
16
+
int fmt;
17
+
int color_encoding;
18
+
};
19
+
20
+
#endif // __MTK_MDP_RDMA_H__