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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
riscv: dts: starfive: jh7100: Add PWM node and pins configuration
Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 1 board.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
authored by
William Qiu
and committed by
Conor Dooley
5e598b99
25290858
+33
+24
arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+24
arch/riscv/boot/dts/starfive/jh7100-common.dtsi
···
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};
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};
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+
pwm_pins: pwm-0 {
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pwm-pins {
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pinmux = <GPIOMUX(7,
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GPO_PWM_PAD_OUT_BIT0,
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GPO_PWM_PAD_OE_N_BIT0,
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GPI_NONE)>,
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<GPIOMUX(5,
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GPO_PWM_PAD_OUT_BIT1,
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GPO_PWM_PAD_OE_N_BIT1,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <35>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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+
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sdio0_pins: sdio0-0 {
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clk-pins {
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pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
···
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&osc_aud {
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clock-frequency = <27000000>;
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&sdio0 {
+9
arch/riscv/boot/dts/starfive/jh7100.dtsi
+9
arch/riscv/boot/dts/starfive/jh7100.dtsi
···
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<&rstgen JH7100_RSTN_WDT>;
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};
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+
pwm: pwm@12490000 {
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compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
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reg = <0x0 0x12490000 0x0 0x10000>;
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clocks = <&clkgen JH7100_CLK_PWM_APB>;
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resets = <&rstgen JH7100_RSTN_PWM_APB>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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+
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sfctemp: temperature-sensor@124a0000 {
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compatible = "starfive,jh7100-temp";
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reg = <0x0 0x124a0000 0x0 0x10000>;