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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: microchip: mpfs: simplify control reg access
The control reg addresses are known when the clocks are registered, so
we can, instead of assigning a base pointer to the structs, assign the
control reg addresses directly. Accordingly, remove the interim
variables used during reads/writes to those registers.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-11-conor.dooley@microchip.com
authored by
Conor Dooley
and committed by
Claudiu Beznea
5fa27b77
52fe6b52
+17
-25
+17
-25
drivers/clk/microchip/clk-mpfs.c
+17
-25
drivers/clk/microchip/clk-mpfs.c
···
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#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
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struct mpfs_cfg_clock {
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void __iomem *reg;
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const struct clk_div_table *table;
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u8 shift;
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u8 width;
···
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struct mpfs_cfg_hw_clock {
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struct mpfs_cfg_clock cfg;
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void __iomem *sys_base;
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struct clk_hw hw;
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struct clk_init_data init;
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unsigned int id;
···
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#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
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struct mpfs_periph_clock {
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void __iomem *reg;
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u8 shift;
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};
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struct mpfs_periph_hw_clock {
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struct mpfs_periph_clock periph;
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void __iomem *sys_base;
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struct clk_hw hw;
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unsigned int id;
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};
···
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static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
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unsigned int num_clks, struct mpfs_clock_data *data)
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{
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void __iomem *base = data->msspll_base;
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unsigned int i;
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int ret;
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for (i = 0; i < num_clks; i++) {
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struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
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ret = mpfs_clk_register_msspll(dev, msspll_hw, base);
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ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
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CLK_MSSPLL);
···
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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void __iomem *base_addr = cfg_hw->sys_base;
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u32 val;
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val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift;
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val = readl_relaxed(cfg->reg) >> cfg->shift;
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val &= clk_div_mask(cfg->width);
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return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
···
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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void __iomem *base_addr = cfg_hw->sys_base;
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unsigned long flags;
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u32 val;
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int divider_setting;
···
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return divider_setting;
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spin_lock_irqsave(&mpfs_clk_lock, flags);
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val = readl_relaxed(base_addr + cfg_hw->reg_offset);
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val = readl_relaxed(cfg->reg);
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val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
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val |= divider_setting << cfg->shift;
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writel_relaxed(val, base_addr + cfg_hw->reg_offset);
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writel_relaxed(val, cfg->reg);
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spin_unlock_irqrestore(&mpfs_clk_lock, flags);
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···
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};
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static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw,
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void __iomem *sys_base)
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void __iomem *base)
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{
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cfg_hw->sys_base = sys_base;
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cfg_hw->cfg.reg = base + cfg_hw->reg_offset;
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return devm_clk_hw_register(dev, &cfg_hw->hw);
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}
···
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static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
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unsigned int num_clks, struct mpfs_clock_data *data)
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{
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void __iomem *sys_base = data->base;
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unsigned int i, id;
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int ret;
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for (i = 0; i < num_clks; i++) {
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struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
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ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
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ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
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cfg_hw->id);
···
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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struct mpfs_periph_clock *periph = &periph_hw->periph;
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void __iomem *base_addr = periph_hw->sys_base;
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u32 reg, val;
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unsigned long flags;
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spin_lock_irqsave(&mpfs_clk_lock, flags);
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reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
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reg = readl_relaxed(periph->reg);
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val = reg | (1u << periph->shift);
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writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
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writel_relaxed(val, periph->reg);
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spin_unlock_irqrestore(&mpfs_clk_lock, flags);
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···
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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struct mpfs_periph_clock *periph = &periph_hw->periph;
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void __iomem *base_addr = periph_hw->sys_base;
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u32 reg, val;
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unsigned long flags;
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spin_lock_irqsave(&mpfs_clk_lock, flags);
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reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
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reg = readl_relaxed(periph->reg);
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val = reg & ~(1u << periph->shift);
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writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
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writel_relaxed(val, periph->reg);
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spin_unlock_irqrestore(&mpfs_clk_lock, flags);
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}
···
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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struct mpfs_periph_clock *periph = &periph_hw->periph;
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void __iomem *base_addr = periph_hw->sys_base;
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u32 reg;
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reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
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reg = readl_relaxed(periph->reg);
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if (reg & (1u << periph->shift))
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return 1;
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···
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};
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static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw,
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void __iomem *sys_base)
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void __iomem *base)
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{
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periph_hw->sys_base = sys_base;
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periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR;
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return devm_clk_hw_register(dev, &periph_hw->hw);
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}
···
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static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
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int num_clks, struct mpfs_clock_data *data)
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{
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void __iomem *sys_base = data->base;
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unsigned int i, id;
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int ret;
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for (i = 0; i < num_clks; i++) {
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struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
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ret = mpfs_clk_register_periph(dev, periph_hw, sys_base);
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ret = mpfs_clk_register_periph(dev, periph_hw, data->base);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
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periph_hw->id);