Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Thomas Gleixner:
"Two fixes for perf x86 hardware implementations:
- Restrict the period on Nehalem machines to prevent perf from
hogging the CPU
- Prevent the AMD IBS driver from overwriting the hardwre controlled
and pre-seeded reserved bits (0-6) in the count register which
caused a sample bias for dispatched micro-ops"
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/amd/ibs: Fix sample bias for dispatched micro-ops
perf/x86/intel: Restrict period on Nehalem
+24
-7
+10
-3
arch/x86/events/amd/ibs.c
+10
-3
arch/x86/events/amd/ibs.c
···
661
661
662
662
throttle = perf_event_overflow(event, &data, ®s);
663
663
out:
664
-
if (throttle)
664
+
if (throttle) {
665
665
perf_ibs_stop(event, 0);
666
-
else
667
-
perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
666
+
} else {
667
+
period >>= 4;
668
+
669
+
if ((ibs_caps & IBS_CAPS_RDWROPCNT) &&
670
+
(*config & IBS_OP_CNT_CTL))
671
+
period |= *config & IBS_OP_CUR_CNT_RAND;
672
+
673
+
perf_ibs_enable_event(perf_ibs, hwc, period);
674
+
}
668
675
669
676
perf_event_update_userpage(event);
670
677
+6
arch/x86/events/intel/core.c
+6
arch/x86/events/intel/core.c
···
3572
3572
return left;
3573
3573
}
3574
3574
3575
+
static u64 nhm_limit_period(struct perf_event *event, u64 left)
3576
+
{
3577
+
return max(left, 32ULL);
3578
+
}
3579
+
3575
3580
PMU_FORMAT_ATTR(event, "config:0-7" );
3576
3581
PMU_FORMAT_ATTR(umask, "config:8-15" );
3577
3582
PMU_FORMAT_ATTR(edge, "config:18" );
···
4611
4606
x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
4612
4607
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4613
4608
x86_pmu.extra_regs = intel_nehalem_extra_regs;
4609
+
x86_pmu.limit_period = nhm_limit_period;
4614
4610
4615
4611
mem_attr = nhm_mem_events_attrs;
4616
4612
+8
-4
arch/x86/include/asm/perf_event.h
+8
-4
arch/x86/include/asm/perf_event.h
···
252
252
#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
253
253
#define IBSCTL_LVT_OFFSET_MASK 0x0F
254
254
255
-
/* ibs fetch bits/masks */
255
+
/* IBS fetch bits/masks */
256
256
#define IBS_FETCH_RAND_EN (1ULL<<57)
257
257
#define IBS_FETCH_VAL (1ULL<<49)
258
258
#define IBS_FETCH_ENABLE (1ULL<<48)
259
259
#define IBS_FETCH_CNT 0xFFFF0000ULL
260
260
#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
261
261
262
-
/* ibs op bits/masks */
263
-
/* lower 4 bits of the current count are ignored: */
264
-
#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
262
+
/*
263
+
* IBS op bits/masks
264
+
* The lower 7 bits of the current count are random bits
265
+
* preloaded by hardware and ignored in software
266
+
*/
267
+
#define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
268
+
#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
265
269
#define IBS_OP_CNT_CTL (1ULL<<19)
266
270
#define IBS_OP_VAL (1ULL<<18)
267
271
#define IBS_OP_ENABLE (1ULL<<17)