Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"The big change this release has been some excellent work from Lukas
Wunner which closes a bunch of holes in the cleanup paths for drivers,
mainly introduced as a result of devm conversions causing bad
interactions with the support SPI has for allocating the bus and
driver data together.
Together with some of the other work done it feels like we've turned
the corner on several long standing pain points with the API.
Summary:
- Many cleanups around probe/remove and error handling from Lukas
Wunner and Uwe Kleine-König, and further fixes around PM from Zhang
Qilong.
- Provide a mask for which bits of the mode can safely be configured
by drivers and use that to fix an issue with the ADS7846 driver.
- Documentation of the expected interactions between SPI and GPIO
level chip select polarity configuration from H. Nikolaus Schaller,
hopefully we're pretty much at the end of sorting out the
interactions there. Thanks to Nikolaus, Sven Van Asbroeck and Linus
Walleij for this.
- DMA support for Allwinner sun6i controllers.
- Support for Canaan K210 Designware implementations and Intel Adler
Lake"
* tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (69 commits)
spi: dt-bindings: clarify CS behavior for spi-cs-high and gpio descriptors
spi: Limit the spi device max speed to controller's max speed
spi: spi-geni-qcom: Use the new method of gpio CS control
platform/chrome: cros_ec_spi: Drop bits_per_word assignment
platform/chrome: cros_ec_spi: Don't overwrite spi::mode
spi: dw: Add support for the Canaan K210 SoC SPI
spi: dw: Add support for 32-bits max xfer size
dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller
spi: Update DT binding docs to support SiFive FU740 SoC
spi: atmel-quadspi: Fix use-after-free on unbind
spi: npcm-fiu: Disable clock in probe error path
spi: ar934x: Don't leak SPI master in probe error path
spi: mt7621: Don't leak SPI master in probe error path
spi: mt7621: Disable clock in probe error path
media: netup_unidvb: Don't leak SPI master in probe error path
spi: sc18is602: Don't leak SPI master in probe error path
spi: rb4xx: Don't leak SPI master in probe error path
spi: gpio: Don't leak SPI master in probe error path
spi: spi-mtk-nor: Don't leak SPI master in probe error path
spi: mxic: Don't leak SPI master in probe error path
...
+482
-239
+2
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+2
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+27
Documentation/devicetree/bindings/spi/spi-controller.yaml
+27
Documentation/devicetree/bindings/spi/spi-controller.yaml
···
42
42
cs2 : &gpio1 1 0
43
43
cs3 : &gpio1 2 0
44
44
45
+
The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
46
+
or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
47
+
48
+
There is a special rule set for combining the second flag of an
49
+
cs-gpio with the optional spi-cs-high flag for SPI slaves.
50
+
51
+
Each table entry defines how the CS pin is to be physically
52
+
driven (not considering potential gpio inversions by pinmux):
53
+
54
+
device node | cs-gpio | CS pin state active | Note
55
+
================+===============+=====================+=====
56
+
spi-cs-high | - | H |
57
+
- | - | L |
58
+
spi-cs-high | ACTIVE_HIGH | H |
59
+
- | ACTIVE_HIGH | L | 1
60
+
spi-cs-high | ACTIVE_LOW | H | 2
61
+
- | ACTIVE_LOW | L |
62
+
63
+
Notes:
64
+
1) Should print a warning about polarity inversion.
65
+
Here it would be wise to avoid and define the gpio as
66
+
ACTIVE_LOW.
67
+
2) Should print a warning about polarity inversion
68
+
because ACTIVE_LOW is overridden by spi-cs-high.
69
+
Should be generally avoided and be replaced by
70
+
spi-cs-high + ACTIVE_HIGH.
71
+
45
72
num-cs:
46
73
$ref: /schemas/types.yaml#/definitions/uint32
47
74
description:
+6
-4
Documentation/devicetree/bindings/spi/spi-sifive.yaml
+6
-4
Documentation/devicetree/bindings/spi/spi-sifive.yaml
···
17
17
properties:
18
18
compatible:
19
19
items:
20
-
- const: sifive,fu540-c000-spi
20
+
- enum:
21
+
- sifive,fu540-c000-spi
22
+
- sifive,fu740-c000-spi
21
23
- const: sifive,spi0
22
24
23
25
description:
24
26
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
25
27
Supported compatible strings are -
26
-
"sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27
-
onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
28
-
SPI v0 IP block with no chip integration tweaks.
28
+
"sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
29
+
as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
30
+
for the SiFive SPI v0 IP block with no chip integration tweaks.
29
31
Please refer to sifive-blocks-ip-versioning.txt for details
30
32
31
33
SPI RTL that corresponds to the IP block version numbers can be found here -
+2
-1
drivers/input/touchscreen/ads7846.c
+2
-1
drivers/input/touchscreen/ads7846.c
···
1288
1288
* may not. So we stick to very-portable 8 bit words, both RX and TX.
1289
1289
*/
1290
1290
spi->bits_per_word = 8;
1291
-
spi->mode = SPI_MODE_0;
1291
+
spi->mode &= ~SPI_MODE_X_MASK;
1292
+
spi->mode |= SPI_MODE_0;
1292
1293
err = spi_setup(spi);
1293
1294
if (err < 0)
1294
1295
return err;
+3
-2
drivers/media/pci/netup_unidvb/netup_unidvb_spi.c
+3
-2
drivers/media/pci/netup_unidvb/netup_unidvb_spi.c
···
175
175
struct spi_master *master;
176
176
struct netup_spi *nspi;
177
177
178
-
master = spi_alloc_master(&ndev->pci_dev->dev,
178
+
master = devm_spi_alloc_master(&ndev->pci_dev->dev,
179
179
sizeof(struct netup_spi));
180
180
if (!master) {
181
181
dev_err(&ndev->pci_dev->dev,
···
208
208
ndev->pci_slot,
209
209
ndev->pci_func);
210
210
if (!spi_new_device(master, &netup_spi_board)) {
211
+
spi_unregister_master(master);
211
212
ndev->spi = NULL;
212
213
dev_err(&ndev->pci_dev->dev,
213
214
"%s(): unable to create SPI device\n", __func__);
···
227
226
if (!spi)
228
227
return;
229
228
229
+
spi_unregister_master(spi->master);
230
230
spin_lock_irqsave(&spi->lock, flags);
231
231
reg = readw(&spi->regs->control_stat);
232
232
writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat);
233
233
reg = readw(&spi->regs->control_stat);
234
234
writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat);
235
235
spin_unlock_irqrestore(&spi->lock, flags);
236
-
spi_unregister_master(spi->master);
237
236
ndev->spi = NULL;
238
237
}
239
238
-2
drivers/platform/chrome/cros_ec_spi.c
-2
drivers/platform/chrome/cros_ec_spi.c
+2
-2
drivers/spi/Kconfig
+2
-2
drivers/spi/Kconfig
···
255
255
config SPI_DW_BT1
256
256
tristate "Baikal-T1 SPI driver for DW SPI core"
257
257
depends on MIPS_BAIKAL_T1 || COMPILE_TEST
258
+
select MULTIPLEXER
259
+
select MUX_MMIO
258
260
help
259
261
Baikal-T1 SoC is equipped with three DW APB SSI-based MMIO SPI
260
262
controllers. Two of them are pretty much normal: with IRQ, DMA,
···
270
268
config SPI_DW_BT1_DIRMAP
271
269
bool "Directly mapped Baikal-T1 Boot SPI flash support"
272
270
depends on SPI_DW_BT1
273
-
select MULTIPLEXER
274
-
select MUX_MMIO
275
271
help
276
272
Directly mapped SPI flash memory is an interface specific to the
277
273
Baikal-T1 System Boot Controller. It is a 16MB MMIO region, which
+19
-23
drivers/spi/atmel-quadspi.c
+19
-23
drivers/spi/atmel-quadspi.c
···
365
365
if (dummy_cycles)
366
366
ifr |= QSPI_IFR_NBDUM(dummy_cycles);
367
367
368
-
/* Set data enable */
369
-
if (op->data.nbytes)
368
+
/* Set data enable and data transfer type. */
369
+
if (op->data.nbytes) {
370
370
ifr |= QSPI_IFR_DATAEN;
371
+
372
+
if (op->addr.nbytes)
373
+
ifr |= QSPI_IFR_TFRTYP_MEM;
374
+
}
371
375
372
376
/*
373
377
* If the QSPI controller is set in regular SPI mode, set it in
···
385
381
/* Clear pending interrupts */
386
382
(void)atmel_qspi_read(aq, QSPI_SR);
387
383
388
-
if (aq->caps->has_ricr) {
389
-
if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
390
-
ifr |= QSPI_IFR_APBTFRTYP_READ;
391
-
392
-
/* Set QSPI Instruction Frame registers */
384
+
/* Set QSPI Instruction Frame registers. */
385
+
if (op->addr.nbytes && !op->data.nbytes)
393
386
atmel_qspi_write(iar, aq, QSPI_IAR);
387
+
388
+
if (aq->caps->has_ricr) {
394
389
if (op->data.dir == SPI_MEM_DATA_IN)
395
390
atmel_qspi_write(icr, aq, QSPI_RICR);
396
391
else
397
392
atmel_qspi_write(icr, aq, QSPI_WICR);
398
-
atmel_qspi_write(ifr, aq, QSPI_IFR);
399
393
} else {
400
-
if (op->data.dir == SPI_MEM_DATA_OUT)
394
+
if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
401
395
ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
402
396
403
-
/* Set QSPI Instruction Frame registers */
404
-
atmel_qspi_write(iar, aq, QSPI_IAR);
405
397
atmel_qspi_write(icr, aq, QSPI_ICR);
406
-
atmel_qspi_write(ifr, aq, QSPI_IFR);
407
398
}
399
+
400
+
atmel_qspi_write(ifr, aq, QSPI_IFR);
408
401
409
402
return 0;
410
403
}
···
536
535
struct resource *res;
537
536
int irq, err = 0;
538
537
539
-
ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
538
+
ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));
540
539
if (!ctrl)
541
540
return -ENOMEM;
542
541
···
558
557
aq->regs = devm_ioremap_resource(&pdev->dev, res);
559
558
if (IS_ERR(aq->regs)) {
560
559
dev_err(&pdev->dev, "missing registers\n");
561
-
err = PTR_ERR(aq->regs);
562
-
goto exit;
560
+
return PTR_ERR(aq->regs);
563
561
}
564
562
565
563
/* Map the AHB memory */
···
566
566
aq->mem = devm_ioremap_resource(&pdev->dev, res);
567
567
if (IS_ERR(aq->mem)) {
568
568
dev_err(&pdev->dev, "missing AHB memory\n");
569
-
err = PTR_ERR(aq->mem);
570
-
goto exit;
569
+
return PTR_ERR(aq->mem);
571
570
}
572
571
573
572
aq->mmap_size = resource_size(res);
···
578
579
579
580
if (IS_ERR(aq->pclk)) {
580
581
dev_err(&pdev->dev, "missing peripheral clock\n");
581
-
err = PTR_ERR(aq->pclk);
582
-
goto exit;
582
+
return PTR_ERR(aq->pclk);
583
583
}
584
584
585
585
/* Enable the peripheral clock */
586
586
err = clk_prepare_enable(aq->pclk);
587
587
if (err) {
588
588
dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
589
-
goto exit;
589
+
return err;
590
590
}
591
591
592
592
aq->caps = of_device_get_match_data(&pdev->dev);
593
593
if (!aq->caps) {
594
594
dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
595
595
err = -EINVAL;
596
-
goto exit;
596
+
goto disable_pclk;
597
597
}
598
598
599
599
if (aq->caps->has_qspick) {
···
636
638
clk_disable_unprepare(aq->qspick);
637
639
disable_pclk:
638
640
clk_disable_unprepare(aq->pclk);
639
-
exit:
640
-
spi_controller_put(ctrl);
641
641
642
642
return err;
643
643
}
+1
-4
drivers/spi/spi-amd.c
+1
-4
drivers/spi/spi-amd.c
···
250
250
struct device *dev = &pdev->dev;
251
251
struct spi_master *master;
252
252
struct amd_spi *amd_spi;
253
-
struct resource *res;
254
253
int err = 0;
255
254
256
255
/* Allocate storage for spi_master and driver private data */
···
260
261
}
261
262
262
263
amd_spi = spi_master_get_devdata(master);
263
-
264
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265
-
amd_spi->io_remap_addr = devm_ioremap_resource(&pdev->dev, res);
264
+
amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
266
265
if (IS_ERR(amd_spi->io_remap_addr)) {
267
266
err = PTR_ERR(amd_spi->io_remap_addr);
268
267
dev_err(dev, "error %d ioremap of SPI registers failed\n", err);
+11
-3
drivers/spi/spi-ar934x.c
+11
-3
drivers/spi/spi-ar934x.c
···
176
176
if (ret)
177
177
return ret;
178
178
179
-
ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
179
+
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
180
180
if (!ctlr) {
181
181
dev_info(&pdev->dev, "failed to allocate spi controller\n");
182
-
return -ENOMEM;
182
+
ret = -ENOMEM;
183
+
goto err_clk_disable;
183
184
}
184
185
185
186
/* disable flash mapping and expose spi controller registers */
···
203
202
sp->clk_freq = clk_get_rate(clk);
204
203
sp->ctlr = ctlr;
205
204
206
-
return devm_spi_register_controller(&pdev->dev, ctlr);
205
+
ret = spi_register_controller(ctlr);
206
+
if (!ret)
207
+
return 0;
208
+
209
+
err_clk_disable:
210
+
clk_disable_unprepare(clk);
211
+
return ret;
207
212
}
208
213
209
214
static int ar934x_spi_remove(struct platform_device *pdev)
···
220
213
ctlr = dev_get_drvdata(&pdev->dev);
221
214
sp = spi_controller_get_devdata(ctlr);
222
215
216
+
spi_unregister_controller(ctlr);
223
217
clk_disable_unprepare(sp->clk);
224
218
225
219
return 0;
+3
-3
drivers/spi/spi-atmel.c
+3
-3
drivers/spi/spi-atmel.c
···
512
512
513
513
master->dma_tx = dma_request_chan(dev, "tx");
514
514
if (IS_ERR(master->dma_tx)) {
515
-
err = dev_err_probe(dev, PTR_ERR(master->dma_tx),
516
-
"No TX DMA channel, DMA is disabled\n");
515
+
err = PTR_ERR(master->dma_tx);
516
+
dev_dbg(dev, "No TX DMA channel, DMA is disabled\n");
517
517
goto error_clear;
518
518
}
519
519
···
524
524
* No reason to check EPROBE_DEFER here since we have already
525
525
* requested tx channel.
526
526
*/
527
-
dev_err(dev, "No RX DMA channel, DMA is disabled\n");
527
+
dev_dbg(dev, "No RX DMA channel, DMA is disabled\n");
528
528
goto error;
529
529
}
530
530
+3
-1
drivers/spi/spi-bcm63xx-hsspi.c
+3
-1
drivers/spi/spi-bcm63xx-hsspi.c
+1
-1
drivers/spi/spi-davinci.c
+1
-1
drivers/spi/spi-davinci.c
···
1040
1040
spi_bitbang_stop(&dspi->bitbang);
1041
1041
1042
1042
clk_disable_unprepare(dspi->clk);
1043
-
spi_master_put(master);
1044
1043
1045
1044
if (dspi->dma_rx) {
1046
1045
dma_release_channel(dspi->dma_rx);
1047
1046
dma_release_channel(dspi->dma_tx);
1048
1047
}
1049
1048
1049
+
spi_master_put(master);
1050
1050
return 0;
1051
1051
}
1052
1052
+4
-2
drivers/spi/spi-dw-bt1.c
+4
-2
drivers/spi/spi-dw-bt1.c
···
217
217
if (mem) {
218
218
dwsbt1->map = devm_ioremap_resource(&pdev->dev, mem);
219
219
if (!IS_ERR(dwsbt1->map)) {
220
-
dwsbt1->map_len = (mem->end - mem->start + 1);
220
+
dwsbt1->map_len = resource_size(mem);
221
221
dws->mem_ops.dirmap_create = dw_spi_bt1_dirmap_create;
222
222
dws->mem_ops.dirmap_read = dw_spi_bt1_dirmap_read;
223
223
} else {
···
280
280
dws->bus_num = pdev->id;
281
281
dws->reg_io_width = 4;
282
282
dws->max_freq = clk_get_rate(dwsbt1->clk);
283
-
if (!dws->max_freq)
283
+
if (!dws->max_freq) {
284
+
ret = -EINVAL;
284
285
goto err_disable_clk;
286
+
}
285
287
286
288
init_func = device_get_match_data(&pdev->dev);
287
289
ret = init_func(pdev, dwsbt1);
+37
-7
drivers/spi/spi-dw-core.c
+37
-7
drivers/spi/spi-dw-core.c
···
137
137
static void dw_writer(struct dw_spi *dws)
138
138
{
139
139
u32 max = tx_max(dws);
140
-
u16 txw = 0;
140
+
u32 txw = 0;
141
141
142
142
while (max--) {
143
143
if (dws->tx) {
144
144
if (dws->n_bytes == 1)
145
145
txw = *(u8 *)(dws->tx);
146
-
else
146
+
else if (dws->n_bytes == 2)
147
147
txw = *(u16 *)(dws->tx);
148
+
else
149
+
txw = *(u32 *)(dws->tx);
148
150
149
151
dws->tx += dws->n_bytes;
150
152
}
···
158
156
static void dw_reader(struct dw_spi *dws)
159
157
{
160
158
u32 max = rx_max(dws);
161
-
u16 rxw;
159
+
u32 rxw;
162
160
163
161
while (max--) {
164
162
rxw = dw_read_io_reg(dws, DW_SPI_DR);
165
163
if (dws->rx) {
166
164
if (dws->n_bytes == 1)
167
165
*(u8 *)(dws->rx) = rxw;
168
-
else
166
+
else if (dws->n_bytes == 2)
169
167
*(u16 *)(dws->rx) = rxw;
168
+
else
169
+
*(u32 *)(dws->rx) = rxw;
170
170
171
171
dws->rx += dws->n_bytes;
172
172
}
···
315
311
u32 speed_hz;
316
312
u16 clk_div;
317
313
318
-
/* CTRLR0[ 4/3: 0] Data Frame Size */
319
-
cr0 |= (cfg->dfs - 1);
314
+
/* CTRLR0[ 4/3: 0] or CTRLR0[ 20: 16] Data Frame Size */
315
+
cr0 |= (cfg->dfs - 1) << dws->dfs_offset;
320
316
321
317
if (!(dws->caps & DW_SPI_CAP_DWC_SSI))
322
318
/* CTRLR0[ 9:8] Transfer Mode */
···
832
828
dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
833
829
}
834
830
831
+
/*
832
+
* Detect CTRLR0.DFS field size and offset by testing the lowest bits
833
+
* writability. Note DWC SSI controller also has the extended DFS, but
834
+
* with zero offset.
835
+
*/
836
+
if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) {
837
+
u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);
838
+
839
+
spi_enable_chip(dws, 0);
840
+
dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);
841
+
cr0 = dw_readl(dws, DW_SPI_CTRLR0);
842
+
dw_writel(dws, DW_SPI_CTRLR0, tmp);
843
+
spi_enable_chip(dws, 1);
844
+
845
+
if (!(cr0 & SPI_DFS_MASK)) {
846
+
dws->caps |= DW_SPI_CAP_DFS32;
847
+
dws->dfs_offset = SPI_DFS32_OFFSET;
848
+
dev_dbg(dev, "Detected 32-bits max data frame size\n");
849
+
}
850
+
} else {
851
+
dws->caps |= DW_SPI_CAP_DFS32;
852
+
}
853
+
835
854
/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
836
855
if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)
837
856
dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
···
891
864
892
865
master->use_gpio_descriptors = true;
893
866
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
894
-
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
867
+
if (dws->caps & DW_SPI_CAP_DFS32)
868
+
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
869
+
else
870
+
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
895
871
master->bus_num = dws->bus_num;
896
872
master->num_chipselect = dws->num_cs;
897
873
master->setup = dw_spi_setup;
+16
drivers/spi/spi-dw-mmio.c
+16
drivers/spi/spi-dw-mmio.c
···
222
222
return 0;
223
223
}
224
224
225
+
static int dw_spi_canaan_k210_init(struct platform_device *pdev,
226
+
struct dw_spi_mmio *dwsmmio)
227
+
{
228
+
/*
229
+
* The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
230
+
* documented to have a 32 word deep TX and RX FIFO, which
231
+
* spi_hw_init() detects. However, when the RX FIFO is filled up to
232
+
* 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
233
+
* problem by force setting fifo_len to 31.
234
+
*/
235
+
dwsmmio->dws.fifo_len = 31;
236
+
237
+
return 0;
238
+
}
239
+
225
240
static int dw_spi_mmio_probe(struct platform_device *pdev)
226
241
{
227
242
int (*init_func)(struct platform_device *pdev,
···
350
335
{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
351
336
{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
352
337
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
338
+
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
353
339
{ /* end of table */}
354
340
};
355
341
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
+5
drivers/spi/spi-dw.h
+5
drivers/spi/spi-dw.h
···
9
9
#include <linux/io.h>
10
10
#include <linux/scatterlist.h>
11
11
#include <linux/spi/spi-mem.h>
12
+
#include <linux/bitfield.h>
12
13
13
14
/* Register offsets */
14
15
#define DW_SPI_CTRLR0 0x00
···
42
41
43
42
/* Bit fields in CTRLR0 */
44
43
#define SPI_DFS_OFFSET 0
44
+
#define SPI_DFS_MASK GENMASK(3, 0)
45
+
#define SPI_DFS32_OFFSET 16
45
46
46
47
#define SPI_FRF_OFFSET 4
47
48
#define SPI_FRF_SPI 0x0
···
124
121
#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
125
122
#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
126
123
#define DW_SPI_CAP_DWC_SSI BIT(2)
124
+
#define DW_SPI_CAP_DFS32 BIT(3)
127
125
128
126
/* Slave spi_transfer/spi_mem_op related */
129
127
struct dw_spi_cfg {
···
152
148
unsigned long paddr;
153
149
int irq;
154
150
u32 fifo_len; /* depth of the FIFO buffer */
151
+
unsigned int dfs_offset; /* CTRLR0 DFS field offset */
155
152
u32 max_mem_freq; /* max mem-ops bus freq */
156
153
u32 max_freq; /* max bus freq supported */
157
154
+3
-3
drivers/spi/spi-fsl-dspi.c
+3
-3
drivers/spi/spi-fsl-dspi.c
···
1165
1165
unsigned int mcr;
1166
1166
1167
1167
/* Set idle states for all chip select signals to high */
1168
-
mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0));
1168
+
mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
1169
1169
1170
1170
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1171
1171
mcr |= SPI_MCR_XSPI;
···
1250
1250
1251
1251
pdata = dev_get_platdata(&pdev->dev);
1252
1252
if (pdata) {
1253
-
ctlr->num_chipselect = pdata->cs_num;
1253
+
ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
1254
1254
ctlr->bus_num = pdata->bus_num;
1255
1255
1256
1256
/* Only Coldfire uses platform data */
···
1263
1263
dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1264
1264
goto out_ctlr_put;
1265
1265
}
1266
-
ctlr->num_chipselect = cs_num;
1266
+
ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
1267
1267
1268
1268
of_property_read_u32(np, "bus-num", &bus_num);
1269
1269
ctlr->bus_num = bus_num;
+8
-3
drivers/spi/spi-fsl-spi.c
+8
-3
drivers/spi/spi-fsl-spi.c
···
716
716
type = fsl_spi_get_type(&ofdev->dev);
717
717
if (type == TYPE_FSL) {
718
718
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
719
+
bool spisel_boot = false;
719
720
#if IS_ENABLED(CONFIG_FSL_SOC)
720
721
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
721
-
bool spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
722
722
723
+
spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
723
724
if (spisel_boot) {
724
725
pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
725
726
if (!pinfo->immr_spi_cs)
···
735
734
* supported on the GRLIB variant.
736
735
*/
737
736
ret = gpiod_count(dev, "cs");
738
-
if (ret <= 0)
737
+
if (ret < 0)
738
+
ret = 0;
739
+
if (ret == 0 && !spisel_boot) {
739
740
pdata->max_chipselect = 1;
740
-
else
741
+
} else {
742
+
pdata->max_chipselect = ret + spisel_boot;
741
743
pdata->cs_control = fsl_spi_cs_control;
744
+
}
742
745
}
743
746
744
747
ret = of_address_to_resource(np, 0, &mem);
+2
-2
drivers/spi/spi-geni-qcom.c
+2
-2
drivers/spi/spi-geni-qcom.c
···
603
603
if (IS_ERR(clk))
604
604
return PTR_ERR(clk);
605
605
606
-
spi = spi_alloc_master(dev, sizeof(*mas));
606
+
spi = devm_spi_alloc_master(dev, sizeof(*mas));
607
607
if (!spi)
608
608
return -ENOMEM;
609
609
···
636
636
spi->auto_runtime_pm = true;
637
637
spi->handle_err = handle_fifo_timeout;
638
638
spi->set_cs = spi_geni_set_cs;
639
+
spi->use_gpio_descriptors = true;
639
640
640
641
init_completion(&mas->cs_done);
641
642
init_completion(&mas->cancel_done);
···
674
673
free_irq(mas->irq, spi);
675
674
spi_geni_probe_runtime_disable:
676
675
pm_runtime_disable(dev);
677
-
spi_master_put(spi);
678
676
dev_pm_opp_of_remove_table(&pdev->dev);
679
677
put_clkname:
680
678
dev_pm_opp_put_clkname(mas->se.opp_table);
+2
-13
drivers/spi/spi-gpio.c
+2
-13
drivers/spi/spi-gpio.c
···
350
350
return 0;
351
351
}
352
352
353
-
static void spi_gpio_put(void *data)
354
-
{
355
-
spi_master_put(data);
356
-
}
357
-
358
353
static int spi_gpio_probe(struct platform_device *pdev)
359
354
{
360
355
int status;
···
358
363
struct device *dev = &pdev->dev;
359
364
struct spi_bitbang *bb;
360
365
361
-
master = spi_alloc_master(dev, sizeof(*spi_gpio));
366
+
master = devm_spi_alloc_master(dev, sizeof(*spi_gpio));
362
367
if (!master)
363
368
return -ENOMEM;
364
-
365
-
status = devm_add_action_or_reset(&pdev->dev, spi_gpio_put, master);
366
-
if (status) {
367
-
spi_master_put(master);
368
-
return status;
369
-
}
370
369
371
370
if (pdev->dev.of_node)
372
371
status = spi_gpio_probe_dt(pdev, master);
···
421
432
if (status)
422
433
return status;
423
434
424
-
return devm_spi_register_master(&pdev->dev, spi_master_get(master));
435
+
return devm_spi_register_master(&pdev->dev, master);
425
436
}
426
437
427
438
MODULE_ALIAS("platform:" DRIVER_NAME);
+3
-1
drivers/spi/spi-img-spfi.c
+3
-1
drivers/spi/spi-img-spfi.c
+3
-30
drivers/spi/spi-imx.c
+3
-30
drivers/spi/spi-imx.c
···
1019
1019
.devtype = IMX53_ECSPI,
1020
1020
};
1021
1021
1022
-
static const struct platform_device_id spi_imx_devtype[] = {
1023
-
{
1024
-
.name = "imx1-cspi",
1025
-
.driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1026
-
}, {
1027
-
.name = "imx21-cspi",
1028
-
.driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1029
-
}, {
1030
-
.name = "imx27-cspi",
1031
-
.driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1032
-
}, {
1033
-
.name = "imx31-cspi",
1034
-
.driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1035
-
}, {
1036
-
.name = "imx35-cspi",
1037
-
.driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1038
-
}, {
1039
-
.name = "imx51-ecspi",
1040
-
.driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1041
-
}, {
1042
-
.name = "imx53-ecspi",
1043
-
.driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1044
-
}, {
1045
-
/* sentinel */
1046
-
}
1047
-
};
1048
-
1049
1022
static const struct of_device_id spi_imx_dt_ids[] = {
1050
1023
{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1051
1024
{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
···
1511
1538
1512
1539
ret = pm_runtime_get_sync(spi_imx->dev);
1513
1540
if (ret < 0) {
1541
+
pm_runtime_put_noidle(spi_imx->dev);
1514
1542
dev_err(spi_imx->dev, "failed to enable clock\n");
1515
1543
return ret;
1516
1544
}
···
1554
1580
struct spi_imx_data *spi_imx;
1555
1581
struct resource *res;
1556
1582
int ret, irq, spi_drctl;
1557
-
const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1558
-
(struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1583
+
const struct spi_imx_devtype_data *devtype_data = of_id->data;
1559
1584
bool slave_mode;
1560
1585
u32 val;
1561
1586
···
1721
1748
1722
1749
ret = pm_runtime_get_sync(spi_imx->dev);
1723
1750
if (ret < 0) {
1751
+
pm_runtime_put_noidle(spi_imx->dev);
1724
1752
dev_err(spi_imx->dev, "failed to enable clock\n");
1725
1753
return ret;
1726
1754
}
···
1796
1822
.of_match_table = spi_imx_dt_ids,
1797
1823
.pm = &imx_spi_pm,
1798
1824
},
1799
-
.id_table = spi_imx_devtype,
1800
1825
.probe = spi_imx_probe,
1801
1826
.remove = spi_imx_remove,
1802
1827
};
+2
-1
drivers/spi/spi-mem.c
+2
-1
drivers/spi/spi-mem.c
···
243
243
244
244
ret = pm_runtime_get_sync(ctlr->dev.parent);
245
245
if (ret < 0) {
246
+
pm_runtime_put_noidle(ctlr->dev.parent);
246
247
dev_err(&ctlr->dev, "Failed to power device: %d\n",
247
248
ret);
248
249
return ret;
···
744
743
mem->name = dev_name(&spi->dev);
745
744
746
745
if (IS_ERR_OR_NULL(mem->name))
747
-
return PTR_ERR(mem->name);
746
+
return PTR_ERR_OR_ZERO(mem->name);
748
747
749
748
spi_set_drvdata(spi, mem);
750
749
+9
-2
drivers/spi/spi-mt7621.c
+9
-2
drivers/spi/spi-mt7621.c
···
350
350
if (status)
351
351
return status;
352
352
353
-
master = spi_alloc_master(&pdev->dev, sizeof(*rs));
353
+
master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
354
354
if (!master) {
355
355
dev_info(&pdev->dev, "master allocation failed\n");
356
+
clk_disable_unprepare(clk);
356
357
return -ENOMEM;
357
358
}
358
359
···
378
377
ret = device_reset(&pdev->dev);
379
378
if (ret) {
380
379
dev_err(&pdev->dev, "SPI reset failed!\n");
380
+
clk_disable_unprepare(clk);
381
381
return ret;
382
382
}
383
383
384
-
return devm_spi_register_controller(&pdev->dev, master);
384
+
ret = spi_register_controller(master);
385
+
if (ret)
386
+
clk_disable_unprepare(clk);
387
+
388
+
return ret;
385
389
}
386
390
387
391
static int mt7621_spi_remove(struct platform_device *pdev)
···
397
391
master = dev_get_drvdata(&pdev->dev);
398
392
rs = spi_controller_get_devdata(master);
399
393
394
+
spi_unregister_controller(master);
400
395
clk_disable_unprepare(rs->clk);
401
396
402
397
return 0;
+16
-2
drivers/spi/spi-mtk-nor.c
+16
-2
drivers/spi/spi-mtk-nor.c
···
103
103
dma_addr_t buffer_dma;
104
104
struct clk *spi_clk;
105
105
struct clk *ctlr_clk;
106
+
struct clk *axi_clk;
106
107
unsigned int spi_freq;
107
108
bool wbuf_en;
108
109
bool has_irq;
···
673
672
{
674
673
clk_disable_unprepare(sp->spi_clk);
675
674
clk_disable_unprepare(sp->ctlr_clk);
675
+
clk_disable_unprepare(sp->axi_clk);
676
676
}
677
677
678
678
static int mtk_nor_enable_clk(struct mtk_nor *sp)
···
687
685
ret = clk_prepare_enable(sp->ctlr_clk);
688
686
if (ret) {
689
687
clk_disable_unprepare(sp->spi_clk);
688
+
return ret;
689
+
}
690
+
691
+
ret = clk_prepare_enable(sp->axi_clk);
692
+
if (ret) {
693
+
clk_disable_unprepare(sp->spi_clk);
694
+
clk_disable_unprepare(sp->ctlr_clk);
690
695
return ret;
691
696
}
692
697
···
755
746
struct spi_controller *ctlr;
756
747
struct mtk_nor *sp;
757
748
void __iomem *base;
758
-
struct clk *spi_clk, *ctlr_clk;
749
+
struct clk *spi_clk, *ctlr_clk, *axi_clk;
759
750
int ret, irq;
760
751
unsigned long dma_bits;
761
752
···
771
762
if (IS_ERR(ctlr_clk))
772
763
return PTR_ERR(ctlr_clk);
773
764
765
+
axi_clk = devm_clk_get_optional(&pdev->dev, "axi");
766
+
if (IS_ERR(axi_clk))
767
+
return PTR_ERR(axi_clk);
768
+
774
769
dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
775
770
if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
776
771
dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
777
772
return -EINVAL;
778
773
}
779
774
780
-
ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
775
+
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
781
776
if (!ctlr) {
782
777
dev_err(&pdev->dev, "failed to allocate spi controller\n");
783
778
return -ENOMEM;
···
807
794
sp->dev = &pdev->dev;
808
795
sp->spi_clk = spi_clk;
809
796
sp->ctlr_clk = ctlr_clk;
797
+
sp->axi_clk = axi_clk;
810
798
sp->high_dma = (dma_bits > 32);
811
799
sp->buffer = dmam_alloc_coherent(&pdev->dev,
812
800
MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
+2
-8
drivers/spi/spi-mxic.c
+2
-8
drivers/spi/spi-mxic.c
···
529
529
struct mxic_spi *mxic;
530
530
int ret;
531
531
532
-
master = spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
532
+
master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
533
533
if (!master)
534
534
return -ENOMEM;
535
535
···
574
574
ret = spi_register_master(master);
575
575
if (ret) {
576
576
dev_err(&pdev->dev, "spi_register_master failed\n");
577
-
goto err_put_master;
577
+
pm_runtime_disable(&pdev->dev);
578
578
}
579
-
580
-
return 0;
581
-
582
-
err_put_master:
583
-
spi_master_put(master);
584
-
pm_runtime_disable(&pdev->dev);
585
579
586
580
return ret;
587
581
}
+1
drivers/spi/spi-mxs.c
+1
drivers/spi/spi-mxs.c
+6
-2
drivers/spi/spi-npcm-fiu.c
+6
-2
drivers/spi/spi-npcm-fiu.c
···
677
677
struct npcm_fiu_spi *fiu;
678
678
void __iomem *regbase;
679
679
struct resource *res;
680
-
int id;
680
+
int id, ret;
681
681
682
682
ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
683
683
if (!ctrl)
···
735
735
ctrl->num_chipselect = fiu->info->max_cs;
736
736
ctrl->dev.of_node = dev->of_node;
737
737
738
-
return devm_spi_register_master(dev, ctrl);
738
+
ret = devm_spi_register_master(dev, ctrl);
739
+
if (ret)
740
+
clk_disable_unprepare(fiu->clk);
741
+
742
+
return ret;
739
743
}
740
744
741
745
static int npcm_fiu_remove(struct platform_device *pdev)
+1
drivers/spi/spi-pic32.c
+1
drivers/spi/spi-pic32.c
+7
-3
drivers/spi/spi-pxa2xx.c
+7
-3
drivers/spi/spi-pxa2xx.c
···
1496
1496
{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1497
1497
{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1498
1498
{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1499
+
/* ADL-S */
1500
+
{ PCI_VDEVICE(INTEL, 0x7aaa), LPSS_CNL_SSP },
1501
+
{ PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP },
1502
+
{ PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP },
1503
+
{ PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP },
1499
1504
/* CNL-LP */
1500
1505
{ PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1501
1506
{ PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
···
1691
1686
}
1692
1687
1693
1688
if (platform_info->is_slave)
1694
-
controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1689
+
controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1695
1690
else
1696
-
controller = spi_alloc_master(dev, sizeof(struct driver_data));
1691
+
controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1697
1692
1698
1693
if (!controller) {
1699
1694
dev_err(&pdev->dev, "cannot alloc spi_controller\n");
···
1916
1911
free_irq(ssp->irq, drv_data);
1917
1912
1918
1913
out_error_controller_alloc:
1919
-
spi_controller_put(controller);
1920
1914
pxa_ssp_free(ssp);
1921
1915
return status;
1922
1916
}
+16
-26
drivers/spi/spi-qcom-qspi.c
+16
-26
drivers/spi/spi-qcom-qspi.c
···
462
462
463
463
dev = &pdev->dev;
464
464
465
-
master = spi_alloc_master(dev, sizeof(*ctrl));
465
+
master = devm_spi_alloc_master(dev, sizeof(*ctrl));
466
466
if (!master)
467
467
return -ENOMEM;
468
468
···
473
473
spin_lock_init(&ctrl->lock);
474
474
ctrl->dev = dev;
475
475
ctrl->base = devm_platform_ioremap_resource(pdev, 0);
476
-
if (IS_ERR(ctrl->base)) {
477
-
ret = PTR_ERR(ctrl->base);
478
-
goto exit_probe_master_put;
479
-
}
476
+
if (IS_ERR(ctrl->base))
477
+
return PTR_ERR(ctrl->base);
480
478
481
479
ctrl->clks = devm_kcalloc(dev, QSPI_NUM_CLKS,
482
480
sizeof(*ctrl->clks), GFP_KERNEL);
483
-
if (!ctrl->clks) {
484
-
ret = -ENOMEM;
485
-
goto exit_probe_master_put;
486
-
}
481
+
if (!ctrl->clks)
482
+
return -ENOMEM;
487
483
488
484
ctrl->clks[QSPI_CLK_CORE].id = "core";
489
485
ctrl->clks[QSPI_CLK_IFACE].id = "iface";
490
486
ret = devm_clk_bulk_get(dev, QSPI_NUM_CLKS, ctrl->clks);
491
487
if (ret)
492
-
goto exit_probe_master_put;
488
+
return ret;
493
489
494
490
ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
495
-
if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) {
496
-
ret = dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi),
497
-
"Failed to get cpu path\n");
498
-
goto exit_probe_master_put;
499
-
}
491
+
if (IS_ERR(ctrl->icc_path_cpu_to_qspi))
492
+
return dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi),
493
+
"Failed to get cpu path\n");
494
+
500
495
/* Set BW vote for register access */
501
496
ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
502
497
Bps_to_icc(1000));
503
498
if (ret) {
504
499
dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
505
500
__func__, ret);
506
-
goto exit_probe_master_put;
501
+
return ret;
507
502
}
508
503
509
504
ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
510
505
if (ret) {
511
506
dev_err(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
512
507
__func__, ret);
513
-
goto exit_probe_master_put;
508
+
return ret;
514
509
}
515
510
516
511
ret = platform_get_irq(pdev, 0);
517
512
if (ret < 0)
518
-
goto exit_probe_master_put;
513
+
return ret;
519
514
ret = devm_request_irq(dev, ret, qcom_qspi_irq,
520
515
IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
521
516
if (ret) {
522
517
dev_err(dev, "Failed to request irq %d\n", ret);
523
-
goto exit_probe_master_put;
518
+
return ret;
524
519
}
525
520
526
521
master->max_speed_hz = 300000000;
···
532
537
master->auto_runtime_pm = true;
533
538
534
539
ctrl->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
535
-
if (IS_ERR(ctrl->opp_table)) {
536
-
ret = PTR_ERR(ctrl->opp_table);
537
-
goto exit_probe_master_put;
538
-
}
540
+
if (IS_ERR(ctrl->opp_table))
541
+
return PTR_ERR(ctrl->opp_table);
539
542
/* OPP table is optional */
540
543
ret = dev_pm_opp_of_add_table(&pdev->dev);
541
544
if (ret && ret != -ENODEV) {
···
554
561
555
562
exit_probe_put_clkname:
556
563
dev_pm_opp_put_clkname(ctrl->opp_table);
557
-
558
-
exit_probe_master_put:
559
-
spi_master_put(master);
560
564
561
565
return ret;
562
566
}
+1
-1
drivers/spi/spi-rb4xx.c
+1
-1
drivers/spi/spi-rb4xx.c
+4
drivers/spi/spi-rockchip.c
+4
drivers/spi/spi-rockchip.c
···
160
160
#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
161
161
#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
162
162
163
+
#define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000
164
+
163
165
struct rockchip_spi {
164
166
struct device *dev;
165
167
···
717
715
goto err_disable_spiclk;
718
716
}
719
717
718
+
pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
719
+
pm_runtime_use_autosuspend(&pdev->dev);
720
720
pm_runtime_set_active(&pdev->dev);
721
721
pm_runtime_enable(&pdev->dev);
722
722
+2
-7
drivers/spi/spi-rpc-if.c
+2
-7
drivers/spi/spi-rpc-if.c
···
134
134
struct rpcif *rpc;
135
135
int error;
136
136
137
-
ctlr = spi_alloc_master(&pdev->dev, sizeof(*rpc));
137
+
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*rpc));
138
138
if (!ctlr)
139
139
return -ENOMEM;
140
140
···
159
159
error = spi_register_controller(ctlr);
160
160
if (error) {
161
161
dev_err(&pdev->dev, "spi_register_controller failed\n");
162
-
goto err_put_ctlr;
162
+
rpcif_disable_rpm(rpc);
163
163
}
164
-
return 0;
165
-
166
-
err_put_ctlr:
167
-
rpcif_disable_rpm(rpc);
168
-
spi_controller_put(ctlr);
169
164
170
165
return error;
171
166
}
+2
-11
drivers/spi/spi-sc18is602.c
+2
-11
drivers/spi/spi-sc18is602.c
···
238
238
struct sc18is602_platform_data *pdata = dev_get_platdata(dev);
239
239
struct sc18is602 *hw;
240
240
struct spi_master *master;
241
-
int error;
242
241
243
242
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
244
243
I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
245
244
return -EINVAL;
246
245
247
-
master = spi_alloc_master(dev, sizeof(struct sc18is602));
246
+
master = devm_spi_alloc_master(dev, sizeof(struct sc18is602));
248
247
if (!master)
249
248
return -ENOMEM;
250
249
···
297
298
master->min_speed_hz = hw->freq / 128;
298
299
master->max_speed_hz = hw->freq / 4;
299
300
300
-
error = devm_spi_register_master(dev, master);
301
-
if (error)
302
-
goto error_reg;
303
-
304
-
return 0;
305
-
306
-
error_reg:
307
-
spi_master_put(master);
308
-
return error;
301
+
return devm_spi_register_master(dev, master);
309
302
}
310
303
311
304
static const struct i2c_device_id sc18is602_id[] = {
+4
-9
drivers/spi/spi-sh.c
+4
-9
drivers/spi/spi-sh.c
···
440
440
if (irq < 0)
441
441
return irq;
442
442
443
-
master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
443
+
master = devm_spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
444
444
if (master == NULL) {
445
445
dev_err(&pdev->dev, "spi_alloc_master error.\n");
446
446
return -ENOMEM;
···
458
458
break;
459
459
default:
460
460
dev_err(&pdev->dev, "No support width\n");
461
-
ret = -ENODEV;
462
-
goto error1;
461
+
return -ENODEV;
463
462
}
464
463
ss->irq = irq;
465
464
ss->master = master;
466
465
ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
467
466
if (ss->addr == NULL) {
468
467
dev_err(&pdev->dev, "ioremap error.\n");
469
-
ret = -ENOMEM;
470
-
goto error1;
468
+
return -ENOMEM;
471
469
}
472
470
INIT_LIST_HEAD(&ss->queue);
473
471
spin_lock_init(&ss->lock);
···
475
477
ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
476
478
if (ret < 0) {
477
479
dev_err(&pdev->dev, "request_irq error\n");
478
-
goto error1;
480
+
return ret;
479
481
}
480
482
481
483
master->num_chipselect = 2;
···
494
496
495
497
error3:
496
498
free_irq(irq, ss);
497
-
error1:
498
-
spi_master_put(master);
499
-
500
499
return ret;
501
500
}
502
501
+1
drivers/spi/spi-sprd.c
+1
drivers/spi/spi-sprd.c
+3
-2
drivers/spi/spi-st-ssc4.c
+3
-2
drivers/spi/spi-st-ssc4.c
···
375
375
ret = devm_spi_register_master(&pdev->dev, master);
376
376
if (ret) {
377
377
dev_err(&pdev->dev, "Failed to register master\n");
378
-
goto clk_disable;
378
+
goto rpm_disable;
379
379
}
380
380
381
381
return 0;
382
382
383
-
clk_disable:
383
+
rpm_disable:
384
384
pm_runtime_disable(&pdev->dev);
385
+
clk_disable:
385
386
clk_disable_unprepare(spi_st->clk);
386
387
put_master:
387
388
spi_master_put(master);
+6
-2
drivers/spi/spi-stm32-qspi.c
+6
-2
drivers/spi/spi-stm32-qspi.c
···
434
434
int ret;
435
435
436
436
ret = pm_runtime_get_sync(qspi->dev);
437
-
if (ret < 0)
437
+
if (ret < 0) {
438
+
pm_runtime_put_noidle(qspi->dev);
438
439
return ret;
440
+
}
439
441
440
442
mutex_lock(&qspi->lock);
441
443
ret = stm32_qspi_send(mem, op);
···
464
462
return -EINVAL;
465
463
466
464
ret = pm_runtime_get_sync(qspi->dev);
467
-
if (ret < 0)
465
+
if (ret < 0) {
466
+
pm_runtime_put_noidle(qspi->dev);
468
467
return ret;
468
+
}
469
469
470
470
presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
471
471
+1
drivers/spi/spi-stm32.c
+1
drivers/spi/spi-stm32.c
+180
-19
drivers/spi/spi-sun6i.c
+180
-19
drivers/spi/spi-sun6i.c
···
18
18
#include <linux/platform_device.h>
19
19
#include <linux/pm_runtime.h>
20
20
#include <linux/reset.h>
21
+
#include <linux/dmaengine.h>
21
22
22
23
#include <linux/spi/spi.h>
24
+
25
+
#define SUN6I_AUTOSUSPEND_TIMEOUT 2000
23
26
24
27
#define SUN6I_FIFO_DEPTH 128
25
28
#define SUN8I_FIFO_DEPTH 64
···
55
52
56
53
#define SUN6I_FIFO_CTL_REG 0x18
57
54
#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
55
+
#define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8)
58
56
#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
59
57
#define SUN6I_FIFO_CTL_RF_RST BIT(15)
60
58
#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
61
59
#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
60
+
#define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24)
62
61
#define SUN6I_FIFO_CTL_TF_RST BIT(31)
63
62
64
63
#define SUN6I_FIFO_STA_REG 0x1c
···
88
83
struct sun6i_spi {
89
84
struct spi_master *master;
90
85
void __iomem *base_addr;
86
+
dma_addr_t dma_addr_rx;
87
+
dma_addr_t dma_addr_tx;
91
88
struct clk *hclk;
92
89
struct clk *mclk;
93
90
struct reset_control *rstc;
···
189
182
return SUN6I_MAX_XFER_SIZE - 1;
190
183
}
191
184
185
+
static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
186
+
struct spi_transfer *tfr)
187
+
{
188
+
struct dma_async_tx_descriptor *rxdesc, *txdesc;
189
+
struct spi_master *master = sspi->master;
190
+
191
+
rxdesc = NULL;
192
+
if (tfr->rx_buf) {
193
+
struct dma_slave_config rxconf = {
194
+
.direction = DMA_DEV_TO_MEM,
195
+
.src_addr = sspi->dma_addr_rx,
196
+
.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
197
+
.src_maxburst = 8,
198
+
};
199
+
200
+
dmaengine_slave_config(master->dma_rx, &rxconf);
201
+
202
+
rxdesc = dmaengine_prep_slave_sg(master->dma_rx,
203
+
tfr->rx_sg.sgl,
204
+
tfr->rx_sg.nents,
205
+
DMA_DEV_TO_MEM,
206
+
DMA_PREP_INTERRUPT);
207
+
if (!rxdesc)
208
+
return -EINVAL;
209
+
}
210
+
211
+
txdesc = NULL;
212
+
if (tfr->tx_buf) {
213
+
struct dma_slave_config txconf = {
214
+
.direction = DMA_MEM_TO_DEV,
215
+
.dst_addr = sspi->dma_addr_tx,
216
+
.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
217
+
.dst_maxburst = 8,
218
+
};
219
+
220
+
dmaengine_slave_config(master->dma_tx, &txconf);
221
+
222
+
txdesc = dmaengine_prep_slave_sg(master->dma_tx,
223
+
tfr->tx_sg.sgl,
224
+
tfr->tx_sg.nents,
225
+
DMA_MEM_TO_DEV,
226
+
DMA_PREP_INTERRUPT);
227
+
if (!txdesc) {
228
+
if (rxdesc)
229
+
dmaengine_terminate_sync(master->dma_rx);
230
+
return -EINVAL;
231
+
}
232
+
}
233
+
234
+
if (tfr->rx_buf) {
235
+
dmaengine_submit(rxdesc);
236
+
dma_async_issue_pending(master->dma_rx);
237
+
}
238
+
239
+
if (tfr->tx_buf) {
240
+
dmaengine_submit(txdesc);
241
+
dma_async_issue_pending(master->dma_tx);
242
+
}
243
+
244
+
return 0;
245
+
}
246
+
192
247
static int sun6i_spi_transfer_one(struct spi_master *master,
193
248
struct spi_device *spi,
194
249
struct spi_transfer *tfr)
···
260
191
unsigned int start, end, tx_time;
261
192
unsigned int trig_level;
262
193
unsigned int tx_len = 0, rx_len = 0;
194
+
bool use_dma;
263
195
int ret = 0;
264
196
u32 reg;
265
197
···
271
201
sspi->tx_buf = tfr->tx_buf;
272
202
sspi->rx_buf = tfr->rx_buf;
273
203
sspi->len = tfr->len;
204
+
use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false;
274
205
275
206
/* Clear pending interrupts */
276
207
sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
···
280
209
sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
281
210
SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
282
211
283
-
/*
284
-
* Setup FIFO interrupt trigger level
285
-
* Here we choose 3/4 of the full fifo depth, as it's the hardcoded
286
-
* value used in old generation of Allwinner SPI controller.
287
-
* (See spi-sun4i.c)
288
-
*/
289
-
trig_level = sspi->fifo_depth / 4 * 3;
290
-
sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
291
-
(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
292
-
(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
212
+
reg = 0;
213
+
214
+
if (!use_dma) {
215
+
/*
216
+
* Setup FIFO interrupt trigger level
217
+
* Here we choose 3/4 of the full fifo depth, as it's
218
+
* the hardcoded value used in old generation of Allwinner
219
+
* SPI controller. (See spi-sun4i.c)
220
+
*/
221
+
trig_level = sspi->fifo_depth / 4 * 3;
222
+
} else {
223
+
/*
224
+
* Setup FIFO DMA request trigger level
225
+
* We choose 1/2 of the full fifo depth, that value will
226
+
* be used as DMA burst length.
227
+
*/
228
+
trig_level = sspi->fifo_depth / 2;
229
+
230
+
if (tfr->tx_buf)
231
+
reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
232
+
if (tfr->rx_buf)
233
+
reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
234
+
}
235
+
236
+
reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
237
+
(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
238
+
239
+
sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
293
240
294
241
/*
295
242
* Setup the transfer control register: Chip Select,
···
389
300
sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
390
301
sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
391
302
392
-
/* Fill the TX FIFO */
393
-
sun6i_spi_fill_fifo(sspi);
303
+
if (!use_dma) {
304
+
/* Fill the TX FIFO */
305
+
sun6i_spi_fill_fifo(sspi);
306
+
} else {
307
+
ret = sun6i_spi_prepare_dma(sspi, tfr);
308
+
if (ret) {
309
+
dev_warn(&master->dev,
310
+
"%s: prepare DMA failed, ret=%d",
311
+
dev_name(&spi->dev), ret);
312
+
return ret;
313
+
}
314
+
}
394
315
395
316
/* Enable the interrupts */
396
317
reg = SUN6I_INT_CTL_TC;
397
318
398
-
if (rx_len > sspi->fifo_depth)
399
-
reg |= SUN6I_INT_CTL_RF_RDY;
400
-
if (tx_len > sspi->fifo_depth)
401
-
reg |= SUN6I_INT_CTL_TF_ERQ;
319
+
if (!use_dma) {
320
+
if (rx_len > sspi->fifo_depth)
321
+
reg |= SUN6I_INT_CTL_RF_RDY;
322
+
if (tx_len > sspi->fifo_depth)
323
+
reg |= SUN6I_INT_CTL_TF_ERQ;
324
+
}
402
325
403
326
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
404
327
···
432
331
}
433
332
434
333
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
334
+
335
+
if (ret && use_dma) {
336
+
dmaengine_terminate_sync(master->dma_rx);
337
+
dmaengine_terminate_sync(master->dma_tx);
338
+
}
435
339
436
340
return ret;
437
341
}
···
528
422
return 0;
529
423
}
530
424
425
+
static bool sun6i_spi_can_dma(struct spi_master *master,
426
+
struct spi_device *spi,
427
+
struct spi_transfer *xfer)
428
+
{
429
+
struct sun6i_spi *sspi = spi_master_get_devdata(master);
430
+
431
+
/*
432
+
* If the number of spi words to transfer is less or equal than
433
+
* the fifo length we can just fill the fifo and wait for a single
434
+
* irq, so don't bother setting up dma
435
+
*/
436
+
return xfer->len > sspi->fifo_depth;
437
+
}
438
+
531
439
static int sun6i_spi_probe(struct platform_device *pdev)
532
440
{
533
441
struct spi_master *master;
534
442
struct sun6i_spi *sspi;
443
+
struct resource *mem;
535
444
int ret = 0, irq;
536
445
537
446
master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
···
558
437
platform_set_drvdata(pdev, master);
559
438
sspi = spi_master_get_devdata(master);
560
439
561
-
sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
440
+
sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
562
441
if (IS_ERR(sspi->base_addr)) {
563
442
ret = PTR_ERR(sspi->base_addr);
564
443
goto err_free_master;
···
615
494
goto err_free_master;
616
495
}
617
496
497
+
master->dma_tx = dma_request_chan(&pdev->dev, "tx");
498
+
if (IS_ERR(master->dma_tx)) {
499
+
/* Check tx to see if we need defer probing driver */
500
+
if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
501
+
ret = -EPROBE_DEFER;
502
+
goto err_free_master;
503
+
}
504
+
dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
505
+
master->dma_tx = NULL;
506
+
}
507
+
508
+
master->dma_rx = dma_request_chan(&pdev->dev, "rx");
509
+
if (IS_ERR(master->dma_rx)) {
510
+
if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
511
+
ret = -EPROBE_DEFER;
512
+
goto err_free_dma_tx;
513
+
}
514
+
dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
515
+
master->dma_rx = NULL;
516
+
}
517
+
518
+
if (master->dma_tx && master->dma_rx) {
519
+
sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
520
+
sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
521
+
master->can_dma = sun6i_spi_can_dma;
522
+
}
523
+
618
524
/*
619
525
* This wake-up/shutdown pattern is to be able to have the
620
526
* device woken up, even if runtime_pm is disabled
···
649
501
ret = sun6i_spi_runtime_resume(&pdev->dev);
650
502
if (ret) {
651
503
dev_err(&pdev->dev, "Couldn't resume the device\n");
652
-
goto err_free_master;
504
+
goto err_free_dma_rx;
653
505
}
654
506
507
+
pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
508
+
pm_runtime_use_autosuspend(&pdev->dev);
655
509
pm_runtime_set_active(&pdev->dev);
656
510
pm_runtime_enable(&pdev->dev);
657
-
pm_runtime_idle(&pdev->dev);
658
511
659
512
ret = devm_spi_register_master(&pdev->dev, master);
660
513
if (ret) {
···
668
519
err_pm_disable:
669
520
pm_runtime_disable(&pdev->dev);
670
521
sun6i_spi_runtime_suspend(&pdev->dev);
522
+
err_free_dma_rx:
523
+
if (master->dma_rx)
524
+
dma_release_channel(master->dma_rx);
525
+
err_free_dma_tx:
526
+
if (master->dma_tx)
527
+
dma_release_channel(master->dma_tx);
671
528
err_free_master:
672
529
spi_master_put(master);
673
530
return ret;
···
681
526
682
527
static int sun6i_spi_remove(struct platform_device *pdev)
683
528
{
529
+
struct spi_master *master = platform_get_drvdata(pdev);
530
+
684
531
pm_runtime_force_suspend(&pdev->dev);
685
532
533
+
if (master->dma_tx)
534
+
dma_release_channel(master->dma_tx);
535
+
if (master->dma_rx)
536
+
dma_release_channel(master->dma_rx);
686
537
return 0;
687
538
}
688
539
+8
-7
drivers/spi/spi-synquacer.c
+8
-7
drivers/spi/spi-synquacer.c
···
657
657
658
658
if (!master->max_speed_hz) {
659
659
dev_err(&pdev->dev, "missing clock source\n");
660
-
return -EINVAL;
660
+
ret = -EINVAL;
661
+
goto disable_clk;
661
662
}
662
663
master->min_speed_hz = master->max_speed_hz / 254;
663
664
···
671
670
rx_irq = platform_get_irq(pdev, 0);
672
671
if (rx_irq <= 0) {
673
672
ret = rx_irq;
674
-
goto put_spi;
673
+
goto disable_clk;
675
674
}
676
675
snprintf(sspi->rx_irq_name, SYNQUACER_HSSPI_IRQ_NAME_MAX, "%s-rx",
677
676
dev_name(&pdev->dev));
···
679
678
0, sspi->rx_irq_name, sspi);
680
679
if (ret) {
681
680
dev_err(&pdev->dev, "request rx_irq failed (%d)\n", ret);
682
-
goto put_spi;
681
+
goto disable_clk;
683
682
}
684
683
685
684
tx_irq = platform_get_irq(pdev, 1);
686
685
if (tx_irq <= 0) {
687
686
ret = tx_irq;
688
-
goto put_spi;
687
+
goto disable_clk;
689
688
}
690
689
snprintf(sspi->tx_irq_name, SYNQUACER_HSSPI_IRQ_NAME_MAX, "%s-tx",
691
690
dev_name(&pdev->dev));
···
693
692
0, sspi->tx_irq_name, sspi);
694
693
if (ret) {
695
694
dev_err(&pdev->dev, "request tx_irq failed (%d)\n", ret);
696
-
goto put_spi;
695
+
goto disable_clk;
697
696
}
698
697
699
698
master->dev.of_node = np;
···
711
710
712
711
ret = synquacer_spi_enable(master);
713
712
if (ret)
714
-
goto fail_enable;
713
+
goto disable_clk;
715
714
716
715
pm_runtime_set_active(sspi->dev);
717
716
pm_runtime_enable(sspi->dev);
···
724
723
725
724
disable_pm:
726
725
pm_runtime_disable(sspi->dev);
727
-
fail_enable:
726
+
disable_clk:
728
727
clk_disable_unprepare(sspi->clk);
729
728
put_spi:
730
729
spi_master_put(master);
+2
drivers/spi/spi-tegra114.c
+2
drivers/spi/spi-tegra114.c
···
966
966
967
967
ret = pm_runtime_get_sync(tspi->dev);
968
968
if (ret < 0) {
969
+
pm_runtime_put_noidle(tspi->dev);
969
970
dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
970
971
if (cdata)
971
972
tegra_spi_cleanup(spi);
···
1475
1474
1476
1475
ret = pm_runtime_get_sync(dev);
1477
1476
if (ret < 0) {
1477
+
pm_runtime_put_noidle(dev);
1478
1478
dev_err(dev, "pm runtime failed, e = %d\n", ret);
1479
1479
return ret;
1480
1480
}
+1
drivers/spi/spi-tegra20-sflash.c
+1
drivers/spi/spi-tegra20-sflash.c
+2
drivers/spi/spi-tegra20-slink.c
+2
drivers/spi/spi-tegra20-slink.c
···
751
751
752
752
ret = pm_runtime_get_sync(tspi->dev);
753
753
if (ret < 0) {
754
+
pm_runtime_put_noidle(tspi->dev);
754
755
dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
755
756
return ret;
756
757
}
···
1189
1188
1190
1189
ret = pm_runtime_get_sync(dev);
1191
1190
if (ret < 0) {
1191
+
pm_runtime_put_noidle(dev);
1192
1192
dev_err(dev, "pm runtime failed, e = %d\n", ret);
1193
1193
return ret;
1194
1194
}
+1
drivers/spi/spi-ti-qspi.c
+1
drivers/spi/spi-ti-qspi.c
+40
-30
drivers/spi/spi.c
+40
-30
drivers/spi/spi.c
···
374
374
return add_uevent_var(env, "MODALIAS=%s%s", SPI_MODULE_PREFIX, spi->modalias);
375
375
}
376
376
377
-
struct bus_type spi_bus_type = {
378
-
.name = "spi",
379
-
.dev_groups = spi_dev_groups,
380
-
.match = spi_match_device,
381
-
.uevent = spi_uevent,
382
-
};
383
-
EXPORT_SYMBOL_GPL(spi_bus_type);
384
-
385
-
386
-
static int spi_drv_probe(struct device *dev)
377
+
static int spi_probe(struct device *dev)
387
378
{
388
379
const struct spi_driver *sdrv = to_spi_driver(dev->driver);
389
380
struct spi_device *spi = to_spi_device(dev);
···
396
405
if (ret)
397
406
return ret;
398
407
399
-
ret = sdrv->probe(spi);
400
-
if (ret)
401
-
dev_pm_domain_detach(dev, true);
408
+
if (sdrv->probe) {
409
+
ret = sdrv->probe(spi);
410
+
if (ret)
411
+
dev_pm_domain_detach(dev, true);
412
+
}
402
413
403
414
return ret;
404
415
}
405
416
406
-
static int spi_drv_remove(struct device *dev)
417
+
static int spi_remove(struct device *dev)
407
418
{
408
419
const struct spi_driver *sdrv = to_spi_driver(dev->driver);
409
-
int ret;
410
420
411
-
ret = sdrv->remove(to_spi_device(dev));
421
+
if (sdrv->remove) {
422
+
int ret;
423
+
424
+
ret = sdrv->remove(to_spi_device(dev));
425
+
if (ret)
426
+
dev_warn(dev,
427
+
"Failed to unbind driver (%pe), ignoring\n",
428
+
ERR_PTR(ret));
429
+
}
430
+
412
431
dev_pm_domain_detach(dev, true);
413
432
414
-
return ret;
433
+
return 0;
415
434
}
416
435
417
-
static void spi_drv_shutdown(struct device *dev)
436
+
static void spi_shutdown(struct device *dev)
418
437
{
419
-
const struct spi_driver *sdrv = to_spi_driver(dev->driver);
438
+
if (dev->driver) {
439
+
const struct spi_driver *sdrv = to_spi_driver(dev->driver);
420
440
421
-
sdrv->shutdown(to_spi_device(dev));
441
+
if (sdrv->shutdown)
442
+
sdrv->shutdown(to_spi_device(dev));
443
+
}
422
444
}
445
+
446
+
struct bus_type spi_bus_type = {
447
+
.name = "spi",
448
+
.dev_groups = spi_dev_groups,
449
+
.match = spi_match_device,
450
+
.uevent = spi_uevent,
451
+
.probe = spi_probe,
452
+
.remove = spi_remove,
453
+
.shutdown = spi_shutdown,
454
+
};
455
+
EXPORT_SYMBOL_GPL(spi_bus_type);
423
456
424
457
/**
425
458
* __spi_register_driver - register a SPI driver
···
457
442
{
458
443
sdrv->driver.owner = owner;
459
444
sdrv->driver.bus = &spi_bus_type;
460
-
if (sdrv->probe)
461
-
sdrv->driver.probe = spi_drv_probe;
462
-
if (sdrv->remove)
463
-
sdrv->driver.remove = spi_drv_remove;
464
-
if (sdrv->shutdown)
465
-
sdrv->driver.shutdown = spi_drv_shutdown;
466
445
return driver_register(&sdrv->driver);
467
446
}
468
447
EXPORT_SYMBOL_GPL(__spi_register_driver);
···
3247
3238
}
3248
3239
3249
3240
/**
3250
-
* spi_split_tranfers_maxsize - split spi transfers into multiple transfers
3251
-
* when an individual transfer exceeds a
3252
-
* certain size
3241
+
* spi_split_transfers_maxsize - split spi transfers into multiple transfers
3242
+
* when an individual transfer exceeds a
3243
+
* certain size
3253
3244
* @ctlr: the @spi_controller for this transfer
3254
3245
* @msg: the @spi_message to transform
3255
3246
* @maxsize: the maximum when to apply this
···
3378
3369
if (status)
3379
3370
return status;
3380
3371
3381
-
if (!spi->max_speed_hz)
3372
+
if (!spi->max_speed_hz ||
3373
+
spi->max_speed_hz > spi->controller->max_speed_hz)
3382
3374
spi->max_speed_hz = spi->controller->max_speed_hz;
3383
3375
3384
3376
mutex_lock(&spi->controller->io_mutex);
+1
include/linux/spi/spi.h
+1
include/linux/spi/spi.h
···
171
171
#define SPI_MODE_1 (0|SPI_CPHA)
172
172
#define SPI_MODE_2 (SPI_CPOL|0)
173
173
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
174
+
#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA)
174
175
#define SPI_CS_HIGH 0x04 /* chipselect active high? */
175
176
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
176
177
#define SPI_3WIRE 0x10 /* SI/SO signals shared */