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phy: qcom-qmp-combo: cleanup the driver

Remove the conditionals and options that are not used by any of combo
USB+DP PHY devices.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220607213203.2819885-20-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 6066bac1 86f5dddd

+10 -159
+10 -159
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 616 616 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 617 617 const struct qmp_phy_init_tbl *serdes_tbl; 618 618 int serdes_tbl_num; 619 - const struct qmp_phy_init_tbl *serdes_tbl_sec; 620 - int serdes_tbl_num_sec; 621 619 const struct qmp_phy_init_tbl *tx_tbl; 622 620 int tx_tbl_num; 623 - const struct qmp_phy_init_tbl *tx_tbl_sec; 624 - int tx_tbl_num_sec; 625 621 const struct qmp_phy_init_tbl *rx_tbl; 626 622 int rx_tbl_num; 627 - const struct qmp_phy_init_tbl *rx_tbl_sec; 628 - int rx_tbl_num_sec; 629 623 const struct qmp_phy_init_tbl *pcs_tbl; 630 624 int pcs_tbl_num; 631 - const struct qmp_phy_init_tbl *pcs_tbl_sec; 632 - int pcs_tbl_num_sec; 633 - const struct qmp_phy_init_tbl *pcs_misc_tbl; 634 - int pcs_misc_tbl_num; 635 - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 636 - int pcs_misc_tbl_num_sec; 637 625 638 626 /* Init sequence for DP PHY block link rates */ 639 627 const struct qmp_phy_init_tbl *serdes_tbl_rbr; ··· 654 666 655 667 unsigned int start_ctrl; 656 668 unsigned int pwrdn_ctrl; 657 - unsigned int mask_com_pcs_ready; 658 669 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 659 670 unsigned int phy_status; 660 671 661 - /* true, if PHY has a separate PHY_COM control block */ 662 - bool has_phy_com_ctrl; 663 - /* true, if PHY has a reset for individual lanes */ 664 - bool has_lane_rst; 665 672 /* true, if PHY needs delay after POWER_DOWN */ 666 673 bool has_pwrdn_delay; 667 674 /* power_down delay in usec */ ··· 667 684 bool has_phy_dp_com_ctrl; 668 685 /* true, if PHY has secondary tx/rx lanes to be configured */ 669 686 bool is_dual_lane_phy; 670 - 671 - /* true, if PCS block has no separate SW_RESET register */ 672 - bool no_pcs_sw_reset; 673 687 }; 674 688 675 689 struct qmp_phy_combo_cfg { ··· 1064 1084 1065 1085 static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) 1066 1086 { 1067 - struct qcom_qmp *qmp = qphy->qmp; 1068 1087 const struct qmp_phy_cfg *cfg = qphy->cfg; 1069 1088 void __iomem *serdes = qphy->serdes; 1070 1089 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1071 1090 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1072 1091 int serdes_tbl_num = cfg->serdes_tbl_num; 1073 - int ret; 1074 1092 1075 1093 qcom_qmp_phy_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1076 - if (cfg->serdes_tbl_sec) 1077 - qcom_qmp_phy_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 1078 - cfg->serdes_tbl_num_sec); 1079 1094 1080 1095 if (cfg->type == PHY_TYPE_DP) { 1081 1096 switch (dp_opts->link_rate) { ··· 1097 1122 default: 1098 1123 /* Other link rates aren't supported */ 1099 1124 return -EINVAL; 1100 - } 1101 - } 1102 - 1103 - 1104 - if (cfg->has_phy_com_ctrl) { 1105 - void __iomem *status; 1106 - unsigned int mask, val; 1107 - 1108 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 1109 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1110 - SERDES_START | PCS_START); 1111 - 1112 - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 1113 - mask = cfg->mask_com_pcs_ready; 1114 - 1115 - ret = readl_poll_timeout(status, val, (val & mask), 10, 1116 - PHY_INIT_COMPLETE_TIMEOUT); 1117 - if (ret) { 1118 - dev_err(qmp->dev, 1119 - "phy common block init timed-out\n"); 1120 - return ret; 1121 1125 } 1122 1126 } 1123 1127 ··· 1584 1630 { 1585 1631 struct qcom_qmp *qmp = qphy->qmp; 1586 1632 const struct qmp_phy_cfg *cfg = qphy->cfg; 1587 - void __iomem *serdes = qphy->serdes; 1588 1633 void __iomem *pcs = qphy->pcs; 1589 1634 void __iomem *dp_com = qmp->dp_com; 1590 1635 int ret, i; ··· 1646 1693 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1647 1694 } 1648 1695 1649 - if (cfg->has_phy_com_ctrl) { 1650 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1651 - SW_PWRDN); 1652 - } else { 1653 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1654 - qphy_setbits(pcs, 1655 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1656 - cfg->pwrdn_ctrl); 1657 - else 1658 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1659 - cfg->pwrdn_ctrl); 1660 - } 1696 + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1697 + qphy_setbits(pcs, 1698 + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1699 + cfg->pwrdn_ctrl); 1700 + else 1701 + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1702 + cfg->pwrdn_ctrl); 1661 1703 1662 1704 mutex_unlock(&qmp->phy_mutex); 1663 1705 ··· 1673 1725 { 1674 1726 struct qcom_qmp *qmp = qphy->qmp; 1675 1727 const struct qmp_phy_cfg *cfg = qphy->cfg; 1676 - void __iomem *serdes = qphy->serdes; 1677 1728 int i = cfg->num_resets; 1678 1729 1679 1730 mutex_lock(&qmp->phy_mutex); ··· 1682 1735 } 1683 1736 1684 1737 reset_control_assert(qmp->ufs_reset); 1685 - if (cfg->has_phy_com_ctrl) { 1686 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1687 - SERDES_START | PCS_START); 1688 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 1689 - SW_RESET); 1690 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1691 - SW_PWRDN); 1692 - } 1693 1738 1694 1739 while (--i >= 0) 1695 1740 reset_control_assert(qmp->resets[i]); ··· 1703 1764 int ret; 1704 1765 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1705 1766 1706 - if (cfg->no_pcs_sw_reset) { 1707 - /* 1708 - * Get UFS reset, which is delayed until now to avoid a 1709 - * circular dependency where UFS needs its PHY, but the PHY 1710 - * needs this UFS reset. 1711 - */ 1712 - if (!qmp->ufs_reset) { 1713 - qmp->ufs_reset = 1714 - devm_reset_control_get_exclusive(qmp->dev, 1715 - "ufsphy"); 1716 - 1717 - if (IS_ERR(qmp->ufs_reset)) { 1718 - ret = PTR_ERR(qmp->ufs_reset); 1719 - dev_err(qmp->dev, 1720 - "failed to get UFS reset: %d\n", 1721 - ret); 1722 - 1723 - qmp->ufs_reset = NULL; 1724 - return ret; 1725 - } 1726 - } 1727 - 1728 - ret = reset_control_assert(qmp->ufs_reset); 1729 - if (ret) 1730 - return ret; 1731 - } 1732 - 1733 1767 ret = qcom_qmp_phy_combo_com_init(qphy); 1734 1768 if (ret) 1735 1769 return ret; ··· 1721 1809 void __iomem *tx = qphy->tx; 1722 1810 void __iomem *rx = qphy->rx; 1723 1811 void __iomem *pcs = qphy->pcs; 1724 - void __iomem *pcs_misc = qphy->pcs_misc; 1725 1812 void __iomem *status; 1726 1813 unsigned int mask, val, ready; 1727 1814 int ret; 1728 1815 1729 1816 qcom_qmp_phy_combo_serdes_init(qphy); 1730 1817 1731 - if (cfg->has_lane_rst) { 1732 - ret = reset_control_deassert(qphy->lane_rst); 1733 - if (ret) { 1734 - dev_err(qmp->dev, "lane%d reset deassert failed\n", 1735 - qphy->index); 1736 - return ret; 1737 - } 1738 - } 1739 - 1740 1818 ret = clk_prepare_enable(qphy->pipe_clk); 1741 1819 if (ret) { 1742 1820 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1743 - goto err_reset_lane; 1821 + return ret; 1744 1822 } 1745 1823 1746 1824 /* Tx, Rx, and PCS configurations */ 1747 1825 qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, 1748 1826 cfg->tx_tbl, cfg->tx_tbl_num, 1); 1749 - if (cfg->tx_tbl_sec) 1750 - qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 1751 - cfg->tx_tbl_num_sec, 1); 1752 1827 1753 1828 /* Configuration for other LANE for USB-DP combo PHY */ 1754 1829 if (cfg->is_dual_lane_phy) { 1755 1830 qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, 1756 1831 cfg->tx_tbl, cfg->tx_tbl_num, 2); 1757 - if (cfg->tx_tbl_sec) 1758 - qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, 1759 - cfg->tx_tbl_sec, 1760 - cfg->tx_tbl_num_sec, 2); 1761 1832 } 1762 1833 1763 1834 /* Configure special DP tx tunings */ ··· 1749 1854 1750 1855 qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, 1751 1856 cfg->rx_tbl, cfg->rx_tbl_num, 1); 1752 - if (cfg->rx_tbl_sec) 1753 - qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, 1754 - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 1755 1857 1756 1858 if (cfg->is_dual_lane_phy) { 1757 1859 qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, 1758 1860 cfg->rx_tbl, cfg->rx_tbl_num, 2); 1759 - if (cfg->rx_tbl_sec) 1760 - qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, 1761 - cfg->rx_tbl_sec, 1762 - cfg->rx_tbl_num_sec, 2); 1763 1861 } 1764 1862 1765 1863 /* Configure link rate, swing, etc. */ ··· 1760 1872 cfg->configure_dp_phy(qphy); 1761 1873 } else { 1762 1874 qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1763 - if (cfg->pcs_tbl_sec) 1764 - qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 1765 - cfg->pcs_tbl_num_sec); 1766 1875 } 1767 1876 1768 1877 ret = reset_control_deassert(qmp->ufs_reset); 1769 1878 if (ret) 1770 1879 goto err_disable_pipe_clk; 1771 1880 1772 - qcom_qmp_phy_combo_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 1773 - cfg->pcs_misc_tbl_num); 1774 - if (cfg->pcs_misc_tbl_sec) 1775 - qcom_qmp_phy_combo_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 1776 - cfg->pcs_misc_tbl_num_sec); 1777 - 1778 1881 if (cfg->has_pwrdn_delay) 1779 1882 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1780 1883 1781 1884 if (cfg->type != PHY_TYPE_DP) { 1782 1885 /* Pull PHY out of reset state */ 1783 - if (!cfg->no_pcs_sw_reset) 1784 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1886 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1785 1887 /* start SerDes and Phy-Coding-Sublayer */ 1786 1888 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1787 1889 ··· 1790 1912 1791 1913 err_disable_pipe_clk: 1792 1914 clk_disable_unprepare(qphy->pipe_clk); 1793 - err_reset_lane: 1794 - if (cfg->has_lane_rst) 1795 - reset_control_assert(qphy->lane_rst); 1796 1915 1797 1916 return ret; 1798 1917 } ··· 1806 1931 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1807 1932 } else { 1808 1933 /* PHY reset */ 1809 - if (!cfg->no_pcs_sw_reset) 1810 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1934 + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1811 1935 1812 1936 /* stop SerDes and Phy-Coding-Sublayer */ 1813 1937 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ··· 1827 1953 static int qcom_qmp_phy_combo_exit(struct phy *phy) 1828 1954 { 1829 1955 struct qmp_phy *qphy = phy_get_drvdata(phy); 1830 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1831 - 1832 - if (cfg->has_lane_rst) 1833 - reset_control_assert(qphy->lane_rst); 1834 1956 1835 1957 qcom_qmp_phy_combo_com_exit(qphy); 1836 1958 ··· 2301 2431 .owner = THIS_MODULE, 2302 2432 }; 2303 2433 2304 - static void qcom_qmp_reset_control_put(void *data) 2305 - { 2306 - reset_control_put(data); 2307 - } 2308 - 2309 2434 static 2310 2435 int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id, 2311 2436 void __iomem *serdes, const struct qmp_phy_cfg *cfg) ··· 2384 2519 return ret; 2385 2520 } 2386 2521 qphy->pipe_clk = NULL; 2387 - } 2388 - 2389 - /* Get lane reset, if any */ 2390 - if (cfg->has_lane_rst) { 2391 - snprintf(prop_name, sizeof(prop_name), "lane%d", id); 2392 - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 2393 - if (IS_ERR(qphy->lane_rst)) { 2394 - dev_err(dev, "failed to get lane%d reset\n", id); 2395 - return PTR_ERR(qphy->lane_rst); 2396 - } 2397 - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 2398 - qphy->lane_rst); 2399 - if (ret) 2400 - return ret; 2401 2522 } 2402 2523 2403 2524 if (cfg->type == PHY_TYPE_DP)