phy: qcom-qmp-usb: drop support for non-USB PHY types

+48 -387

1 changed file

expand all

drivers

phy

qualcomm

phy-qcom-qmp-usb.c

+48 -387

drivers/phy/qualcomm/phy-qcom-qmp-usb.c

··· 2059 2059 struct qcom_qmp *qmp = qphy->qmp; 2060 2060 const struct qmp_phy_cfg *cfg = qphy->cfg; 2061 2061 void __iomem *serdes = qphy->serdes; 2062 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 2063 2062 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 2064 2063 int serdes_tbl_num = cfg->serdes_tbl_num; 2065 2064 int ret; ··· 2067 2068 if (cfg->serdes_tbl_sec) 2068 2069 qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 2069 2070 cfg->serdes_tbl_num_sec); 2070 - 2071 - if (cfg->type == PHY_TYPE_DP) { 2072 - switch (dp_opts->link_rate) { 2073 - case 1620: 2074 - qcom_qmp_phy_usb_configure(serdes, cfg->regs, 2075 - cfg->serdes_tbl_rbr, 2076 - cfg->serdes_tbl_rbr_num); 2077 - break; 2078 - case 2700: 2079 - qcom_qmp_phy_usb_configure(serdes, cfg->regs, 2080 - cfg->serdes_tbl_hbr, 2081 - cfg->serdes_tbl_hbr_num); 2082 - break; 2083 - case 5400: 2084 - qcom_qmp_phy_usb_configure(serdes, cfg->regs, 2085 - cfg->serdes_tbl_hbr2, 2086 - cfg->serdes_tbl_hbr2_num); 2087 - break; 2088 - case 8100: 2089 - qcom_qmp_phy_usb_configure(serdes, cfg->regs, 2090 - cfg->serdes_tbl_hbr3, 2091 - cfg->serdes_tbl_hbr3_num); 2092 - break; 2093 - default: 2094 - /* Other link rates aren't supported */ 2095 - return -EINVAL; 2096 - } 2097 - } 2098 - 2099 2071 2100 2072 if (cfg->has_phy_com_ctrl) { 2101 2073 void __iomem *status; ··· 2087 2117 return ret; 2088 2118 } 2089 2119 } 2090 - 2091 - return 0; 2092 - } 2093 - 2094 - static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 2095 - { 2096 - const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2097 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2098 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2099 - 2100 - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 2101 - if (qphy->dp_opts.set_voltages) { 2102 - cfg->configure_dp_tx(qphy); 2103 - qphy->dp_opts.set_voltages = 0; 2104 - } 2105 - 2106 - return 0; 2107 - } 2108 - 2109 - static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 2110 - { 2111 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2112 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2113 - 2114 - if (cfg->calibrate_dp_phy) 2115 - return cfg->calibrate_dp_phy(qphy); 2116 2120 2117 2121 return 0; 2118 2122 } ··· 2260 2316 if (ret) 2261 2317 return ret; 2262 2318 2263 - if (cfg->type == PHY_TYPE_DP) 2264 - cfg->dp_aux_init(qphy); 2265 - 2266 2319 return 0; 2267 2320 } 2268 2321 ··· 2310 2369 cfg->tx_tbl_num_sec, 2); 2311 2370 } 2312 2371 2313 - /* Configure special DP tx tunings */ 2314 - if (cfg->type == PHY_TYPE_DP) 2315 - cfg->configure_dp_tx(qphy); 2316 - 2317 2372 qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, 2318 2373 cfg->rx_tbl, cfg->rx_tbl_num, 1); 2319 2374 if (cfg->rx_tbl_sec) ··· 2326 2389 } 2327 2390 2328 2391 /* Configure link rate, swing, etc. */ 2329 - if (cfg->type == PHY_TYPE_DP) { 2330 - cfg->configure_dp_phy(qphy); 2331 - } else { 2332 - qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2333 - if (cfg->pcs_tbl_sec) 2334 - qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 2335 - cfg->pcs_tbl_num_sec); 2336 - } 2392 + qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2393 + if (cfg->pcs_tbl_sec) 2394 + qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 2395 + cfg->pcs_tbl_num_sec); 2337 2396 2338 2397 ret = reset_control_deassert(qmp->ufs_reset); 2339 2398 if (ret) ··· 2341 2408 qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 2342 2409 cfg->pcs_misc_tbl_num_sec); 2343 2410 2344 - /* 2345 - * Pull out PHY from POWER DOWN state. 2346 - * This is active low enable signal to power-down PHY. 2347 - */ 2348 - if(cfg->type == PHY_TYPE_PCIE) 2349 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 2350 - 2351 2411 if (cfg->has_pwrdn_delay) 2352 2412 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2353 2413 2354 - if (cfg->type != PHY_TYPE_DP) { 2355 - /* Pull PHY out of reset state */ 2356 - if (!cfg->no_pcs_sw_reset) 2357 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2358 - /* start SerDes and Phy-Coding-Sublayer */ 2359 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2414 + /* Pull PHY out of reset state */ 2415 + if (!cfg->no_pcs_sw_reset) 2416 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2417 + /* start SerDes and Phy-Coding-Sublayer */ 2418 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2360 2419 2361 - if (cfg->type == PHY_TYPE_UFS) { 2362 - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 2363 - mask = PCS_READY; 2364 - ready = PCS_READY; 2365 - } else { 2366 - status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2367 - mask = cfg->phy_status; 2368 - ready = 0; 2369 - } 2420 + status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2421 + mask = cfg->phy_status; 2422 + ready = 0; 2370 2423 2371 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2372 - PHY_INIT_COMPLETE_TIMEOUT); 2373 - if (ret) { 2374 - dev_err(qmp->dev, "phy initialization timed-out\n"); 2375 - goto err_disable_pipe_clk; 2376 - } 2424 + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2425 + PHY_INIT_COMPLETE_TIMEOUT); 2426 + if (ret) { 2427 + dev_err(qmp->dev, "phy initialization timed-out\n"); 2428 + goto err_disable_pipe_clk; 2377 2429 } 2430 + 2378 2431 return 0; 2379 2432 2380 2433 err_disable_pipe_clk: ··· 2379 2460 2380 2461 clk_disable_unprepare(qphy->pipe_clk); 2381 2462 2382 - if (cfg->type == PHY_TYPE_DP) { 2383 - /* Assert DP PHY power down */ 2384 - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 2463 + /* PHY reset */ 2464 + if (!cfg->no_pcs_sw_reset) 2465 + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2466 + 2467 + /* stop SerDes and Phy-Coding-Sublayer */ 2468 + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2469 + 2470 + /* Put PHY into POWER DOWN state: active low */ 2471 + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2472 + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2473 + cfg->pwrdn_ctrl); 2385 2474 } else { 2386 - /* PHY reset */ 2387 - if (!cfg->no_pcs_sw_reset) 2388 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2389 - 2390 - /* stop SerDes and Phy-Coding-Sublayer */ 2391 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2392 - 2393 - /* Put PHY into POWER DOWN state: active low */ 2394 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2395 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2396 - cfg->pwrdn_ctrl); 2397 - } else { 2398 - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 2399 - cfg->pwrdn_ctrl); 2400 - } 2475 + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 2476 + cfg->pwrdn_ctrl); 2401 2477 } 2402 2478 2403 2479 return 0; ··· 2669 2755 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2670 2756 } 2671 2757 2672 - /* 2673 - * Display Port PLL driver block diagram for branch clocks 2674 - * 2675 - * +------------------------------+ 2676 - * | DP_VCO_CLK | 2677 - * | | 2678 - * | +-------------------+ | 2679 - * | | (DP PLL/VCO) | | 2680 - * | +---------+---------+ | 2681 - * | v | 2682 - * | +----------+-----------+ | 2683 - * | | hsclk_divsel_clk_src | | 2684 - * | +----------+-----------+ | 2685 - * +------------------------------+ 2686 - * | 2687 - * +---------<---------v------------>----------+ 2688 - * | | 2689 - * +--------v----------------+ | 2690 - * | dp_phy_pll_link_clk | | 2691 - * | link_clk | | 2692 - * +--------+----------------+ | 2693 - * | | 2694 - * | | 2695 - * v v 2696 - * Input to DISPCC block | 2697 - * for link clk, crypto clk | 2698 - * and interface clock | 2699 - * | 2700 - * | 2701 - * +--------<------------+-----------------+---<---+ 2702 - * | | | 2703 - * +----v---------+ +--------v-----+ +--------v------+ 2704 - * | vco_divided | | vco_divided | | vco_divided | 2705 - * | _clk_src | | _clk_src | | _clk_src | 2706 - * | | | | | | 2707 - * |divsel_six | | divsel_two | | divsel_four | 2708 - * +-------+------+ +-----+--------+ +--------+------+ 2709 - * | | | 2710 - * v---->----------v-------------<------v 2711 - * | 2712 - * +----------+-----------------+ 2713 - * | dp_phy_pll_vco_div_clk | 2714 - * +---------+------------------+ 2715 - * | 2716 - * v 2717 - * Input to DISPCC block 2718 - * for DP pixel clock 2719 - * 2720 - */ 2721 - static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 2722 - struct clk_rate_request *req) 2723 - { 2724 - switch (req->rate) { 2725 - case 1620000000UL / 2: 2726 - case 2700000000UL / 2: 2727 - /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2728 - return 0; 2729 - default: 2730 - return -EINVAL; 2731 - } 2732 - } 2733 - 2734 - static unsigned long 2735 - qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2736 - { 2737 - const struct qmp_phy_dp_clks *dp_clks; 2738 - const struct qmp_phy *qphy; 2739 - const struct phy_configure_opts_dp *dp_opts; 2740 - 2741 - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 2742 - qphy = dp_clks->qphy; 2743 - dp_opts = &qphy->dp_opts; 2744 - 2745 - switch (dp_opts->link_rate) { 2746 - case 1620: 2747 - return 1620000000UL / 2; 2748 - case 2700: 2749 - return 2700000000UL / 2; 2750 - case 5400: 2751 - return 5400000000UL / 4; 2752 - case 8100: 2753 - return 8100000000UL / 6; 2754 - default: 2755 - return 0; 2756 - } 2757 - } 2758 - 2759 - static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 2760 - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 2761 - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 2762 - }; 2763 - 2764 - static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 2765 - struct clk_rate_request *req) 2766 - { 2767 - switch (req->rate) { 2768 - case 162000000: 2769 - case 270000000: 2770 - case 540000000: 2771 - case 810000000: 2772 - return 0; 2773 - default: 2774 - return -EINVAL; 2775 - } 2776 - } 2777 - 2778 - static unsigned long 2779 - qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2780 - { 2781 - const struct qmp_phy_dp_clks *dp_clks; 2782 - const struct qmp_phy *qphy; 2783 - const struct phy_configure_opts_dp *dp_opts; 2784 - 2785 - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 2786 - qphy = dp_clks->qphy; 2787 - dp_opts = &qphy->dp_opts; 2788 - 2789 - switch (dp_opts->link_rate) { 2790 - case 1620: 2791 - case 2700: 2792 - case 5400: 2793 - case 8100: 2794 - return dp_opts->link_rate * 100000; 2795 - default: 2796 - return 0; 2797 - } 2798 - } 2799 - 2800 - static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 2801 - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 2802 - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 2803 - }; 2804 - 2805 - static struct clk_hw * 2806 - qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2807 - { 2808 - struct qmp_phy_dp_clks *dp_clks = data; 2809 - unsigned int idx = clkspec->args[0]; 2810 - 2811 - if (idx >= 2) { 2812 - pr_err("%s: invalid index %u\n", __func__, idx); 2813 - return ERR_PTR(-EINVAL); 2814 - } 2815 - 2816 - if (idx == 0) 2817 - return &dp_clks->dp_link_hw; 2818 - 2819 - return &dp_clks->dp_pixel_hw; 2820 - } 2821 - 2822 - static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 2823 - struct device_node *np) 2824 - { 2825 - struct clk_init_data init = { }; 2826 - struct qmp_phy_dp_clks *dp_clks; 2827 - char name[64]; 2828 - int ret; 2829 - 2830 - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 2831 - if (!dp_clks) 2832 - return -ENOMEM; 2833 - 2834 - dp_clks->qphy = qphy; 2835 - qphy->dp_clks = dp_clks; 2836 - 2837 - snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 2838 - init.ops = &qcom_qmp_dp_link_clk_ops; 2839 - init.name = name; 2840 - dp_clks->dp_link_hw.init = &init; 2841 - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 2842 - if (ret) 2843 - return ret; 2844 - 2845 - snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 2846 - init.ops = &qcom_qmp_dp_pixel_clk_ops; 2847 - init.name = name; 2848 - dp_clks->dp_pixel_hw.init = &init; 2849 - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 2850 - if (ret) 2851 - return ret; 2852 - 2853 - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 2854 - if (ret) 2855 - return ret; 2856 - 2857 - /* 2858 - * Roll a devm action because the clock provider is the child node, but 2859 - * the child node is not actually a device. 2860 - */ 2861 - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2862 - } 2863 - 2864 - static const struct phy_ops qcom_qmp_phy_usb_gen_ops = { 2758 + static const struct phy_ops qcom_qmp_phy_usb_ops = { 2865 2759 .init = qcom_qmp_phy_usb_enable, 2866 2760 .exit = qcom_qmp_phy_usb_disable, 2867 - .set_mode = qcom_qmp_phy_usb_set_mode, 2868 - .owner = THIS_MODULE, 2869 - }; 2870 - 2871 - static const struct phy_ops qcom_qmp_phy_usb_dp_ops = { 2872 - .init = qcom_qmp_phy_usb_init, 2873 - .configure = qcom_qmp_dp_phy_configure, 2874 - .power_on = qcom_qmp_phy_usb_power_on, 2875 - .calibrate = qcom_qmp_dp_phy_calibrate, 2876 - .power_off = qcom_qmp_phy_usb_power_off, 2877 - .exit = qcom_qmp_phy_usb_exit, 2878 - .set_mode = qcom_qmp_phy_usb_set_mode, 2879 - .owner = THIS_MODULE, 2880 - }; 2881 - 2882 - static const struct phy_ops qcom_qmp_pcie_ufs_ops = { 2883 - .power_on = qcom_qmp_phy_usb_enable, 2884 - .power_off = qcom_qmp_phy_usb_disable, 2885 2761 .set_mode = qcom_qmp_phy_usb_set_mode, 2886 2762 .owner = THIS_MODULE, 2887 2763 }; ··· 2688 2984 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2689 2985 struct phy *generic_phy; 2690 2986 struct qmp_phy *qphy; 2691 - const struct phy_ops *ops; 2692 2987 char prop_name[MAX_PROP_NAME]; 2693 2988 int ret; 2694 2989 ··· 2754 3051 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 2755 3052 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 2756 3053 if (IS_ERR(qphy->pipe_clk)) { 2757 - if (cfg->type == PHY_TYPE_PCIE || 2758 - cfg->type == PHY_TYPE_USB3) { 2759 - ret = PTR_ERR(qphy->pipe_clk); 2760 - if (ret != -EPROBE_DEFER) 2761 - dev_err(dev, 2762 - "failed to get lane%d pipe_clk, %d\n", 2763 - id, ret); 2764 - return ret; 2765 - } 2766 - qphy->pipe_clk = NULL; 3054 + ret = PTR_ERR(qphy->pipe_clk); 3055 + if (ret != -EPROBE_DEFER) 3056 + dev_err(dev, 3057 + "failed to get lane%d pipe_clk, %d\n", 3058 + id, ret); 3059 + return ret; 2767 3060 } 2768 3061 2769 3062 /* Get lane reset, if any */ ··· 2776 3077 return ret; 2777 3078 } 2778 3079 2779 - if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) 2780 - ops = &qcom_qmp_pcie_ufs_ops; 2781 - else if (cfg->type == PHY_TYPE_DP) 2782 - ops = &qcom_qmp_phy_usb_dp_ops; 2783 - else 2784 - ops = &qcom_qmp_phy_usb_gen_ops; 2785 - 2786 - generic_phy = devm_phy_create(dev, np, ops); 3080 + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); 2787 3081 if (IS_ERR(generic_phy)) { 2788 3082 ret = PTR_ERR(generic_phy); 2789 3083 dev_err(dev, "failed to create qphy %d\n", ret); ··· 2864 3172 struct device_node *child; 2865 3173 struct phy_provider *phy_provider; 2866 3174 void __iomem *serdes; 2867 - void __iomem *usb_serdes; 2868 - void __iomem *dp_serdes = NULL; 2869 - const struct qmp_phy_combo_cfg *combo_cfg = NULL; 2870 3175 const struct qmp_phy_cfg *cfg = NULL; 2871 - const struct qmp_phy_cfg *usb_cfg = NULL; 2872 - const struct qmp_phy_cfg *dp_cfg = NULL; 2873 3176 int num, id, expected_phys; 2874 3177 int ret; 2875 3178 ··· 2881 3194 return -EINVAL; 2882 3195 2883 3196 /* per PHY serdes; usually located at base address */ 2884 - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 3197 + serdes = devm_platform_ioremap_resource(pdev, 0); 2885 3198 if (IS_ERR(serdes)) 2886 3199 return PTR_ERR(serdes); 2887 3200 2888 3201 /* per PHY dp_com; if PHY has dp_com control block */ 2889 - if (combo_cfg || cfg->has_phy_dp_com_ctrl) { 3202 + if (cfg->has_phy_dp_com_ctrl) { 2890 3203 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2891 3204 if (IS_ERR(qmp->dp_com)) 2892 3205 return PTR_ERR(qmp->dp_com); 2893 3206 } 2894 3207 2895 - if (combo_cfg) { 2896 - /* Only two serdes for combo PHY */ 2897 - dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2898 - if (IS_ERR(dp_serdes)) 2899 - return PTR_ERR(dp_serdes); 2900 - 2901 - dp_cfg = combo_cfg->dp_cfg; 2902 - expected_phys = 2; 2903 - } else { 2904 - expected_phys = cfg->nlanes; 2905 - } 3208 + expected_phys = cfg->nlanes; 2906 3209 2907 3210 mutex_init(&qmp->phy_mutex); 2908 3211 ··· 2931 3254 2932 3255 id = 0; 2933 3256 for_each_available_child_of_node(dev->of_node, child) { 2934 - if (of_node_name_eq(child, "dp-phy")) { 2935 - cfg = dp_cfg; 2936 - serdes = dp_serdes; 2937 - } else if (of_node_name_eq(child, "usb3-phy")) { 2938 - cfg = usb_cfg; 2939 - serdes = usb_serdes; 2940 - } 2941 - 2942 3257 /* Create per-lane phy */ 2943 3258 ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg); 2944 3259 if (ret) { ··· 2943 3274 * Register the pipe clock provided by phy. 2944 3275 * See function description to see details of this pipe clock. 2945 3276 */ 2946 - if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { 2947 - ret = phy_pipe_clk_register(qmp, child); 2948 - if (ret) { 2949 - dev_err(qmp->dev, 2950 - "failed to register pipe clock source\n"); 2951 - goto err_node_put; 2952 - } 2953 - } else if (cfg->type == PHY_TYPE_DP) { 2954 - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 2955 - if (ret) { 2956 - dev_err(qmp->dev, 2957 - "failed to register DP clock source\n"); 2958 - goto err_node_put; 2959 - } 3277 + ret = phy_pipe_clk_register(qmp, child); 3278 + if (ret) { 3279 + dev_err(qmp->dev, 3280 + "failed to register pipe clock source\n"); 3281 + goto err_node_put; 2960 3282 } 3283 + 2961 3284 id++; 2962 3285 } 2963 3286

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