Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm: perf/kvm: Use GENMASK for ARMV8_PMU_PMCR_N
This is so that FIELD_GET and FIELD_PREP can be used and that the fields
are in a consistent format to arm64/tools/sysreg
Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20231211161331.1277825-3-james.clark@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
authored by
James Clark
and committed by
Will Deacon
62e1f212
9343c790
+8
-11
+3
-5
arch/arm64/kvm/pmu-emul.c
+3
-5
arch/arm64/kvm/pmu-emul.c
···
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u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
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{
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u64 val = kvm_vcpu_read_pmcr(vcpu) >> ARMV8_PMU_PMCR_N_SHIFT;
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u64 val = FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu));
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val &= ARMV8_PMU_PMCR_N_MASK;
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if (val == 0)
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return BIT(ARMV8_PMU_CYCLE_IDX);
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else
···
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*/
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u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu)
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{
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u64 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0) &
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~(ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT);
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u64 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
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return pmcr | ((u64)vcpu->kvm->arch.pmcr_n << ARMV8_PMU_PMCR_N_SHIFT);
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return u64_replace_bits(pmcr, vcpu->kvm->arch.pmcr_n, ARMV8_PMU_PMCR_N);
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}
+2
-2
arch/arm64/kvm/sys_regs.c
+2
-2
arch/arm64/kvm/sys_regs.c
···
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u64 pmcr, val;
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pmcr = kvm_vcpu_read_pmcr(vcpu);
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val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
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val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr);
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if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
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kvm_inject_undefined(vcpu);
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return false;
···
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static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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u8 new_n = (val >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
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u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val);
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struct kvm *kvm = vcpu->kvm;
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mutex_lock(&kvm->arch.config_lock);
+2
-2
drivers/perf/arm_pmuv3.c
+2
-2
drivers/perf/arm_pmuv3.c
···
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#include <clocksource/arm_arch_timer.h>
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/clocksource.h>
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#include <linux/of.h>
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#include <linux/perf/arm_pmu.h>
···
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probe->present = true;
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/* Read the nb of CNTx counters supported from PMNC */
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cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
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& ARMV8_PMU_PMCR_N_MASK;
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cpu_pmu->num_events = FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read());
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/* Add the CPU cycles counter */
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cpu_pmu->num_events += 1;
+1
-2
include/linux/perf/arm_pmuv3.h
+1
-2
include/linux/perf/arm_pmuv3.h
···
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#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
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#define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */
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#define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */
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#define ARMV8_PMU_PMCR_N_MASK 0x1f
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#define ARMV8_PMU_PMCR_N GENMASK(15, 11) /* Number of counters supported */
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#define ARMV8_PMU_PMCR_MASK 0xff /* Mask for writable bits */
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/*