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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mxc_nand: do not depend on disabling the irq in the interrupt handler
This patch reverts the driver to enabling/disabling the NFC interrupt
mask rather than enabling/disabling the system interrupt. This cleans
up the driver so that it doesn't rely on interrupts being disabled
within the interrupt handler.
For i.MX21 we keep the current behaviour, that is calling
enable_irq/disable_irq_nosync to enable/disable interrupts. This patch
is based on earlier work by John Ogness.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: John Ogness <john.ogness@linutronix.de>
Tested-by: John Ogness <john.ogness@linutronix.de>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
authored by
Sascha Hauer
and committed by
Linus Torvalds
63f1474c
f68c834b
+83
-9
+83
-9
drivers/mtd/nand/mxc_nand.c
+83
-9
drivers/mtd/nand/mxc_nand.c
···
30
30
#include <linux/clk.h>
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31
#include <linux/err.h>
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32
#include <linux/io.h>
33
+
#include <linux/irq.h>
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+
#include <linux/completion.h>
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#include <asm/mach/flash.h>
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#include <mach/mxc_nand.h>
···
153
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int irq;
154
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int eccsize;
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153
156
-
wait_queue_head_t irq_waitq;
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+
struct completion op_completion;
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uint8_t *data_buf;
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unsigned int buf_start;
···
166
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void (*send_read_id)(struct mxc_nand_host *);
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uint16_t (*get_dev_status)(struct mxc_nand_host *);
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int (*check_int)(struct mxc_nand_host *);
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+
void (*irq_control)(struct mxc_nand_host *, int);
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};
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/* OOB placement block for use with hardware ecc generation */
···
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{
220
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struct mxc_nand_host *host = dev_id;
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222
-
disable_irq_nosync(irq);
219
+
if (!host->check_int(host))
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return IRQ_NONE;
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221
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-
wake_up(&host->irq_waitq);
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+
host->irq_control(host, 0);
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+
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+
complete(&host->op_completion);
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return IRQ_HANDLED;
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}
···
251
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if (!(tmp & NFC_V1_V2_CONFIG2_INT))
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return 0;
253
247
254
-
writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
248
+
if (!cpu_is_mx21())
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writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
255
250
256
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return 1;
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+
}
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+
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+
/*
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* It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
256
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* if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
257
+
* driver can enable/disable the irq line rather than simply masking the
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* interrupts.
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+
*/
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+
static void irq_control_mx21(struct mxc_nand_host *host, int activate)
261
+
{
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if (activate)
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enable_irq(host->irq);
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else
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disable_irq_nosync(host->irq);
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+
}
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+
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+
static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
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+
{
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uint16_t tmp;
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+
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tmp = readw(NFC_V1_V2_CONFIG1);
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+
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if (activate)
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tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
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+
else
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+
tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
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+
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writew(tmp, NFC_V1_V2_CONFIG1);
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+
}
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+
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+
static void irq_control_v3(struct mxc_nand_host *host, int activate)
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+
{
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uint32_t tmp;
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+
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tmp = readl(NFC_V3_CONFIG2);
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+
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+
if (activate)
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+
tmp &= ~NFC_V3_CONFIG2_INT_MSK;
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+
else
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tmp |= NFC_V3_CONFIG2_INT_MSK;
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+
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+
writel(tmp, NFC_V3_CONFIG2);
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}
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/* This function polls the NANDFC to wait for the basic operation to
···
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if (useirq) {
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if (!host->check_int(host)) {
311
-
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-
enable_irq(host->irq);
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-
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-
wait_event(host->irq_waitq, host->check_int(host));
262
+
INIT_COMPLETION(host->op_completion);
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+
host->irq_control(host, 1);
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wait_for_completion(&host->op_completion);
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}
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} else {
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while (max_retries-- > 0) {
···
847
799
NFC_V3_CONFIG2_2CMD_PHASES |
848
800
NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
849
801
NFC_V3_CONFIG2_ST_CMD(0x70) |
802
+
NFC_V3_CONFIG2_INT_MSK |
850
803
NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
851
804
852
805
if (chip->ecc.mode == NAND_ECC_HW)
···
1073
1024
host->send_read_id = send_read_id_v1_v2;
1074
1025
host->get_dev_status = get_dev_status_v1_v2;
1075
1026
host->check_int = check_int_v1_v2;
1027
+
if (cpu_is_mx21())
1028
+
host->irq_control = irq_control_mx21;
1029
+
else
1030
+
host->irq_control = irq_control_v1_v2;
1076
1031
}
1077
1032
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if (nfc_is_v21()) {
···
1115
1062
host->send_read_id = send_read_id_v3;
1116
1063
host->check_int = check_int_v3;
1117
1064
host->get_dev_status = get_dev_status_v3;
1065
+
host->irq_control = irq_control_v3;
1118
1066
oob_smallpage = &nandv2_hw_eccoob_smallpage;
1119
1067
oob_largepage = &nandv2_hw_eccoob_largepage;
1120
1068
} else
···
1147
1093
this->options |= NAND_USE_FLASH_BBT;
1148
1094
}
1149
1095
1150
-
init_waitqueue_head(&host->irq_waitq);
1096
+
init_completion(&host->op_completion);
1151
1097
1152
1098
host->irq = platform_get_irq(pdev, 0);
1099
+
1100
+
/*
1101
+
* mask the interrupt. For i.MX21 explicitely call
1102
+
* irq_control_v1_v2 to use the mask bit. We can't call
1103
+
* disable_irq_nosync() for an interrupt we do not own yet.
1104
+
*/
1105
+
if (cpu_is_mx21())
1106
+
irq_control_v1_v2(host, 0);
1107
+
else
1108
+
host->irq_control(host, 0);
1153
1109
1154
1110
err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1155
1111
if (err)
1156
1112
goto eirq;
1113
+
1114
+
host->irq_control(host, 0);
1115
+
1116
+
/*
1117
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* Now that the interrupt is disabled make sure the interrupt
1118
+
* mask bit is cleared on i.MX21. Otherwise we can't read
1119
+
* the interrupt status bit on this machine.
1120
+
*/
1121
+
if (cpu_is_mx21())
1122
+
irq_control_v1_v2(host, 1);
1157
1123
1158
1124
/* first scan to find the device and get the page size */
1159
1125
if (nand_scan_ident(mtd, 1, NULL)) {