Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rockchip: dw_hdmi: add RK3399 HDMI support
RK3399 and RK3288 shared the same HDMI IP controller, only some light
difference with GRF configure.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
+59
-12
+3
-1
Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+3
-1
Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
···
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Required properties:
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- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
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- compatible: should be one of the following:
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"rockchip,rk3288-dw-hdmi"
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"rockchip,rk3399-dw-hdmi"
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- reg: See dw_hdmi.txt.
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- reg-io-width: See dw_hdmi.txt. Shall be 4.
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- interrupts: HDMI interrupt number
+56
-11
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+56
-11
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
···
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#include "rockchip_drm_drv.h"
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#include "rockchip_drm_vop.h"
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#define GRF_SOC_CON6 0x025c
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#define HDMI_SEL_VOP_LIT (1 << 4)
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#define RK3288_GRF_SOC_CON6 0x025C
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#define RK3288_HDMI_LCDC_SEL BIT(4)
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#define RK3399_GRF_SOC_CON20 0x6250
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#define RK3399_HDMI_LCDC_SEL BIT(6)
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#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
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/**
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* struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
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* @lcdsel_grf_reg: grf register offset of lcdc select
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* @lcdsel_big: reg value of selecting vop big for HDMI
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* @lcdsel_lit: reg value of selecting vop little for HDMI
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*/
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struct rockchip_hdmi_chip_data {
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u32 lcdsel_grf_reg;
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u32 lcdsel_big;
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u32 lcdsel_lit;
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};
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struct rockchip_hdmi {
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struct device *dev;
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struct regmap *regmap;
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struct drm_encoder encoder;
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const struct rockchip_hdmi_chip_data *chip_data;
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};
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#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
···
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{
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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u32 val;
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int mux;
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int ret;
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mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
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if (mux)
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val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
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ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
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if (ret)
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val = hdmi->chip_data->lcdsel_lit;
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else
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val = HDMI_SEL_VOP_LIT << 16;
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val = hdmi->chip_data->lcdsel_big;
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regmap_write(hdmi->regmap, GRF_SOC_CON6, val);
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ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
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if (ret != 0)
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dev_err(hdmi->dev, "Could not write to GRF: %d\n", ret);
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dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
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(mux) ? "LIT" : "BIG");
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ret ? "LIT" : "BIG");
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}
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static int
···
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.atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
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};
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static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = {
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static struct rockchip_hdmi_chip_data rk3288_chip_data = {
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.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
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.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
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};
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static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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.phy_data = &rk3288_chip_data,
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};
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static struct rockchip_hdmi_chip_data rk3399_chip_data = {
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.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
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.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
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};
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static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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.phy_data = &rk3399_chip_data,
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};
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static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-hdmi",
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.data = &rockchip_hdmi_drv_data
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.data = &rk3288_hdmi_drv_data
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},
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{ .compatible = "rockchip,rk3399-dw-hdmi",
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.data = &rk3399_hdmi_drv_data
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},
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{},
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};
···
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match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
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plat_data = match->data;
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hdmi->dev = &pdev->dev;
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hdmi->chip_data = plat_data->phy_data;
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encoder = &hdmi->encoder;
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encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);