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drm/msm/adreno: Expose a PARAM to check AQE support

AQE (Applicaton Qrisc Engine) is required to support VK ray-pipeline. Two
conditions should be met to use this HW:
1. AQE firmware should be loaded and programmed
2. Preemption support

Expose a new MSM_PARAM to allow userspace to query its support.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714685/
Message-ID: <20260327-a8xx-gpu-batch2-v2-17-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark 64ac64bb 7fad3309

+19
+13
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 2604 2604 return 0; 2605 2605 } 2606 2606 2607 + static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu) 2608 + { 2609 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2610 + 2611 + /* 2612 + * AQE uses preemption context record as scratch pad, so check if 2613 + * preemption is enabled 2614 + */ 2615 + return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo; 2616 + } 2617 + 2607 2618 static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2608 2619 { 2609 2620 struct msm_drm_private *priv = dev->dev_private; ··· 2814 2803 .bus_halt = a6xx_bus_clear_pending_transactions, 2815 2804 .mmu_fault_handler = a6xx_fault_handler, 2816 2805 .gx_is_on = a7xx_gmu_gx_is_on, 2806 + .aqe_is_enabled = a6xx_aqe_is_enabled, 2817 2807 }; 2818 2808 2819 2809 const struct adreno_gpu_funcs a8xx_gpu_funcs = { ··· 2843 2831 .bus_halt = a8xx_bus_clear_pending_transactions, 2844 2832 .mmu_fault_handler = a8xx_fault_handler, 2845 2833 .gx_is_on = a8xx_gmu_gx_is_on, 2834 + .aqe_is_enabled = a6xx_aqe_is_enabled, 2846 2835 };
+4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
··· 441 441 case MSM_PARAM_HAS_PRR: 442 442 *value = adreno_smmu_has_prr(gpu); 443 443 return 0; 444 + case MSM_PARAM_AQE: 445 + *value = !!(adreno_gpu->funcs->aqe_is_enabled && 446 + adreno_gpu->funcs->aqe_is_enabled(adreno_gpu)); 447 + return 0; 444 448 default: 445 449 return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param); 446 450 }
+1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
··· 80 80 void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off); 81 81 int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data); 82 82 bool (*gx_is_on)(struct adreno_gpu *adreno_gpu); 83 + bool (*aqe_is_enabled)(struct adreno_gpu *adreno_gpu); 83 84 }; 84 85 85 86 struct adreno_reglist {
+1
include/uapi/drm/msm_drm.h
··· 117 117 * ioctl will throw -EPIPE. 118 118 */ 119 119 #define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */ 120 + #define MSM_PARAM_AQE 0x17 /* RO */ 120 121 121 122 /* For backwards compat. The original support for preemption was based on 122 123 * a single ring per priority level so # of priority levels equals the #