Merge tag 'mediatek-drm-next-6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next

+7

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

··· 27 27 - mediatek,mt8188-dp-intf 28 28 - mediatek,mt8192-dpi 29 29 - mediatek,mt8195-dp-intf 30 + - mediatek,mt8195-dpi 30 31 - items: 31 32 - enum: 32 33 - mediatek,mt6795-dpi ··· 36 35 - enum: 37 36 - mediatek,mt8365-dpi 38 37 - const: mediatek,mt8192-dpi 38 + - items: 39 + - enum: 40 + - mediatek,mt8188-dpi 41 + - const: mediatek,mt8195-dpi 39 42 40 43 reg: 41 44 maxItems: 1 ··· 121 116 - | 122 117 #include <dt-bindings/interrupt-controller/arm-gic.h> 123 118 #include <dt-bindings/clock/mt8173-clk.h> 119 + #include <dt-bindings/power/mt8173-power.h> 124 120 125 121 dpi: dpi@1401d000 { 126 122 compatible = "mediatek,mt8173-dpi"; 127 123 reg = <0x1401d000 0x1000>; 128 124 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 125 + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 129 126 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 130 127 <&mmsys CLK_MM_DPI_ENGINE>, 131 128 <&apmixedsys CLK_APMIXED_TVDPLL>;

+3

Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

··· 22 22 oneOf: 23 23 - enum: 24 24 - mediatek,mt8195-disp-dsc 25 + - items: 26 + - const: mediatek,mt8188-disp-dsc 27 + - const: mediatek,mt8195-disp-dsc 25 28 26 29 reg: 27 30 maxItems: 1

+5 -2

drivers/gpu/drm/mediatek/mtk_crtc.c

··· 620 620 621 621 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 622 622 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); 623 + goto update_config_out; 623 624 } 624 - #else 625 + #endif 625 626 spin_lock_irqsave(&mtk_crtc->config_lock, flags); 626 627 mtk_crtc->config_updating = false; 627 628 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 628 - #endif 629 629 630 + #if IS_REACHABLE(CONFIG_MTK_CMDQ) 631 + update_config_out: 632 + #endif 630 633 mutex_unlock(&mtk_crtc->hw_lock); 631 634 } 632 635

+3 -3

drivers/gpu/drm/mediatek/mtk_dp.c

··· 1766 1766 1767 1767 ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); 1768 1768 if (ret < 1) { 1769 - drm_err(mtk_dp->drm_dev, "Read mstm cap failed\n"); 1769 + dev_err(mtk_dp->dev, "Read mstm cap failed: %zd\n", ret); 1770 1770 return ret == 0 ? -EIO : ret; 1771 1771 } 1772 1772 ··· 1776 1776 DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, 1777 1777 &val); 1778 1778 if (ret < 1) { 1779 - drm_err(mtk_dp->drm_dev, "Read irq vector failed\n"); 1779 + dev_err(mtk_dp->dev, "Read irq vector failed: %zd\n", ret); 1780 1780 return ret == 0 ? -EIO : ret; 1781 1781 } 1782 1782 ··· 2059 2059 2060 2060 ret = mtk_dp_parse_capabilities(mtk_dp); 2061 2061 if (ret) { 2062 - drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); 2062 + dev_err(mtk_dp->dev, "Can't parse capabilities: %d\n", ret); 2063 2063 return ret; 2064 2064 } 2065 2065

+251 -92

drivers/gpu/drm/mediatek/mtk_dpi.c

··· 4 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 5 */ 6 6 7 + #include <linux/bitfield.h> 7 8 #include <linux/clk.h> 8 9 #include <linux/component.h> 10 + #include <linux/debugfs.h> 9 11 #include <linux/interrupt.h> 10 12 #include <linux/kernel.h> 11 13 #include <linux/media-bus-format.h> ··· 118 116 u16 c_bottom; 119 117 }; 120 118 119 + struct mtk_dpi_factor { 120 + u32 clock; 121 + u8 factor; 122 + }; 123 + 121 124 /** 122 125 * struct mtk_dpi_conf - Configuration of mediatek dpi. 123 - * @cal_factor: Callback function to calculate factor value. 126 + * @dpi_factor: SoC-specific pixel clock PLL factor values. 127 + * @num_dpi_factor: Number of pixel clock PLL factor values. 124 128 * @reg_h_fre_con: Register address of frequency control. 125 129 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. 126 130 * @edge_sel_en: Enable of edge selection. ··· 135 127 * @is_ck_de_pol: Support CK/DE polarity. 136 128 * @swap_input_support: Support input swap function. 137 129 * @support_direct_pin: IP supports direct connection to dpi panels. 138 - * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this 139 - * config to enable this feature. 140 130 * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH 141 131 * (no shift). 142 132 * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). 143 133 * @channel_swap_shift: Shift value of channel swap. 144 134 * @yuv422_en_bit: Enable bit of yuv422. 145 135 * @csc_enable_bit: Enable bit of CSC. 136 + * @input_2p_en_bit: Enable bit for input two pixel per round feature. 137 + * If present, implies that the feature must be enabled. 146 138 * @pixels_per_iter: Quantity of transferred pixels per iteration. 147 139 * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. 140 + * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed 141 + * for DPI registers access. 142 + * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per 143 + * round, the DPI hardware will internally transform it to 1T1P. 148 144 */ 149 145 struct mtk_dpi_conf { 150 - unsigned int (*cal_factor)(int clock); 146 + const struct mtk_dpi_factor *dpi_factor; 147 + const u8 num_dpi_factor; 151 148 u32 reg_h_fre_con; 152 149 u32 max_clock_khz; 153 150 bool edge_sel_en; ··· 161 148 bool is_ck_de_pol; 162 149 bool swap_input_support; 163 150 bool support_direct_pin; 164 - bool input_2pixel; 165 151 u32 dimension_mask; 166 152 u32 hvsize_mask; 167 153 u32 channel_swap_shift; 168 154 u32 yuv422_en_bit; 169 155 u32 csc_enable_bit; 156 + u32 input_2p_en_bit; 170 157 u32 pixels_per_iter; 171 158 bool edge_cfg_in_mmsys; 159 + bool clocked_by_hdmi; 160 + bool output_1pixel; 172 161 }; 173 162 174 163 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) ··· 179 164 180 165 tmp |= (val & mask); 181 166 writel(tmp, dpi->regs + offset); 167 + } 168 + 169 + static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable) 170 + { 171 + u32 val; 172 + 173 + if (enable) 174 + val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN; 175 + else 176 + val = 0; 177 + 178 + mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN); 182 179 } 183 180 184 181 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) ··· 437 410 438 411 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 439 412 { 440 - mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 413 + if (dpi->conf->reg_h_fre_con) 414 + mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 441 415 } 442 416 443 417 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 444 418 { 445 - if (dpi->conf->edge_sel_en) 419 + if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con) 446 420 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 447 421 } 448 422 ··· 499 471 500 472 mtk_dpi_disable(dpi); 501 473 clk_disable_unprepare(dpi->pixel_clk); 474 + clk_disable_unprepare(dpi->tvd_clk); 502 475 clk_disable_unprepare(dpi->engine_clk); 503 476 } 504 477 ··· 516 487 goto err_refcount; 517 488 } 518 489 490 + ret = clk_prepare_enable(dpi->tvd_clk); 491 + if (ret) { 492 + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); 493 + goto err_engine; 494 + } 495 + 519 496 ret = clk_prepare_enable(dpi->pixel_clk); 520 497 if (ret) { 521 498 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); ··· 531 496 return 0; 532 497 533 498 err_pixel: 499 + clk_disable_unprepare(dpi->tvd_clk); 500 + err_engine: 534 501 clk_disable_unprepare(dpi->engine_clk); 535 502 err_refcount: 536 503 dpi->refcount--; 537 504 return ret; 505 + } 506 + 507 + static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk) 508 + { 509 + const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor; 510 + int i; 511 + 512 + for (i = 0; i < dpi->conf->num_dpi_factor; i++) { 513 + if (mode_clk <= dpi_factor[i].clock) 514 + return dpi_factor[i].factor; 515 + } 516 + 517 + /* If no match try the lowest possible factor */ 518 + return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; 519 + } 520 + 521 + static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk) 522 + { 523 + unsigned long pll_rate; 524 + unsigned int factor; 525 + 526 + /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 527 + factor = mtk_dpi_calculate_factor(dpi, mode_clk); 528 + pll_rate = vm->pixelclock * factor; 529 + 530 + dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 531 + pll_rate, vm->pixelclock); 532 + 533 + clk_set_rate(dpi->tvd_clk, pll_rate); 534 + pll_rate = clk_get_rate(dpi->tvd_clk); 535 + 536 + /* 537 + * Depending on the IP version, we may output a different amount of 538 + * pixels for each iteration: divide the clock by this number and 539 + * adjust the display porches accordingly. 540 + */ 541 + vm->pixelclock = pll_rate / factor; 542 + vm->pixelclock /= dpi->conf->pixels_per_iter; 543 + 544 + if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 545 + (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) 546 + clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); 547 + else 548 + clk_set_rate(dpi->pixel_clk, vm->pixelclock); 549 + 550 + vm->pixelclock = clk_get_rate(dpi->pixel_clk); 551 + 552 + dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 553 + pll_rate, vm->pixelclock); 538 554 } 539 555 540 556 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, ··· 598 512 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 599 513 struct mtk_dpi_sync_param vsync_reven = { 0 }; 600 514 struct videomode vm = { 0 }; 601 - unsigned long pll_rate; 602 - unsigned int factor; 603 515 604 - /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 605 - factor = dpi->conf->cal_factor(mode->clock); 606 516 drm_display_mode_to_videomode(mode, &vm); 607 - pll_rate = vm.pixelclock * factor; 608 517 609 - dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 610 - pll_rate, vm.pixelclock); 611 - 612 - clk_set_rate(dpi->tvd_clk, pll_rate); 613 - pll_rate = clk_get_rate(dpi->tvd_clk); 614 - 615 - /* 616 - * Depending on the IP version, we may output a different amount of 617 - * pixels for each iteration: divide the clock by this number and 618 - * adjust the display porches accordingly. 619 - */ 620 - vm.pixelclock = pll_rate / factor; 621 - vm.pixelclock /= dpi->conf->pixels_per_iter; 622 - 623 - if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 624 - (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) 625 - clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); 626 - else 627 - clk_set_rate(dpi->pixel_clk, vm.pixelclock); 628 - 629 - 630 - vm.pixelclock = clk_get_rate(dpi->pixel_clk); 631 - 632 - dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 633 - pll_rate, vm.pixelclock); 518 + if (!dpi->conf->clocked_by_hdmi) 519 + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); 634 520 635 521 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 636 522 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; ··· 665 607 if (dpi->conf->support_direct_pin) { 666 608 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 667 609 mtk_dpi_config_2n_h_fre(dpi); 668 - mtk_dpi_dual_edge(dpi); 610 + 611 + /* DPI can connect to either an external bridge or the internal HDMI encoder */ 612 + if (dpi->conf->output_1pixel) 613 + mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN); 614 + else 615 + mtk_dpi_dual_edge(dpi); 616 + 669 617 mtk_dpi_config_disable_edge(dpi); 670 618 } 671 - if (dpi->conf->input_2pixel) { 672 - mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, 673 - DPINTF_INPUT_2P_EN); 619 + if (dpi->conf->input_2p_en_bit) { 620 + mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit, 621 + dpi->conf->input_2p_en_bit); 674 622 } 675 623 mtk_dpi_sw_reset(dpi, false); 676 624 ··· 831 767 return MODE_OK; 832 768 } 833 769 770 + static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg) 771 + { 772 + struct mtk_dpi *dpi = m->private; 773 + bool en; 774 + u32 val; 775 + 776 + if (!dpi) 777 + return -EINVAL; 778 + 779 + val = readl(dpi->regs + DPI_PATTERN0); 780 + en = val & DPI_PAT_EN; 781 + val = FIELD_GET(DPI_PAT_SEL, val); 782 + 783 + seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled"); 784 + 785 + if (en) { 786 + seq_printf(m, "Internal pattern %d: ", val); 787 + switch (val) { 788 + case 0: 789 + seq_puts(m, "256 Vertical Gray\n"); 790 + break; 791 + case 1: 792 + seq_puts(m, "1024 Vertical Gray\n"); 793 + break; 794 + case 2: 795 + seq_puts(m, "256 Horizontal Gray\n"); 796 + break; 797 + case 3: 798 + seq_puts(m, "1024 Horizontal Gray\n"); 799 + break; 800 + case 4: 801 + seq_puts(m, "Vertical Color bars\n"); 802 + break; 803 + case 6: 804 + seq_puts(m, "Frame border\n"); 805 + break; 806 + case 7: 807 + seq_puts(m, "Dot moire\n"); 808 + break; 809 + default: 810 + seq_puts(m, "Invalid selection\n"); 811 + break; 812 + } 813 + } 814 + 815 + return 0; 816 + } 817 + 818 + static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf, 819 + size_t len, loff_t *offp) 820 + { 821 + struct seq_file *m = file->private_data; 822 + u32 en, type; 823 + char buf[6]; 824 + 825 + if (!m || !m->private || *offp || len > sizeof(buf) - 1) 826 + return -EINVAL; 827 + 828 + memset(buf, 0, sizeof(buf)); 829 + if (copy_from_user(buf, ubuf, len)) 830 + return -EFAULT; 831 + 832 + if (sscanf(buf, "%u %u", &en, &type) != 2) 833 + return -EINVAL; 834 + 835 + if (en < 0 || en > 1 || type < 0 || type > 7) 836 + return -EINVAL; 837 + 838 + mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en); 839 + return len; 840 + } 841 + 842 + static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file) 843 + { 844 + return single_open(file, mtk_dpi_debug_tp_show, inode->i_private); 845 + } 846 + 847 + static const struct file_operations mtk_dpi_debug_tp_fops = { 848 + .owner = THIS_MODULE, 849 + .open = mtk_dpi_debug_tp_open, 850 + .read = seq_read, 851 + .write = mtk_dpi_debug_tp_write, 852 + .llseek = seq_lseek, 853 + .release = single_release, 854 + }; 855 + 856 + static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 857 + { 858 + struct mtk_dpi *dpi = bridge_to_dpi(bridge); 859 + 860 + debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops); 861 + } 862 + 834 863 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { 835 864 .attach = mtk_dpi_bridge_attach, 836 865 .mode_set = mtk_dpi_bridge_mode_set, ··· 936 779 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 937 780 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 938 781 .atomic_reset = drm_atomic_helper_bridge_reset, 782 + .debugfs_init = mtk_dpi_debugfs_init, 939 783 }; 940 784 941 785 void mtk_dpi_start(struct device *dev) 942 786 { 943 787 struct mtk_dpi *dpi = dev_get_drvdata(dev); 944 788 945 - mtk_dpi_power_on(dpi); 789 + if (!dpi->conf->clocked_by_hdmi) 790 + mtk_dpi_power_on(dpi); 946 791 } 947 792 948 793 void mtk_dpi_stop(struct device *dev) 949 794 { 950 795 struct mtk_dpi *dpi = dev_get_drvdata(dev); 951 796 952 - mtk_dpi_power_off(dpi); 797 + if (!dpi->conf->clocked_by_hdmi) 798 + mtk_dpi_power_off(dpi); 953 799 } 954 800 955 801 unsigned int mtk_dpi_encoder_index(struct device *dev) ··· 1017 857 .unbind = mtk_dpi_unbind, 1018 858 }; 1019 859 1020 - static unsigned int mt8173_calculate_factor(int clock) 1021 - { 1022 - if (clock <= 27000) 1023 - return 3 << 4; 1024 - else if (clock <= 84000) 1025 - return 3 << 3; 1026 - else if (clock <= 167000) 1027 - return 3 << 2; 1028 - else 1029 - return 3 << 1; 1030 - } 1031 - 1032 - static unsigned int mt2701_calculate_factor(int clock) 1033 - { 1034 - if (clock <= 64000) 1035 - return 4; 1036 - else if (clock <= 128000) 1037 - return 2; 1038 - else 1039 - return 1; 1040 - } 1041 - 1042 - static unsigned int mt8183_calculate_factor(int clock) 1043 - { 1044 - if (clock <= 27000) 1045 - return 8; 1046 - else if (clock <= 167000) 1047 - return 4; 1048 - else 1049 - return 2; 1050 - } 1051 - 1052 - static unsigned int mt8195_dpintf_calculate_factor(int clock) 1053 - { 1054 - if (clock < 70000) 1055 - return 4; 1056 - else if (clock < 200000) 1057 - return 2; 1058 - else 1059 - return 1; 1060 - } 1061 - 1062 860 static const u32 mt8173_output_fmts[] = { 1063 861 MEDIA_BUS_FMT_RGB888_1X24, 1064 862 }; ··· 1031 913 MEDIA_BUS_FMT_YUYV8_1X16, 1032 914 }; 1033 915 916 + static const struct mtk_dpi_factor dpi_factor_mt2701[] = { 917 + { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 } 918 + }; 919 + 920 + static const struct mtk_dpi_factor dpi_factor_mt8173[] = { 921 + { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 } 922 + }; 923 + 924 + static const struct mtk_dpi_factor dpi_factor_mt8183[] = { 925 + { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 } 926 + }; 927 + 928 + static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = { 929 + { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 } 930 + }; 931 + 1034 932 static const struct mtk_dpi_conf mt8173_conf = { 1035 - .cal_factor = mt8173_calculate_factor, 933 + .dpi_factor = dpi_factor_mt8173, 934 + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173), 1036 935 .reg_h_fre_con = 0xe0, 1037 936 .max_clock_khz = 300000, 1038 937 .output_fmts = mt8173_output_fmts, ··· 1066 931 }; 1067 932 1068 933 static const struct mtk_dpi_conf mt2701_conf = { 1069 - .cal_factor = mt2701_calculate_factor, 934 + .dpi_factor = dpi_factor_mt2701, 935 + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701), 1070 936 .reg_h_fre_con = 0xb0, 1071 937 .edge_sel_en = true, 1072 938 .max_clock_khz = 150000, ··· 1085 949 }; 1086 950 1087 951 static const struct mtk_dpi_conf mt8183_conf = { 1088 - .cal_factor = mt8183_calculate_factor, 952 + .dpi_factor = dpi_factor_mt8183, 953 + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1089 954 .reg_h_fre_con = 0xe0, 1090 955 .max_clock_khz = 100000, 1091 956 .output_fmts = mt8183_output_fmts, ··· 1103 966 }; 1104 967 1105 968 static const struct mtk_dpi_conf mt8186_conf = { 1106 - .cal_factor = mt8183_calculate_factor, 969 + .dpi_factor = dpi_factor_mt8183, 970 + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1107 971 .reg_h_fre_con = 0xe0, 1108 972 .max_clock_khz = 150000, 1109 973 .output_fmts = mt8183_output_fmts, ··· 1122 984 }; 1123 985 1124 986 static const struct mtk_dpi_conf mt8192_conf = { 1125 - .cal_factor = mt8183_calculate_factor, 987 + .dpi_factor = dpi_factor_mt8183, 988 + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1126 989 .reg_h_fre_con = 0xe0, 1127 990 .max_clock_khz = 150000, 1128 991 .output_fmts = mt8183_output_fmts, ··· 1139 1000 .csc_enable_bit = CSC_ENABLE, 1140 1001 }; 1141 1002 1003 + static const struct mtk_dpi_conf mt8195_conf = { 1004 + .max_clock_khz = 594000, 1005 + .output_fmts = mt8183_output_fmts, 1006 + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1007 + .pixels_per_iter = 1, 1008 + .is_ck_de_pol = true, 1009 + .swap_input_support = true, 1010 + .support_direct_pin = true, 1011 + .dimension_mask = HPW_MASK, 1012 + .hvsize_mask = HSIZE_MASK, 1013 + .channel_swap_shift = CH_SWAP, 1014 + .yuv422_en_bit = YUV422_EN, 1015 + .csc_enable_bit = CSC_ENABLE, 1016 + .input_2p_en_bit = DPI_INPUT_2P_EN, 1017 + .clocked_by_hdmi = true, 1018 + .output_1pixel = true, 1019 + }; 1020 + 1142 1021 static const struct mtk_dpi_conf mt8195_dpintf_conf = { 1143 - .cal_factor = mt8195_dpintf_calculate_factor, 1022 + .dpi_factor = dpi_factor_mt8195_dp_intf, 1023 + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), 1144 1024 .max_clock_khz = 600000, 1145 1025 .output_fmts = mt8195_output_fmts, 1146 1026 .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), 1147 1027 .pixels_per_iter = 4, 1148 - .input_2pixel = true, 1149 1028 .dimension_mask = DPINTF_HPW_MASK, 1150 1029 .hvsize_mask = DPINTF_HSIZE_MASK, 1151 1030 .channel_swap_shift = DPINTF_CH_SWAP, 1152 1031 .yuv422_en_bit = DPINTF_YUV422_EN, 1153 1032 .csc_enable_bit = DPINTF_CSC_ENABLE, 1033 + .input_2p_en_bit = DPINTF_INPUT_2P_EN, 1154 1034 }; 1155 1035 1156 1036 static int mtk_dpi_probe(struct platform_device *pdev) ··· 1260 1102 { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, 1261 1103 { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, 1262 1104 { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, 1105 + { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf }, 1263 1106 { /* sentinel */ }, 1264 1107 }; 1265 1108 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);

+9

drivers/gpu/drm/mediatek/mtk_dpi_regs.h

··· 40 40 #define FAKE_DE_LEVEN BIT(21) 41 41 #define FAKE_DE_RODD BIT(22) 42 42 #define FAKE_DE_REVEN BIT(23) 43 + 44 + /* DPI_CON: DPI instances */ 45 + #define DPI_OUTPUT_1T1P_EN BIT(24) 46 + #define DPI_INPUT_2P_EN BIT(25) 47 + /* DPI_CON: DPINTF instances */ 43 48 #define DPINTF_YUV422_EN BIT(24) 44 49 #define DPINTF_CSC_ENABLE BIT(26) 45 50 #define DPINTF_INPUT_2P_EN BIT(29) ··· 239 234 #define INT_MATRIX_SEL_MASK GENMASK(4, 0) 240 235 #define MATRIX_SEL_RGB_TO_JPEG 0 241 236 #define MATRIX_SEL_RGB_TO_BT601 2 237 + 238 + #define DPI_PATTERN0 0xf00 239 + #define DPI_PAT_EN BIT(0) 240 + #define DPI_PAT_SEL GENMASK(6, 4) 242 241 243 242 #endif /* __MTK_DPI_REGS_H */

+10

drivers/gpu/drm/mediatek/mtk_drm_drv.c

··· 327 327 .min_height = 1, 328 328 }; 329 329 330 + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 331 + .mmsys_dev_num = 1, 332 + }; 333 + 330 334 static const struct of_device_id mtk_drm_of_ids[] = { 331 335 { .compatible = "mediatek,mt2701-mmsys", 332 336 .data = &mt2701_mmsys_driver_data}, ··· 358 354 .data = &mt8195_vdosys0_driver_data}, 359 355 { .compatible = "mediatek,mt8195-vdosys1", 360 356 .data = &mt8195_vdosys1_driver_data}, 357 + { .compatible = "mediatek,mt8365-mmsys", 358 + .data = &mt8365_mmsys_driver_data}, 361 359 { } 362 360 }; 363 361 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); ··· 760 754 .data = (void *)MTK_DISP_MUTEX }, 761 755 { .compatible = "mediatek,mt8195-disp-mutex", 762 756 .data = (void *)MTK_DISP_MUTEX }, 757 + { .compatible = "mediatek,mt8365-disp-mutex", 758 + .data = (void *)MTK_DISP_MUTEX }, 763 759 { .compatible = "mediatek,mt8173-disp-od", 764 760 .data = (void *)MTK_DISP_OD }, 765 761 { .compatible = "mediatek,mt2701-disp-ovl", ··· 818 810 .data = (void *)MTK_DPI }, 819 811 { .compatible = "mediatek,mt8195-dp-intf", 820 812 .data = (void *)MTK_DP_INTF }, 813 + { .compatible = "mediatek,mt8195-dpi", 814 + .data = (void *)MTK_DPI }, 821 815 { .compatible = "mediatek,mt2701-dsi", 822 816 .data = (void *)MTK_DSI }, 823 817 { .compatible = "mediatek,mt8173-dsi",

+3 -3

drivers/gpu/drm/mediatek/mtk_dsi.c

··· 1116 1116 const struct mipi_dsi_msg *msg) 1117 1117 { 1118 1118 struct mtk_dsi *dsi = host_to_dsi(host); 1119 - u32 recv_cnt, i; 1119 + ssize_t recv_cnt; 1120 1120 u8 read_data[16]; 1121 1121 void *src_addr; 1122 1122 u8 irq_flag = CMD_DONE_INT_FLAG; 1123 1123 u32 dsi_mode; 1124 - int ret; 1124 + int ret, i; 1125 1125 1126 1126 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL); 1127 1127 if (dsi_mode & MODE) { ··· 1170 1170 if (recv_cnt) 1171 1171 memcpy(msg->rx_buf, src_addr, recv_cnt); 1172 1172 1173 - DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", 1173 + DRM_INFO("dsi get %zd byte data from the panel address(0x%x)\n", 1174 1174 recv_cnt, *((u8 *)(msg->tx_buf))); 1175 1175 1176 1176 restore_dsi_mode:

+47 -57

drivers/gpu/drm/mediatek/mtk_hdmi.c

··· 137 137 138 138 struct hdmi_audio_param { 139 139 enum hdmi_audio_coding_type aud_codec; 140 - enum hdmi_audio_sample_size aud_sampe_size; 140 + enum hdmi_audio_sample_size aud_sample_size; 141 141 enum hdmi_aud_input_type aud_input_type; 142 142 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 143 143 enum hdmi_aud_mclk aud_mclk; ··· 163 163 struct clk *clk[MTK_HDMI_CLK_COUNT]; 164 164 struct drm_display_mode mode; 165 165 bool dvi_mode; 166 - u32 min_clock; 167 - u32 max_clock; 168 - u32 max_hdisplay; 169 - u32 max_vdisplay; 170 - u32 ibias; 171 - u32 ibias_up; 172 166 struct regmap *sys_regmap; 173 167 unsigned int sys_offset; 174 168 void __iomem *regs; 175 - enum hdmi_colorspace csp; 169 + struct platform_device *audio_pdev; 176 170 struct hdmi_audio_param aud_param; 177 171 bool audio_enable; 178 172 bool powered; ··· 981 987 return 0; 982 988 } 983 989 984 - static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, 985 - const char *vendor, 986 - const char *product) 990 + static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi) 987 991 { 992 + struct drm_bridge *bridge = &hdmi->bridge; 988 993 struct hdmi_spd_infoframe frame; 989 994 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; 990 995 ssize_t err; 991 996 992 - err = hdmi_spd_infoframe_init(&frame, vendor, product); 997 + err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product); 993 998 if (err < 0) { 994 999 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 995 1000 err); ··· 1065 1072 { 1066 1073 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1067 1074 1068 - hdmi->csp = HDMI_COLORSPACE_RGB; 1069 1075 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1070 - aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1076 + aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1071 1077 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1072 1078 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1073 1079 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; ··· 1159 1167 return ret; 1160 1168 1161 1169 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1162 - if (ret) 1163 - goto err; 1170 + if (ret) { 1171 + clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1172 + return ret; 1173 + } 1164 1174 1165 1175 return 0; 1166 - err: 1167 - clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1168 - return ret; 1169 1176 } 1170 1177 1171 1178 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) ··· 1368 1377 { 1369 1378 mtk_hdmi_setup_audio_infoframe(hdmi); 1370 1379 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1371 - mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); 1380 + mtk_hdmi_setup_spd_infoframe(hdmi); 1372 1381 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1373 1382 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1374 1383 } ··· 1560 1569 switch (daifmt->fmt) { 1561 1570 case HDMI_I2S: 1562 1571 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1563 - hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1572 + hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1564 1573 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1565 1574 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1566 1575 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1567 1576 break; 1568 1577 case HDMI_SPDIF: 1569 1578 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1570 - hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1579 + hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1571 1580 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; 1572 1581 break; 1573 1582 default: ··· 1650 1659 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, 1651 1660 }; 1652 1661 1662 + static void mtk_hdmi_unregister_audio_driver(void *data) 1663 + { 1664 + platform_device_unregister(data); 1665 + } 1666 + 1653 1667 static int mtk_hdmi_register_audio_driver(struct device *dev) 1654 1668 { 1655 1669 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); ··· 1665 1669 .data = hdmi, 1666 1670 .no_capture_mute = 1, 1667 1671 }; 1668 - struct platform_device *pdev; 1672 + int ret; 1669 1673 1670 - pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1671 - PLATFORM_DEVID_AUTO, &codec_data, 1672 - sizeof(codec_data)); 1673 - if (IS_ERR(pdev)) 1674 - return PTR_ERR(pdev); 1674 + hdmi->audio_pdev = platform_device_register_data(dev, 1675 + HDMI_CODEC_DRV_NAME, 1676 + PLATFORM_DEVID_AUTO, 1677 + &codec_data, 1678 + sizeof(codec_data)); 1679 + if (IS_ERR(hdmi->audio_pdev)) 1680 + return PTR_ERR(hdmi->audio_pdev); 1675 1681 1676 - DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); 1682 + ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver, 1683 + hdmi->audio_pdev); 1684 + if (ret) 1685 + return ret; 1686 + 1677 1687 return 0; 1678 1688 } 1679 1689 ··· 1723 1721 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 1724 1722 | DRM_BRIDGE_OP_HPD; 1725 1723 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1726 - drm_bridge_add(&hdmi->bridge); 1724 + hdmi->bridge.vendor = "MediaTek"; 1725 + hdmi->bridge.product = "On-Chip HDMI"; 1726 + 1727 + ret = devm_drm_bridge_add(dev, &hdmi->bridge); 1728 + if (ret) 1729 + return dev_err_probe(dev, ret, "Failed to add bridge\n"); 1727 1730 1728 1731 ret = mtk_hdmi_clk_enable_audio(hdmi); 1729 - if (ret) { 1730 - drm_bridge_remove(&hdmi->bridge); 1732 + if (ret) 1731 1733 return dev_err_probe(dev, ret, 1732 1734 "Failed to enable audio clocks\n"); 1733 - } 1734 1735 1735 1736 return 0; 1736 1737 } ··· 1742 1737 { 1743 1738 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1744 1739 1745 - drm_bridge_remove(&hdmi->bridge); 1746 1740 mtk_hdmi_clk_disable_audio(hdmi); 1747 1741 } 1748 1742 1749 - #ifdef CONFIG_PM_SLEEP 1750 - static int mtk_hdmi_suspend(struct device *dev) 1743 + static __maybe_unused int mtk_hdmi_suspend(struct device *dev) 1751 1744 { 1752 1745 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1753 1746 ··· 1754 1751 return 0; 1755 1752 } 1756 1753 1757 - static int mtk_hdmi_resume(struct device *dev) 1754 + static __maybe_unused int mtk_hdmi_resume(struct device *dev) 1758 1755 { 1759 1756 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1760 - int ret = 0; 1761 1757 1762 - ret = mtk_hdmi_clk_enable_audio(hdmi); 1763 - if (ret) { 1764 - dev_err(dev, "hdmi resume failed!\n"); 1765 - return ret; 1766 - } 1767 - 1768 - return 0; 1758 + return mtk_hdmi_clk_enable_audio(hdmi); 1769 1759 } 1770 - #endif 1771 - static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, 1772 - mtk_hdmi_suspend, mtk_hdmi_resume); 1760 + 1761 + static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume); 1773 1762 1774 1763 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = { 1775 1764 .tz_disabled = true, ··· 1773 1778 }; 1774 1779 1775 1780 static const struct of_device_id mtk_hdmi_of_ids[] = { 1776 - { .compatible = "mediatek,mt2701-hdmi", 1777 - .data = &mtk_hdmi_conf_mt2701, 1778 - }, 1779 - { .compatible = "mediatek,mt8167-hdmi", 1780 - .data = &mtk_hdmi_conf_mt8167, 1781 - }, 1782 - { .compatible = "mediatek,mt8173-hdmi", 1783 - }, 1784 - {} 1781 + { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 }, 1782 + { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 }, 1783 + { .compatible = "mediatek,mt8173-hdmi" }, 1784 + { /* sentinel */ } 1785 1785 }; 1786 1786 MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids); 1787 1787

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