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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
clocks for the PCIe controller, operates in normal mode only. Let's
describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Yao Zi
and committed by
Heiko Stuebner
651aabc9
3688efdb
+8
-4
+6
-4
drivers/clk/rockchip/clk-pll.c
+6
-4
drivers/clk/rockchip/clk-pll.c
···
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rockchip_rk3036_pll_get_params(pll, &cur);
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cur.rate = 0;
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-
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
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if (cur_parent == PLL_MODE_NORM) {
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pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
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rate_change_remuxed = 1;
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if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
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cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
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if (cur_parent == PLL_MODE_NORM) {
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pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
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rate_change_remuxed = 1;
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}
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}
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/* update pll values */
+2
drivers/clk/rockchip/clk.h
+2
drivers/clk/rockchip/clk.h
···
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* Flags:
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* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
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* rate_table parameters and ajust them if necessary.
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* ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
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*/
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struct rockchip_pll_clock {
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unsigned int id;
···
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};
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#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
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#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
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#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
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_lshift, _pflags, _rtable) \