Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 DeviceTree updates for v6.6
Initial support for the SM4450 platform and the QRD device thereon is
added.
The IPQ5018 platform is introduced, and the RDP432-C2 board thereon.
A shared definition of the IPQ5332 RDP is introduced, as is GPIO-based
LEDs and buttons.
On the IPQ9574 RDP433 USB, CPU cooling maps and regulators are added.
On MSM8916, the D3 camera mezzanine is improved and refactored out to
its own dts. The Samsung Galaxy S4 Mini gains support for its PMIC with
charger, while Samsung Galaxy J5 and E5 gains touchscreen support.
A few fixes for MSM8939 are introduced, and initial support for Samsung
Galaxy A7 is add.
Support for scaling the cache bus fabric is introduced on MSM8996. A
missing interrupt for the USB2 controller is added. The touchscreen vio
supply on Xiaomi Mi 5 is corrected, and a few other cleanups are
introduces across other devices.
The display controller is introduced for MSM8998, a few clock fixes are
introduced and missing power domains are added for the multimedia
subsystem iommu.
Reserved memory-regions and reserved GPIO lists are updated for the
QDU/QRU1000 IDPs.
USB3 PHY is added to the QCM2290, the RB1 gains regulators and GPU is
enabled for the RB2.
PCIe and Ethernet support is introduced on SA8775P, and enabled for the
Ride board.
On SC7180 the PSCI integration is refactored, to allow supporting
devices with the Qualcomm firmware. BWMON is introduced, alongside the
CPUfreq-based bus voting.
A number of fixes are added for SC8180X, on the Primus and Lenovo Flex
5G devices pmic_glink is introduced and wired up, to provide support for
external display.
Missing SCM interconnect is added to SC8280XP, and the PDC is marked as
wakeup-parent of TLMM. On the CRD the gpio for vreg_misc_3p3 is
corrected and a few regulators are renamed to align with schematics. The
Lenovo Thinkpad X13s gains camera activity LED and a set of previously
reserved GPIOs are released. The SA8540P Ride platform gains RTC
support.
For SDM670 CPU and L3 frequency scaling is added, the PDC is introduced
and wired up as wakeup-parent of the TLMM.
On SDM845 the UFS controller gains interconnect path description,
power-domain information is added to GCC and minimum frequency of the
UFS ICE is corrected. On RB3 continuous splash memory region is
described, and the camera subsystem is enabled. On the Lenovo Yoga C630
a missing power supply for the display panel is added, and the debug
UART is introduced.
SDX75 RPMh power-domains and SPMI controller are introduces, the PMX75
PMIC is described and added to the IDP.
GPU description is added to SM6115, and together with display enabled on
the Lenovo Tab P11.
On SM635 BWMON is introduced for LLCC and DDR scaling. Display and GPU
is added, and the PDC is registered as wakeup-parent of TLMM.
L3 cache scaling is introduced on SM6375.
The DSI PHY compatible and an interrupt for I2C7 are corrected for
SM8150, on the Sony Xperia 1 and 5 the ramoops pmsg size is corrected.
On SM8250 BWMONs are introduced for DDR and LLCC scaling, the UFS node
gains interconnect paths, SMMU is marked as DMA coherent and dynamic
power coefficients are updated. On Sony Xperia 1 II and 5 II GPIO line
names are updated.
On SM8350 missing cluster sleep states and LMH interrupts are added,
the CPU compatibles are corrected and APR and LPASS pinctrl support is
introduced. The HDK gains uSD card support and PMK8350 is added.
For SM8450 support for RNG and RPMh stats are added, the ICE handling is
extracted from the UFS node and the display subsystem gains a missing
interconnect path. Thermal description is improved for the HDK.
On SM8550 MTP and QRD the pmic_glink is introduced, to provide
DisplayPort output. A missing regulator supply is also added.
A few platforms that happens to share the RPMH power-domain resource
identifier constants are migrated to new generic defines. ADC channel
names are generalized on various PMICs.
A variety of devices gain chassis-type, and the GIC_SPI constant is
replacing the 0 across a few different platforms.
* tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (215 commits)
arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Add PDC
arm64: dts: qcom: msm8916-samsung-e5: Add touchscreen
arm64: dts: qcom: sc7180: Split up TF-A related PSCI configuration
arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED
arm64: dts: qcom: sc8280xp-x13s: Unreserve NC pins
arm64: dts: qcom: msm8998: Add DPU1 nodes
arm64: dts: qcom: msm8996: Fix dsi1 interrupts
arm64: dts: qcom: sdx75-idp: Add regulator nodes
arm64: dts: qcom: sdx75: Add rpmhpd node
arm64: dts: qcom: sdx75-idp: Add pmics supported in SDX75
arm64: dts: qcom: Add pmx75 PMIC dtsi
arm64: dts: qcom: Add pm7550ba PMIC dtsi
arm64: dts: qcom: Add pinctrl gpio support for pm7250b
arm64: dts: qcom: sdx75: Add spmi node
arm64: dts: qcom: msm8998: Add missing power domain to MMSS SMMU
...
Link: https://lore.kernel.org/r/20230819034551.2537866-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+8956
-1972
+1
-1
Documentation/devicetree/bindings/arm/qcom-soc.yaml
+1
-1
Documentation/devicetree/bindings/arm/qcom-soc.yaml
···
31
31
compatible:
32
32
oneOf:
33
33
# Preferred naming style for compatibles of SoC components:
34
-
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$"
34
+
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
35
35
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
36
36
37
37
# Legacy namings - variations of existing patterns/compatibles are OK,
+14
Documentation/devicetree/bindings/arm/qcom.yaml
+14
Documentation/devicetree/bindings/arm/qcom.yaml
···
30
30
apq8084
31
31
apq8096
32
32
ipq4018
33
+
ipq5018
33
34
ipq5332
34
35
ipq6018
35
36
ipq8074
···
73
72
sdx65
74
73
sdx75
75
74
sm4250
75
+
sm4450
76
76
sm6115
77
77
sm6115p
78
78
sm6125
···
106
104
hk10-c2
107
105
idp
108
106
liquid
107
+
rdp432-c2
109
108
mtp
110
109
qrd
111
110
rb2
···
189
186
190
187
- items:
191
188
- enum:
189
+
- samsung,a7
192
190
- sony,kanuti-tulip
193
191
- square,apq8039-t2
194
192
- const: qcom,msm8939
···
342
338
- qcom,ipq4019-ap-dk07.1-c2
343
339
- qcom,ipq4019-dk04.1-c1
344
340
- const: qcom,ipq4019
341
+
342
+
- items:
343
+
- enum:
344
+
- qcom,ipq5018-rdp432-c2
345
+
- const: qcom,ipq5018
345
346
346
347
- items:
347
348
- enum:
···
910
901
- qcom,qrb4210-rb2
911
902
- const: qcom,qrb4210
912
903
- const: qcom,sm4250
904
+
905
+
- items:
906
+
- enum:
907
+
- qcom,sm4450-qrd
908
+
- const: qcom,sm4450
913
909
914
910
- items:
915
911
- enum:
+63
Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
+63
Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Global Clock & Reset Controller on IPQ5018
8
+
9
+
maintainers:
10
+
- Sricharan Ramabadhran <quic_srichara@quicinc.com>
11
+
12
+
description: |
13
+
Qualcomm global clock control module provides the clocks, resets and power
14
+
domains on IPQ5018
15
+
16
+
See also::
17
+
include/dt-bindings/clock/qcom,ipq5018-gcc.h
18
+
include/dt-bindings/reset/qcom,ipq5018-gcc.h
19
+
20
+
properties:
21
+
compatible:
22
+
const: qcom,gcc-ipq5018
23
+
24
+
clocks:
25
+
items:
26
+
- description: Board XO source
27
+
- description: Sleep clock source
28
+
- description: PCIE20 PHY0 pipe clock source
29
+
- description: PCIE20 PHY1 pipe clock source
30
+
- description: USB3 PHY pipe clock source
31
+
- description: GEPHY RX clock source
32
+
- description: GEPHY TX clock source
33
+
- description: UNIPHY RX clock source
34
+
- description: UNIPHY TX clk source
35
+
36
+
required:
37
+
- compatible
38
+
- clocks
39
+
40
+
allOf:
41
+
- $ref: qcom,gcc.yaml#
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
clock-controller@1800000 {
48
+
compatible = "qcom,gcc-ipq5018";
49
+
reg = <0x01800000 0x80000>;
50
+
clocks = <&xo_board_clk>,
51
+
<&sleep_clk>,
52
+
<&pcie20_phy0_pipe_clk>,
53
+
<&pcie20_phy1_pipe_clk>,
54
+
<&usb3_phy0_pipe_clk>,
55
+
<&gephy_rx_clk>,
56
+
<&gephy_tx_clk>,
57
+
<&uniphy_rx_clk>,
58
+
<&uniphy_tx_clk>;
59
+
#clock-cells = <1>;
60
+
#reset-cells = <1>;
61
+
#power-domain-cells = <1>;
62
+
};
63
+
...
+4
arch/arm64/boot/dts/qcom/Makefile
+4
arch/arm64/boot/dts/qcom/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
3
+
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb
3
4
dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
4
5
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
5
6
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
6
7
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
8
+
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
7
9
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
8
10
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
9
11
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
···
41
39
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
42
40
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
43
41
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
42
+
dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb
44
43
dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb
45
44
dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
46
45
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
···
189
186
dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
190
187
dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb
191
188
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
189
+
dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
192
190
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
193
191
dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb
194
192
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
+81
arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts
+81
arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Ltd.
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include "apq8016-sbc.dts"
10
+
11
+
/ {
12
+
camera_vdddo_1v8: camera-vdddo-1v8 {
13
+
compatible = "regulator-fixed";
14
+
regulator-name = "camera_vdddo";
15
+
regulator-min-microvolt = <1800000>;
16
+
regulator-max-microvolt = <1800000>;
17
+
regulator-always-on;
18
+
};
19
+
20
+
camera_vdda_2v8: camera-vdda-2v8 {
21
+
compatible = "regulator-fixed";
22
+
regulator-name = "camera_vdda";
23
+
regulator-min-microvolt = <2800000>;
24
+
regulator-max-microvolt = <2800000>;
25
+
regulator-always-on;
26
+
};
27
+
28
+
camera_vddd_1v5: camera-vddd-1v5 {
29
+
compatible = "regulator-fixed";
30
+
regulator-name = "camera_vddd";
31
+
regulator-min-microvolt = <1500000>;
32
+
regulator-max-microvolt = <1500000>;
33
+
regulator-always-on;
34
+
};
35
+
};
36
+
37
+
&camss {
38
+
status = "okay";
39
+
40
+
ports {
41
+
port@0 {
42
+
reg = <0>;
43
+
csiphy0_ep: endpoint {
44
+
data-lanes = <0 2>;
45
+
remote-endpoint = <&ov5640_ep>;
46
+
};
47
+
};
48
+
};
49
+
};
50
+
51
+
&cci {
52
+
status = "okay";
53
+
};
54
+
55
+
&cci_i2c0 {
56
+
camera_rear@3b {
57
+
compatible = "ovti,ov5640";
58
+
reg = <0x3b>;
59
+
60
+
powerdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
61
+
reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
62
+
pinctrl-names = "default";
63
+
pinctrl-0 = <&camera_rear_default>;
64
+
65
+
clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
66
+
clock-names = "xclk";
67
+
assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
68
+
assigned-clock-rates = <23880000>;
69
+
70
+
DOVDD-supply = <&camera_vdddo_1v8>;
71
+
AVDD-supply = <&camera_vdda_2v8>;
72
+
DVDD-supply = <&camera_vddd_1v5>;
73
+
74
+
port {
75
+
ov5640_ep: endpoint {
76
+
data-lanes = <1 2>;
77
+
remote-endpoint = <&csiphy0_ep>;
78
+
};
79
+
};
80
+
};
81
+
};
+6
-79
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
+6
-79
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
···
34
34
stdout-path = "serial0";
35
35
};
36
36
37
-
camera_vdddo_1v8: camera-vdddo-1v8 {
38
-
compatible = "regulator-fixed";
39
-
regulator-name = "camera_vdddo";
40
-
regulator-min-microvolt = <1800000>;
41
-
regulator-max-microvolt = <1800000>;
42
-
regulator-always-on;
43
-
};
44
-
45
-
camera_vdda_2v8: camera-vdda-2v8 {
46
-
compatible = "regulator-fixed";
47
-
regulator-name = "camera_vdda";
48
-
regulator-min-microvolt = <2800000>;
49
-
regulator-max-microvolt = <2800000>;
50
-
regulator-always-on;
51
-
};
52
-
53
-
camera_vddd_1v5: camera-vddd-1v5 {
54
-
compatible = "regulator-fixed";
55
-
regulator-name = "camera_vddd";
56
-
regulator-min-microvolt = <1500000>;
57
-
regulator-max-microvolt = <1500000>;
58
-
regulator-always-on;
59
-
};
60
-
61
37
reserved-memory {
62
38
ramoops@bff00000 {
63
39
compatible = "ramoops";
···
53
77
54
78
usb_id: usb-id {
55
79
compatible = "linux,extcon-usb-gpio";
56
-
id-gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>;
80
+
id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
57
81
pinctrl-names = "default";
58
82
pinctrl-0 = <&usb_id_default>;
59
83
};
···
148
172
};
149
173
150
174
&blsp_i2c2 {
151
-
/* On Low speed expansion */
175
+
/* On Low speed expansion: LS-I2C0 */
152
176
status = "okay";
153
-
label = "LS-I2C0";
154
177
};
155
178
156
179
&blsp_i2c4 {
157
-
/* On High speed expansion */
180
+
/* On High speed expansion: HS-I2C2 */
158
181
status = "okay";
159
-
label = "HS-I2C2";
160
182
161
183
adv_bridge: bridge@39 {
162
184
status = "okay";
···
202
228
};
203
229
204
230
&blsp_i2c6 {
205
-
/* On Low speed expansion */
231
+
/* On Low speed expansion: LS-I2C1 */
206
232
status = "okay";
207
-
label = "LS-I2C1";
208
233
};
209
234
210
235
&blsp_spi3 {
211
-
/* On High speed expansion */
236
+
/* On High speed expansion: HS-SPI1 */
212
237
status = "okay";
213
-
label = "HS-SPI1";
214
238
};
215
239
216
240
&blsp_spi5 {
217
-
/* On Low speed expansion */
241
+
/* On Low speed expansion: LS-SPI0 */
218
242
status = "okay";
219
-
label = "LS-SPI0";
220
243
};
221
244
222
245
&blsp_uart1 {
···
228
257
229
258
&camss {
230
259
status = "okay";
231
-
ports {
232
-
port@0 {
233
-
reg = <0>;
234
-
csiphy0_ep: endpoint {
235
-
data-lanes = <0 2>;
236
-
remote-endpoint = <&ov5640_ep>;
237
-
status = "okay";
238
-
};
239
-
};
240
-
};
241
-
};
242
-
243
-
&cci {
244
-
status = "okay";
245
-
};
246
-
247
-
&cci_i2c0 {
248
-
camera_rear@3b {
249
-
compatible = "ovti,ov5640";
250
-
reg = <0x3b>;
251
-
252
-
enable-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
253
-
reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
254
-
pinctrl-names = "default";
255
-
pinctrl-0 = <&camera_rear_default>;
256
-
257
-
clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
258
-
clock-names = "xclk";
259
-
clock-frequency = <23880000>;
260
-
261
-
vdddo-supply = <&camera_vdddo_1v8>;
262
-
vdda-supply = <&camera_vdda_2v8>;
263
-
vddd-supply = <&camera_vddd_1v5>;
264
-
265
-
/* No camera mezzanine by default */
266
-
status = "disabled";
267
-
268
-
port {
269
-
ov5640_ep: endpoint {
270
-
data-lanes = <0 2>;
271
-
remote-endpoint = <&csiphy0_ep>;
272
-
};
273
-
};
274
-
};
275
260
};
276
261
277
262
&lpass {
-2
arch/arm64/boot/dts/qcom/apq8039-t2.dts
-2
arch/arm64/boot/dts/qcom/apq8039-t2.dts
···
366
366
function = "gpio";
367
367
pins = "gpio107";
368
368
bias-pull-up;
369
-
input-enable;
370
369
};
371
370
};
372
371
···
374
375
pinctrl-0 = <&pinctrl_otg_default>;
375
376
pinctrl-1 = <&pinctrl_otg_host>;
376
377
pinctrl-2 = <&pinctrl_otg_device>;
377
-
pin-switch-delay-us = <100000>;
378
378
usb-role-switch;
379
379
status = "okay";
380
380
+12
-15
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+12
-15
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
···
99
99
100
100
usb2_id: usb2-id {
101
101
compatible = "linux,extcon-usb-gpio";
102
-
id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
102
+
id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
103
103
pinctrl-names = "default";
104
104
pinctrl-0 = <&usb2_vbus_det_gpio>;
105
105
};
106
106
107
107
usb3_id: usb3-id {
108
108
compatible = "linux,extcon-usb-gpio";
109
-
id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
109
+
id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
110
110
pinctrl-names = "default";
111
111
pinctrl-0 = <&usb3_vbus_det_gpio>;
112
112
};
···
138
138
};
139
139
140
140
&blsp1_i2c3 {
141
-
/* On Low speed expansion */
142
-
label = "LS-I2C0";
141
+
/* On Low speed expansion: LS-I2C0 */
143
142
status = "okay";
144
143
};
145
144
···
167
168
};
168
169
169
170
&blsp2_i2c1 {
170
-
/* On High speed expansion */
171
-
label = "HS-I2C2";
171
+
/* On High speed expansion: HS-I2C2 */
172
172
status = "okay";
173
173
};
174
174
175
175
&blsp2_i2c1 {
176
-
/* On Low speed expansion */
177
-
label = "LS-I2C1";
176
+
/* On Low speed expansion: LS-I2C1 */
178
177
status = "okay";
179
178
};
180
179
···
233
236
status = "okay";
234
237
235
238
pinctrl-names = "default", "sleep";
236
-
pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>;
237
-
pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>;
239
+
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
240
+
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
238
241
239
242
core-vdda-supply = <&vreg_l12a_1p8>;
240
243
core-vcc-supply = <&vreg_s4a_1p8>;
···
430
433
drive-strength = <2>;
431
434
};
432
435
433
-
mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state {
436
+
hdmi_hpd_active: hdmi-hpd-active-state {
434
437
pins = "gpio34";
435
438
function = "hdmi_hot";
436
439
bias-pull-down;
437
440
drive-strength = <16>;
438
441
};
439
442
440
-
mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state {
443
+
hdmi_hpd_suspend: hdmi-hpd-suspend-state {
441
444
pins = "gpio34";
442
445
function = "hdmi_hot";
443
446
bias-pull-down;
444
447
drive-strength = <2>;
445
448
};
446
449
447
-
mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state {
450
+
hdmi_ddc_active: hdmi-ddc-active-state {
448
451
pins = "gpio32", "gpio33";
449
452
function = "hdmi_ddc";
450
453
drive-strength = <2>;
451
454
bias-pull-up;
452
455
};
453
456
454
-
mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state {
457
+
hdmi_ddc_suspend: hdmi-ddc-suspend-state {
455
458
pins = "gpio32", "gpio33";
456
459
function = "hdmi_ddc";
457
460
drive-strength = <2>;
···
1040
1043
};
1041
1044
};
1042
1045
1043
-
mdss_hdmi-dai-link {
1046
+
hdmi-dai-link {
1044
1047
link-name = "HDMI";
1045
1048
cpu {
1046
1049
sound-dai = <&q6afedai HDMI_RX>;
+72
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+72
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2
+
/*
3
+
* IPQ5018 MP03.1-C2 board device tree source
4
+
*
5
+
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "ipq5018.dtsi"
11
+
12
+
/ {
13
+
model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
14
+
compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
15
+
16
+
aliases {
17
+
serial0 = &blsp1_uart1;
18
+
};
19
+
20
+
chosen {
21
+
stdout-path = "serial0:115200n8";
22
+
};
23
+
};
24
+
25
+
&blsp1_uart1 {
26
+
pinctrl-0 = <&uart1_pins>;
27
+
pinctrl-names = "default";
28
+
status = "okay";
29
+
};
30
+
31
+
&sdhc_1 {
32
+
pinctrl-0 = <&sdc_default_state>;
33
+
pinctrl-names = "default";
34
+
mmc-ddr-1_8v;
35
+
mmc-hs200-1_8v;
36
+
max-frequency = <192000000>;
37
+
bus-width = <4>;
38
+
status = "okay";
39
+
};
40
+
41
+
&sleep_clk {
42
+
clock-frequency = <32000>;
43
+
};
44
+
45
+
&tlmm {
46
+
sdc_default_state: sdc-default-state {
47
+
clk-pins {
48
+
pins = "gpio9";
49
+
function = "sdc1_clk";
50
+
drive-strength = <8>;
51
+
bias-disable;
52
+
};
53
+
54
+
cmd-pins {
55
+
pins = "gpio8";
56
+
function = "sdc1_cmd";
57
+
drive-strength = <8>;
58
+
bias-pull-up;
59
+
};
60
+
61
+
data-pins {
62
+
pins = "gpio4", "gpio5", "gpio6", "gpio7";
63
+
function = "sdc1_data";
64
+
drive-strength = <8>;
65
+
bias-disable;
66
+
};
67
+
};
68
+
};
69
+
70
+
&xo_board_clk {
71
+
clock-frequency = <24000000>;
72
+
};
+250
arch/arm64/boot/dts/qcom/ipq5018.dtsi
+250
arch/arm64/boot/dts/qcom/ipq5018.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2
+
/*
3
+
* IPQ5018 SoC device tree source
4
+
*
5
+
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
10
+
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
11
+
12
+
/ {
13
+
interrupt-parent = <&intc>;
14
+
#address-cells = <2>;
15
+
#size-cells = <2>;
16
+
17
+
clocks {
18
+
sleep_clk: sleep-clk {
19
+
compatible = "fixed-clock";
20
+
#clock-cells = <0>;
21
+
};
22
+
23
+
xo_board_clk: xo-board-clk {
24
+
compatible = "fixed-clock";
25
+
#clock-cells = <0>;
26
+
};
27
+
};
28
+
29
+
cpus {
30
+
#address-cells = <1>;
31
+
#size-cells = <0>;
32
+
33
+
CPU0: cpu@0 {
34
+
device_type = "cpu";
35
+
compatible = "arm,cortex-a53";
36
+
reg = <0x0>;
37
+
enable-method = "psci";
38
+
next-level-cache = <&L2_0>;
39
+
};
40
+
41
+
CPU1: cpu@1 {
42
+
device_type = "cpu";
43
+
compatible = "arm,cortex-a53";
44
+
reg = <0x1>;
45
+
enable-method = "psci";
46
+
next-level-cache = <&L2_0>;
47
+
};
48
+
49
+
L2_0: l2-cache {
50
+
compatible = "cache";
51
+
cache-level = <2>;
52
+
cache-size = <0x80000>;
53
+
cache-unified;
54
+
};
55
+
};
56
+
57
+
firmware {
58
+
scm {
59
+
compatible = "qcom,scm-ipq5018", "qcom,scm";
60
+
};
61
+
};
62
+
63
+
memory@40000000 {
64
+
device_type = "memory";
65
+
/* We expect the bootloader to fill in the size */
66
+
reg = <0x0 0x40000000 0x0 0x0>;
67
+
};
68
+
69
+
pmu {
70
+
compatible = "arm,cortex-a53-pmu";
71
+
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
72
+
};
73
+
74
+
psci {
75
+
compatible = "arm,psci-1.0";
76
+
method = "smc";
77
+
};
78
+
79
+
reserved-memory {
80
+
#address-cells = <2>;
81
+
#size-cells = <2>;
82
+
ranges;
83
+
84
+
tz_region: tz@4ac00000 {
85
+
reg = <0x0 0x4ac00000 0x0 0x200000>;
86
+
no-map;
87
+
};
88
+
};
89
+
90
+
soc: soc@0 {
91
+
compatible = "simple-bus";
92
+
#address-cells = <1>;
93
+
#size-cells = <1>;
94
+
ranges = <0 0 0 0xffffffff>;
95
+
96
+
tlmm: pinctrl@1000000 {
97
+
compatible = "qcom,ipq5018-tlmm";
98
+
reg = <0x01000000 0x300000>;
99
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
100
+
gpio-controller;
101
+
#gpio-cells = <2>;
102
+
gpio-ranges = <&tlmm 0 0 47>;
103
+
interrupt-controller;
104
+
#interrupt-cells = <2>;
105
+
106
+
uart1_pins: uart1-state {
107
+
pins = "gpio31", "gpio32", "gpio33", "gpio34";
108
+
function = "blsp1_uart1";
109
+
drive-strength = <8>;
110
+
bias-pull-down;
111
+
};
112
+
};
113
+
114
+
gcc: clock-controller@1800000 {
115
+
compatible = "qcom,gcc-ipq5018";
116
+
reg = <0x01800000 0x80000>;
117
+
clocks = <&xo_board_clk>,
118
+
<&sleep_clk>,
119
+
<0>,
120
+
<0>,
121
+
<0>,
122
+
<0>,
123
+
<0>,
124
+
<0>,
125
+
<0>;
126
+
#clock-cells = <1>;
127
+
#reset-cells = <1>;
128
+
#power-domain-cells = <1>;
129
+
};
130
+
131
+
sdhc_1: mmc@7804000 {
132
+
compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
133
+
reg = <0x7804000 0x1000>;
134
+
reg-names = "hc";
135
+
136
+
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
137
+
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
138
+
interrupt-names = "hc_irq", "pwr_irq";
139
+
140
+
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
141
+
<&gcc GCC_SDCC1_APPS_CLK>,
142
+
<&xo_board_clk>;
143
+
clock-names = "iface", "core", "xo";
144
+
non-removable;
145
+
status = "disabled";
146
+
};
147
+
148
+
blsp1_uart1: serial@78af000 {
149
+
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
150
+
reg = <0x078af000 0x200>;
151
+
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
152
+
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
153
+
<&gcc GCC_BLSP1_AHB_CLK>;
154
+
clock-names = "core", "iface";
155
+
status = "disabled";
156
+
};
157
+
158
+
intc: interrupt-controller@b000000 {
159
+
compatible = "qcom,msm-qgic2";
160
+
reg = <0x0b000000 0x1000>, /* GICD */
161
+
<0x0b002000 0x2000>, /* GICC */
162
+
<0x0b001000 0x1000>, /* GICH */
163
+
<0x0b004000 0x2000>; /* GICV */
164
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
165
+
interrupt-controller;
166
+
#interrupt-cells = <3>;
167
+
#address-cells = <1>;
168
+
#size-cells = <1>;
169
+
ranges = <0 0x0b00a000 0x1ffa>;
170
+
171
+
v2m0: v2m@0 {
172
+
compatible = "arm,gic-v2m-frame";
173
+
reg = <0x00000000 0xff8>;
174
+
msi-controller;
175
+
};
176
+
177
+
v2m1: v2m@1000 {
178
+
compatible = "arm,gic-v2m-frame";
179
+
reg = <0x00001000 0xff8>;
180
+
msi-controller;
181
+
};
182
+
};
183
+
184
+
timer@b120000 {
185
+
compatible = "arm,armv7-timer-mem";
186
+
reg = <0x0b120000 0x1000>;
187
+
#address-cells = <1>;
188
+
#size-cells = <1>;
189
+
ranges;
190
+
191
+
frame@b120000 {
192
+
reg = <0x0b121000 0x1000>,
193
+
<0x0b122000 0x1000>;
194
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
195
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
196
+
frame-number = <0>;
197
+
};
198
+
199
+
frame@b123000 {
200
+
reg = <0xb123000 0x1000>;
201
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
202
+
frame-number = <1>;
203
+
status = "disabled";
204
+
};
205
+
206
+
frame@b124000 {
207
+
frame-number = <2>;
208
+
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
209
+
reg = <0x0b124000 0x1000>;
210
+
status = "disabled";
211
+
};
212
+
213
+
frame@b125000 {
214
+
reg = <0x0b125000 0x1000>;
215
+
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
216
+
frame-number = <3>;
217
+
status = "disabled";
218
+
};
219
+
220
+
frame@b126000 {
221
+
reg = <0x0b126000 0x1000>;
222
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
223
+
frame-number = <4>;
224
+
status = "disabled";
225
+
};
226
+
227
+
frame@b127000 {
228
+
reg = <0x0b127000 0x1000>;
229
+
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
230
+
frame-number = <5>;
231
+
status = "disabled";
232
+
};
233
+
234
+
frame@b128000 {
235
+
reg = <0x0b128000 0x1000>;
236
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
237
+
frame-number = <6>;
238
+
status = "disabled";
239
+
};
240
+
};
241
+
};
242
+
243
+
timer {
244
+
compatible = "arm,armv8-timer";
245
+
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
246
+
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
247
+
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
248
+
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
249
+
};
250
+
};
+78
arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
+78
arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* IPQ5332 RDP board common device tree source
4
+
*
5
+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/input/input.h>
12
+
#include "ipq5332.dtsi"
13
+
14
+
/ {
15
+
aliases {
16
+
serial0 = &blsp1_uart0;
17
+
};
18
+
19
+
chosen {
20
+
stdout-path = "serial0";
21
+
};
22
+
23
+
gpio-keys {
24
+
compatible = "gpio-keys";
25
+
pinctrl-0 = <&gpio_keys_default>;
26
+
pinctrl-names = "default";
27
+
28
+
button-wps {
29
+
label = "wps";
30
+
linux,code = <KEY_WPS_BUTTON>;
31
+
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
32
+
debounce-interval = <60>;
33
+
};
34
+
};
35
+
36
+
leds {
37
+
compatible = "gpio-leds";
38
+
pinctrl-0 = <&gpio_leds_default>;
39
+
pinctrl-names = "default";
40
+
41
+
led-0 {
42
+
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
43
+
linux,default-trigger = "phy0tx";
44
+
default-state = "off";
45
+
};
46
+
};
47
+
};
48
+
49
+
&blsp1_uart0 {
50
+
pinctrl-0 = <&serial_0_pins>;
51
+
pinctrl-names = "default";
52
+
status = "okay";
53
+
};
54
+
55
+
&sleep_clk {
56
+
clock-frequency = <32000>;
57
+
};
58
+
59
+
&xo_board {
60
+
clock-frequency = <24000000>;
61
+
};
62
+
63
+
/* PINCTRL */
64
+
&tlmm {
65
+
gpio_keys_default: gpio-keys-default-state {
66
+
pins = "gpio35";
67
+
function = "gpio";
68
+
drive-strength = <8>;
69
+
bias-pull-up;
70
+
};
71
+
72
+
gpio_leds_default: gpio-leds-default-state {
73
+
pins = "gpio36";
74
+
function = "gpio";
75
+
drive-strength = <8>;
76
+
bias-pull-down;
77
+
};
78
+
};
+1
-25
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
+1
-25
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
···
7
7
8
8
/dts-v1/;
9
9
10
-
#include "ipq5332.dtsi"
10
+
#include "ipq5332-rdp-common.dtsi"
11
11
12
12
/ {
13
13
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
14
14
compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
15
-
16
-
aliases {
17
-
serial0 = &blsp1_uart0;
18
-
};
19
-
20
-
chosen {
21
-
stdout-path = "serial0";
22
-
};
23
-
};
24
-
25
-
&blsp1_uart0 {
26
-
pinctrl-0 = <&serial_0_pins>;
27
-
pinctrl-names = "default";
28
-
status = "okay";
29
15
};
30
16
31
17
&blsp1_i2c1 {
···
31
45
pinctrl-names = "default";
32
46
status = "okay";
33
47
};
34
-
35
-
&sleep_clk {
36
-
clock-frequency = <32000>;
37
-
};
38
-
39
-
&xo_board {
40
-
clock-frequency = <24000000>;
41
-
};
42
-
43
-
/* PINCTRL */
44
48
45
49
&tlmm {
46
50
i2c_1_pins: i2c-1-state {
+1
-25
arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
+1
-25
arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
···
7
7
8
8
/dts-v1/;
9
9
10
-
#include "ipq5332.dtsi"
10
+
#include "ipq5332-rdp-common.dtsi"
11
11
12
12
/ {
13
13
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";
14
14
compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
15
-
16
-
aliases {
17
-
serial0 = &blsp1_uart0;
18
-
};
19
-
20
-
chosen {
21
-
stdout-path = "serial0";
22
-
};
23
-
};
24
-
25
-
&blsp1_uart0 {
26
-
pinctrl-0 = <&serial_0_pins>;
27
-
pinctrl-names = "default";
28
-
status = "okay";
29
15
};
30
16
31
17
&blsp1_i2c1 {
···
45
59
pinctrl-names = "default";
46
60
status = "okay";
47
61
};
48
-
49
-
&sleep_clk {
50
-
clock-frequency = <32000>;
51
-
};
52
-
53
-
&xo_board {
54
-
clock-frequency = <24000000>;
55
-
};
56
-
57
-
/* PINCTRL */
58
62
59
63
&tlmm {
60
64
i2c_1_pins: i2c-1-state {
+1
-23
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
+1
-23
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
···
7
7
8
8
/dts-v1/;
9
9
10
-
#include "ipq5332.dtsi"
10
+
#include "ipq5332-rdp-common.dtsi"
11
11
12
12
/ {
13
13
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
14
14
compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
15
-
16
-
aliases {
17
-
serial0 = &blsp1_uart0;
18
-
};
19
-
20
-
chosen {
21
-
stdout-path = "serial0";
22
-
};
23
-
};
24
-
25
-
&blsp1_uart0 {
26
-
pinctrl-0 = <&serial_0_pins>;
27
-
pinctrl-names = "default";
28
-
status = "okay";
29
15
};
30
16
31
17
&blsp1_spi0 {
···
37
51
pinctrl-0 = <&sdc_default_state>;
38
52
pinctrl-names = "default";
39
53
status = "okay";
40
-
};
41
-
42
-
&sleep_clk {
43
-
clock-frequency = <32000>;
44
-
};
45
-
46
-
&xo_board {
47
-
clock-frequency = <24000000>;
48
54
};
49
55
50
56
/* PINCTRL */
+1
-46
arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
+1
-46
arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
···
7
7
8
8
/dts-v1/;
9
9
10
-
#include <dt-bindings/gpio/gpio.h>
11
-
#include <dt-bindings/input/input.h>
12
-
#include "ipq5332.dtsi"
10
+
#include "ipq5332-rdp-common.dtsi"
13
11
14
12
/ {
15
13
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9";
16
14
compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332";
17
-
18
-
aliases {
19
-
serial0 = &blsp1_uart0;
20
-
};
21
-
22
-
chosen {
23
-
stdout-path = "serial0";
24
-
};
25
-
26
-
gpio-keys {
27
-
compatible = "gpio-keys";
28
-
pinctrl-0 = <&gpio_keys_default_state>;
29
-
pinctrl-names = "default";
30
-
31
-
button-wps {
32
-
label = "wps";
33
-
linux,code = <KEY_WPS_BUTTON>;
34
-
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
35
-
linux,input-type = <1>;
36
-
debounce-interval = <60>;
37
-
};
38
-
};
39
-
};
40
-
41
-
&blsp1_uart0 {
42
-
pinctrl-0 = <&serial_0_pins>;
43
-
pinctrl-names = "default";
44
-
status = "okay";
45
15
};
46
16
47
17
&blsp1_i2c1 {
···
32
62
status = "okay";
33
63
};
34
64
35
-
&sleep_clk {
36
-
clock-frequency = <32000>;
37
-
};
38
-
39
-
&xo_board {
40
-
clock-frequency = <24000000>;
41
-
};
42
-
43
65
/* PINCTRL */
44
66
45
67
&tlmm {
46
-
gpio_keys_default_state: gpio-keys-default-state {
47
-
pins = "gpio35";
48
-
function = "gpio";
49
-
drive-strength = <8>;
50
-
bias-pull-up;
51
-
};
52
-
53
68
i2c_1_pins: i2c-1-state {
54
69
pins = "gpio29", "gpio30";
55
70
function = "blsp1_i2c0";
+26
-22
arch/arm64/boot/dts/qcom/ipq6018.dtsi
+26
-22
arch/arm64/boot/dts/qcom/ipq6018.dtsi
···
146
146
method = "smc";
147
147
};
148
148
149
+
rpm: remoteproc {
150
+
compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
151
+
152
+
glink-edge {
153
+
compatible = "qcom,glink-rpm";
154
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
155
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
156
+
mboxes = <&apcs_glb 0>;
157
+
158
+
rpm_requests: rpm-requests {
159
+
compatible = "qcom,rpm-ipq6018";
160
+
qcom,glink-channels = "rpm_requests";
161
+
162
+
regulators {
163
+
compatible = "qcom,rpm-mp5496-regulators";
164
+
165
+
ipq6018_s2: s2 {
166
+
regulator-min-microvolt = <725000>;
167
+
regulator-max-microvolt = <1062500>;
168
+
regulator-always-on;
169
+
};
170
+
};
171
+
};
172
+
};
173
+
};
174
+
149
175
reserved-memory {
150
176
#address-cells = <2>;
151
177
#size-cells = <2>;
···
205
179
q6_region: memory@4ab00000 {
206
180
reg = <0x0 0x4ab00000 0x0 0x5500000>;
207
181
no-map;
208
-
};
209
-
};
210
-
211
-
rpm-glink {
212
-
compatible = "qcom,glink-rpm";
213
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
214
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
215
-
mboxes = <&apcs_glb 0>;
216
-
217
-
rpm_requests: rpm-requests {
218
-
compatible = "qcom,rpm-ipq6018";
219
-
qcom,glink-channels = "rpm_requests";
220
-
221
-
regulators {
222
-
compatible = "qcom,rpm-mp5496-regulators";
223
-
224
-
ipq6018_s2: s2 {
225
-
regulator-min-microvolt = <725000>;
226
-
regulator-max-microvolt = <1062500>;
227
-
regulator-always-on;
228
-
};
229
-
};
230
182
};
231
183
};
232
184
+4
-4
arch/arm64/boot/dts/qcom/ipq8074.dtsi
+4
-4
arch/arm64/boot/dts/qcom/ipq8074.dtsi
···
794
794
795
795
pcie1: pci@10000000 {
796
796
compatible = "qcom,pcie-ipq8074";
797
-
reg = <0x10000000 0xf1d>,
798
-
<0x10000f20 0xa8>,
799
-
<0x00088000 0x2000>,
800
-
<0x10100000 0x1000>;
797
+
reg = <0x10000000 0xf1d>,
798
+
<0x10000f20 0xa8>,
799
+
<0x00088000 0x2000>,
800
+
<0x10100000 0x1000>;
801
801
reg-names = "dbi", "elbi", "parf", "config";
802
802
device_type = "pci";
803
803
linux,pci-domain = <1>;
+48
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+48
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
···
21
21
chosen {
22
22
stdout-path = "serial0:115200n8";
23
23
};
24
+
25
+
regulator_fixed_3p3: s3300 {
26
+
compatible = "regulator-fixed";
27
+
regulator-min-microvolt = <3300000>;
28
+
regulator-max-microvolt = <3300000>;
29
+
regulator-boot-on;
30
+
regulator-always-on;
31
+
regulator-name = "fixed_3p3";
32
+
};
33
+
34
+
regulator_fixed_0p925: s0925 {
35
+
compatible = "regulator-fixed";
36
+
regulator-min-microvolt = <925000>;
37
+
regulator-max-microvolt = <925000>;
38
+
regulator-boot-on;
39
+
regulator-always-on;
40
+
regulator-name = "fixed_0p925";
41
+
};
24
42
};
25
43
26
44
&blsp1_uart2 {
···
62
44
*/
63
45
regulator-min-microvolt = <725000>;
64
46
regulator-max-microvolt = <1075000>;
47
+
};
48
+
49
+
mp5496_l2: l2 {
50
+
regulator-min-microvolt = <1800000>;
51
+
regulator-max-microvolt = <1800000>;
52
+
regulator-always-on;
53
+
regulator-boot-on;
65
54
};
66
55
};
67
56
};
···
121
96
bias-pull-down;
122
97
};
123
98
};
99
+
};
100
+
101
+
&usb_0_dwc3 {
102
+
dr_mode = "host";
103
+
};
104
+
105
+
&usb_0_qmpphy {
106
+
vdda-pll-supply = <&mp5496_l2>;
107
+
vdda-phy-supply = <®ulator_fixed_0p925>;
108
+
109
+
status = "okay";
110
+
};
111
+
112
+
&usb_0_qusbphy {
113
+
vdd-supply = <®ulator_fixed_0p925>;
114
+
vdda-pll-supply = <&mp5496_l2>;
115
+
vdda-phy-dpdm-supply = <®ulator_fixed_3p3>;
116
+
117
+
status = "okay";
118
+
};
119
+
120
+
&usb3 {
121
+
status = "okay";
124
122
};
125
123
126
124
&xo_board_clk {
+162
-20
arch/arm64/boot/dts/qcom/ipq9574.dtsi
+162
-20
arch/arm64/boot/dts/qcom/ipq9574.dtsi
···
10
10
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11
11
#include <dt-bindings/interrupt-controller/arm-gic.h>
12
12
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13
+
#include <dt-bindings/thermal/thermal.h>
13
14
14
15
/ {
15
16
interrupt-parent = <&intc>;
···
43
42
clock-names = "cpu";
44
43
operating-points-v2 = <&cpu_opp_table>;
45
44
cpu-supply = <&ipq9574_s1>;
45
+
#cooling-cells = <2>;
46
46
};
47
47
48
48
CPU1: cpu@1 {
···
56
54
clock-names = "cpu";
57
55
operating-points-v2 = <&cpu_opp_table>;
58
56
cpu-supply = <&ipq9574_s1>;
57
+
#cooling-cells = <2>;
59
58
};
60
59
61
60
CPU2: cpu@2 {
···
69
66
clock-names = "cpu";
70
67
operating-points-v2 = <&cpu_opp_table>;
71
68
cpu-supply = <&ipq9574_s1>;
69
+
#cooling-cells = <2>;
72
70
};
73
71
74
72
CPU3: cpu@3 {
···
82
78
clock-names = "cpu";
83
79
operating-points-v2 = <&cpu_opp_table>;
84
80
cpu-supply = <&ipq9574_s1>;
81
+
#cooling-cells = <2>;
85
82
};
86
83
87
84
L2_0: l2-cache {
···
156
151
method = "smc";
157
152
};
158
153
154
+
rpm: remoteproc {
155
+
compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
156
+
157
+
glink-edge {
158
+
compatible = "qcom,glink-rpm";
159
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
160
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
161
+
mboxes = <&apcs_glb 0>;
162
+
163
+
rpm_requests: rpm-requests {
164
+
compatible = "qcom,rpm-ipq9574";
165
+
qcom,glink-channels = "rpm_requests";
166
+
};
167
+
};
168
+
};
169
+
159
170
reserved-memory {
160
171
#address-cells = <2>;
161
172
#size-cells = <2>;
···
197
176
reg = <0x0 0x4aa00000 0x0 0x100000>;
198
177
hwlocks = <&tcsr_mutex 0>;
199
178
no-map;
200
-
};
201
-
};
202
-
203
-
rpm-glink {
204
-
compatible = "qcom,glink-rpm";
205
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
206
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
207
-
mboxes = <&apcs_glb 0>;
208
-
209
-
rpm_requests: rpm-requests {
210
-
compatible = "qcom,rpm-ipq9574";
211
-
qcom,glink-channels = "rpm_requests";
212
179
};
213
180
};
214
181
···
410
401
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
411
402
<&gcc GCC_BLSP1_AHB_CLK>;
412
403
clock-names = "core", "iface";
404
+
assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
405
+
assigned-clock-rates = <50000000>;
413
406
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
414
407
dma-names = "tx", "rx";
415
408
status = "disabled";
···
440
429
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
441
430
<&gcc GCC_BLSP1_AHB_CLK>;
442
431
clock-names = "core", "iface";
432
+
assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
433
+
assigned-clock-rates = <50000000>;
443
434
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
444
435
dma-names = "tx", "rx";
445
436
status = "disabled";
···
470
457
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
471
458
<&gcc GCC_BLSP1_AHB_CLK>;
472
459
clock-names = "core", "iface";
460
+
assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
461
+
assigned-clock-rates = <50000000>;
473
462
dmas = <&blsp_dma 18>, <&blsp_dma 19>;
474
463
dma-names = "tx", "rx";
475
464
status = "disabled";
···
501
486
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
502
487
<&gcc GCC_BLSP1_AHB_CLK>;
503
488
clock-names = "core", "iface";
489
+
assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
490
+
assigned-clock-rates = <50000000>;
504
491
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
505
492
dma-names = "tx", "rx";
506
493
status = "disabled";
···
520
503
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
521
504
dma-names = "tx", "rx";
522
505
status = "disabled";
506
+
};
507
+
508
+
usb_0_qusbphy: phy@7b000 {
509
+
compatible = "qcom,ipq9574-qusb2-phy";
510
+
reg = <0x0007b000 0x180>;
511
+
#phy-cells = <0>;
512
+
513
+
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
514
+
<&xo_board_clk>;
515
+
clock-names = "cfg_ahb",
516
+
"ref";
517
+
518
+
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
519
+
status = "disabled";
520
+
};
521
+
522
+
usb_0_qmpphy: phy@7d000 {
523
+
compatible = "qcom,ipq9574-qmp-usb3-phy";
524
+
reg = <0x0007d000 0xa00>;
525
+
#phy-cells = <0>;
526
+
527
+
clocks = <&gcc GCC_USB0_AUX_CLK>,
528
+
<&xo_board_clk>,
529
+
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
530
+
<&gcc GCC_USB0_PIPE_CLK>;
531
+
clock-names = "aux",
532
+
"ref",
533
+
"cfg_ahb",
534
+
"pipe";
535
+
536
+
resets = <&gcc GCC_USB0_PHY_BCR>,
537
+
<&gcc GCC_USB3PHY_0_PHY_BCR>;
538
+
reset-names = "phy",
539
+
"phy_phy";
540
+
541
+
#clock-cells = <0>;
542
+
clock-output-names = "usb0_pipe_clk";
543
+
544
+
status = "disabled";
545
+
};
546
+
547
+
usb3: usb@8af8800 {
548
+
compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
549
+
reg = <0x08af8800 0x400>;
550
+
#address-cells = <1>;
551
+
#size-cells = <1>;
552
+
ranges;
553
+
554
+
clocks = <&gcc GCC_SNOC_USB_CLK>,
555
+
<&gcc GCC_USB0_MASTER_CLK>,
556
+
<&gcc GCC_ANOC_USB_AXI_CLK>,
557
+
<&gcc GCC_USB0_SLEEP_CLK>,
558
+
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
559
+
560
+
clock-names = "cfg_noc",
561
+
"core",
562
+
"iface",
563
+
"sleep",
564
+
"mock_utmi";
565
+
566
+
assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
567
+
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
568
+
assigned-clock-rates = <200000000>,
569
+
<24000000>;
570
+
571
+
interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
572
+
interrupt-names = "pwr_event";
573
+
574
+
resets = <&gcc GCC_USB_BCR>;
575
+
status = "disabled";
576
+
577
+
usb_0_dwc3: usb@8a00000 {
578
+
compatible = "snps,dwc3";
579
+
reg = <0x8a00000 0xcd00>;
580
+
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
581
+
clock-names = "ref";
582
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
583
+
phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
584
+
phy-names = "usb2-phy", "usb3-phy";
585
+
tx-fifo-resize;
586
+
snps,is-utmi-l1-suspend;
587
+
snps,hird-threshold = /bits/ 8 <0x0>;
588
+
snps,dis_u2_susphy_quirk;
589
+
snps,dis_u3_susphy_quirk;
590
+
};
523
591
};
524
592
525
593
intc: interrupt-controller@b000000 {
···
829
727
thermal-sensors = <&tsens 10>;
830
728
831
729
trips {
832
-
cpu-critical {
730
+
cpu0_crit: cpu-critical {
833
731
temperature = <120000>;
834
732
hysteresis = <10000>;
835
733
type = "critical";
836
734
};
837
735
838
-
cpu-passive {
736
+
cpu0_alert: cpu-passive {
839
737
temperature = <110000>;
840
738
hysteresis = <1000>;
841
739
type = "passive";
740
+
};
741
+
};
742
+
743
+
cooling-maps {
744
+
map0 {
745
+
trip = <&cpu0_alert>;
746
+
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
747
+
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
748
+
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
749
+
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
842
750
};
843
751
};
844
752
};
···
859
747
thermal-sensors = <&tsens 11>;
860
748
861
749
trips {
862
-
cpu-critical {
750
+
cpu1_crit: cpu-critical {
863
751
temperature = <120000>;
864
752
hysteresis = <10000>;
865
753
type = "critical";
866
754
};
867
755
868
-
cpu-passive {
756
+
cpu1_alert: cpu-passive {
869
757
temperature = <110000>;
870
758
hysteresis = <1000>;
871
759
type = "passive";
760
+
};
761
+
};
762
+
763
+
cooling-maps {
764
+
map0 {
765
+
trip = <&cpu1_alert>;
766
+
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
767
+
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
768
+
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
769
+
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
872
770
};
873
771
};
874
772
};
···
889
767
thermal-sensors = <&tsens 12>;
890
768
891
769
trips {
892
-
cpu-critical {
770
+
cpu2_crit: cpu-critical {
893
771
temperature = <120000>;
894
772
hysteresis = <10000>;
895
773
type = "critical";
896
774
};
897
775
898
-
cpu-passive {
776
+
cpu2_alert: cpu-passive {
899
777
temperature = <110000>;
900
778
hysteresis = <1000>;
901
779
type = "passive";
780
+
};
781
+
};
782
+
783
+
cooling-maps {
784
+
map0 {
785
+
trip = <&cpu2_alert>;
786
+
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
787
+
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
788
+
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
789
+
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
902
790
};
903
791
};
904
792
};
···
919
787
thermal-sensors = <&tsens 13>;
920
788
921
789
trips {
922
-
cpu-critical {
790
+
cpu3_crit: cpu-critical {
923
791
temperature = <120000>;
924
792
hysteresis = <10000>;
925
793
type = "critical";
926
794
};
927
795
928
-
cpu-passive {
796
+
cpu3_alert: cpu-passive {
929
797
temperature = <110000>;
930
798
hysteresis = <1000>;
931
799
type = "passive";
800
+
};
801
+
};
802
+
803
+
cooling-maps {
804
+
map0 {
805
+
trip = <&cpu3_alert>;
806
+
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
807
+
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
808
+
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
809
+
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
932
810
};
933
811
};
934
812
};
+1
-1
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
+1
arch/arm64/boot/dts/qcom/msm8916-mtp.dts
+1
arch/arm64/boot/dts/qcom/msm8916-mtp.dts
+19
-2
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
+19
-2
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
···
42
42
43
43
&blsp_i2c2 {
44
44
/* lis2hh12 accelerometer instead of BMC150 */
45
-
status = "disabled";
46
-
47
45
/delete-node/ accelerometer@10;
48
46
/delete-node/ magnetometer@12;
47
+
48
+
accelerometer@1d {
49
+
compatible = "st,lis2hh12";
50
+
reg = <0x1d>;
51
+
52
+
interrupt-parent = <&tlmm>;
53
+
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
54
+
55
+
vdd-supply = <&pm8916_l5>;
56
+
vddio-supply = <&pm8916_l5>;
57
+
58
+
st,drdy-int-pin = <1>;
59
+
mount-matrix = "1", "0", "0",
60
+
"0", "-1", "0",
61
+
"0", "0", "1";
62
+
63
+
pinctrl-0 = <&accel_int_default>;
64
+
pinctrl-names = "default";
65
+
};
49
66
};
50
67
51
68
®_motor_vdd {
+20
arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts
+20
arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts
···
22
22
compatible = "samsung,e5", "qcom,msm8916";
23
23
chassis-type = "handset";
24
24
};
25
+
26
+
&blsp_i2c5 {
27
+
status = "okay";
28
+
29
+
touchscreen@48 {
30
+
compatible = "melfas,mms345l";
31
+
reg = <0x48>;
32
+
33
+
interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
34
+
35
+
touchscreen-size-x = <720>;
36
+
touchscreen-size-y = <1280>;
37
+
38
+
avdd-supply = <®_vdd_tsp_a>;
39
+
vdd-supply = <&pm8916_l6>;
40
+
41
+
pinctrl-0 = <&ts_int_default>;
42
+
pinctrl-names = "default";
43
+
};
44
+
};
-1
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
-1
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
+29
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
+29
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
···
86
86
};
87
87
};
88
88
89
+
&blsp_i2c5 {
90
+
status = "okay";
91
+
92
+
touchscreen: touchscreen@50 {
93
+
compatible = "imagis,ist3038c";
94
+
reg = <0x50>;
95
+
96
+
interrupt-parent = <&tlmm>;
97
+
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
98
+
99
+
touchscreen-size-x = <720>;
100
+
touchscreen-size-y = <1280>;
101
+
102
+
vddio-supply = <&pm8916_l6>;
103
+
104
+
pinctrl-0 = <&tsp_int_default>;
105
+
pinctrl-names = "default";
106
+
};
107
+
};
108
+
89
109
&blsp_uart2 {
90
110
status = "okay";
91
111
};
···
182
162
sdc2_cd_default: sdc2-cd-default-state {
183
163
pins = "gpio38";
184
164
function = "gpio";
165
+
166
+
drive-strength = <2>;
167
+
bias-disable;
168
+
};
169
+
170
+
tsp_int_default: tsp-int-default-state {
171
+
pins = "gpio13";
172
+
function = "gpio";
173
+
185
174
drive-strength = <2>;
186
175
bias-disable;
187
176
};
+8
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
+8
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
+26
arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts
+26
arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts
···
8
8
model = "Samsung Galaxy J5 (2016)";
9
9
compatible = "samsung,j5x", "qcom,msm8916";
10
10
chassis-type = "handset";
11
+
12
+
reg_vdd_tsp_a: regulator-vdd-tsp-a {
13
+
compatible = "regulator-fixed";
14
+
regulator-name = "vdd_tsp_a";
15
+
regulator-min-microvolt = <3000000>;
16
+
regulator-max-microvolt = <3000000>;
17
+
18
+
gpio = <&tlmm 108 GPIO_ACTIVE_HIGH>;
19
+
enable-active-high;
20
+
21
+
pinctrl-0 = <&tsp_ldo_en_default>;
22
+
pinctrl-names = "default";
23
+
};
11
24
};
12
25
13
26
&muic {
14
27
interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
28
+
};
29
+
30
+
&touchscreen {
31
+
vdd-supply = <®_vdd_tsp_a>;
32
+
};
33
+
34
+
&tlmm {
35
+
tsp_ldo_en_default: tsp-ldo-en-default-state {
36
+
pins = "gpio108";
37
+
function = "gpio";
38
+
drive-strength = <2>;
39
+
bias-disable;
40
+
};
15
41
};
16
42
17
43
&muic_int_default {
+66
-4
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
+66
-4
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
···
142
142
143
143
pinctrl-names = "default";
144
144
pinctrl-0 = <&muic_irq_default>;
145
+
146
+
usb_con: connector {
147
+
compatible = "usb-b-connector";
148
+
label = "micro-USB";
149
+
type = "micro";
150
+
};
145
151
};
146
152
};
147
153
···
205
199
pinctrl-0 = <&nfc_default>;
206
200
};
207
201
};
202
+
203
+
battery: battery {
204
+
compatible = "simple-battery";
205
+
precharge-current-microamp = <450000>;
206
+
constant-charge-current-max-microamp = <1000000>;
207
+
charge-term-current-microamp = <150000>;
208
+
precharge-upper-limit-microvolt = <3500000>;
209
+
constant-charge-voltage-max-microvolt = <4350000>;
210
+
};
208
211
};
209
212
210
213
&blsp_i2c2 {
···
234
219
compatible = "yamaha,yas537";
235
220
reg = <0x2e>;
236
221
237
-
mount-matrix = "0", "1", "0",
238
-
"1", "0", "0",
239
-
"0", "0", "-1";
222
+
mount-matrix = "0", "1", "0",
223
+
"1", "0", "0",
224
+
"0", "0", "-1";
240
225
};
241
226
};
242
227
243
228
&blsp_i2c4 {
244
229
status = "okay";
245
230
246
-
battery@35 {
231
+
fuel-gauge@35 {
247
232
compatible = "richtek,rt5033-battery";
248
233
reg = <0x35>;
249
234
···
252
237
253
238
pinctrl-names = "default";
254
239
pinctrl-0 = <&fg_alert_default>;
240
+
241
+
power-supplies = <&rt5033_charger>;
255
242
};
256
243
};
257
244
···
275
258
276
259
pinctrl-names = "default";
277
260
pinctrl-0 = <&tsp_irq_default>;
261
+
};
262
+
};
263
+
264
+
&blsp_i2c6 {
265
+
status = "okay";
266
+
267
+
pmic@34 {
268
+
compatible = "richtek,rt5033";
269
+
reg = <0x34>;
270
+
271
+
interrupt-parent = <&tlmm>;
272
+
interrupts = <62 IRQ_TYPE_EDGE_FALLING>;
273
+
274
+
pinctrl-names = "default";
275
+
pinctrl-0 = <&pmic_int_default>;
276
+
277
+
regulators {
278
+
rt5033_reg_safe_ldo: SAFE_LDO {
279
+
regulator-min-microvolt = <4900000>;
280
+
regulator-max-microvolt = <4900000>;
281
+
regulator-always-on;
282
+
};
283
+
rt5033_reg_ldo: LDO {
284
+
regulator-min-microvolt = <2800000>;
285
+
regulator-max-microvolt = <2800000>;
286
+
};
287
+
rt5033_reg_buck: BUCK {
288
+
regulator-min-microvolt = <1200000>;
289
+
regulator-max-microvolt = <1200000>;
290
+
};
291
+
};
292
+
293
+
rt5033_charger: charger {
294
+
compatible = "richtek,rt5033-charger";
295
+
monitored-battery = <&battery>;
296
+
richtek,usb-connector = <&usb_con>;
297
+
};
278
298
};
279
299
};
280
300
···
435
381
436
382
nfc_i2c_default: nfc-i2c-default-state {
437
383
pins = "gpio0", "gpio1";
384
+
function = "gpio";
385
+
386
+
drive-strength = <2>;
387
+
bias-disable;
388
+
};
389
+
390
+
pmic_int_default: pmic-int-default-state {
391
+
pins = "gpio62";
438
392
function = "gpio";
439
393
440
394
drive-strength = <2>;
+1
-1
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
+11
-3
arch/arm64/boot/dts/qcom/msm8916.dtsi
+11
-3
arch/arm64/boot/dts/qcom/msm8916.dtsi
···
282
282
};
283
283
};
284
284
285
-
smd {
286
-
compatible = "qcom,smd";
285
+
rpm: remoteproc {
286
+
compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
287
287
288
-
rpm {
288
+
smd-edge {
289
289
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
290
290
qcom,ipc = <&apcs 8 0>;
291
291
qcom,smd-edge = <15>;
···
1712
1712
ports {
1713
1713
#address-cells = <1>;
1714
1714
#size-cells = <0>;
1715
+
1716
+
port@0 {
1717
+
reg = <0>;
1718
+
};
1719
+
1720
+
port@1 {
1721
+
reg = <1>;
1722
+
};
1715
1723
};
1716
1724
};
1717
1725
+495
arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts
+495
arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
/dts-v1/;
4
+
5
+
#include "msm8939-pm8916.dtsi"
6
+
7
+
#include <dt-bindings/gpio/gpio.h>
8
+
#include <dt-bindings/input/input.h>
9
+
#include <dt-bindings/interrupt-controller/irq.h>
10
+
11
+
/ {
12
+
model = "Samsung Galaxy A7 (2015)";
13
+
compatible = "samsung,a7", "qcom,msm8939";
14
+
chassis-type = "handset";
15
+
16
+
aliases {
17
+
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
18
+
mmc1 = &sdhc_2; /* SDC2 SD card slot */
19
+
serial0 = &blsp_uart2;
20
+
};
21
+
22
+
chosen {
23
+
stdout-path = "serial0";
24
+
};
25
+
26
+
reserved-memory {
27
+
/* Additional memory used by Samsung firmware modifications */
28
+
tz-apps@85500000 {
29
+
reg = <0x0 0x85500000 0x0 0xb00000>;
30
+
no-map;
31
+
};
32
+
};
33
+
34
+
gpio-hall-sensor {
35
+
compatible = "gpio-keys";
36
+
37
+
pinctrl-0 = <&gpio_hall_sensor_default>;
38
+
pinctrl-names = "default";
39
+
40
+
label = "GPIO Hall Effect Sensor";
41
+
42
+
event-hall-sensor {
43
+
label = "Hall Effect Sensor";
44
+
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
45
+
linux,input-type = <EV_SW>;
46
+
linux,code = <SW_LID>;
47
+
linux,can-disable;
48
+
};
49
+
};
50
+
51
+
gpio-keys {
52
+
compatible = "gpio-keys";
53
+
54
+
pinctrl-0 = <&gpio_keys_default>;
55
+
pinctrl-names = "default";
56
+
57
+
label = "GPIO Buttons";
58
+
59
+
button-volume-up {
60
+
label = "Volume Up";
61
+
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
62
+
linux,code = <KEY_VOLUMEUP>;
63
+
};
64
+
65
+
button-home {
66
+
label = "Home";
67
+
gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
68
+
linux,code = <KEY_HOMEPAGE>;
69
+
};
70
+
};
71
+
72
+
i2c-fg {
73
+
compatible = "i2c-gpio";
74
+
sda-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
75
+
scl-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
76
+
77
+
pinctrl-0 = <&fg_i2c_default>;
78
+
pinctrl-names = "default";
79
+
80
+
#address-cells = <1>;
81
+
#size-cells = <0>;
82
+
83
+
battery@35 {
84
+
compatible = "richtek,rt5033-battery";
85
+
reg = <0x35>;
86
+
87
+
interrupt-parent = <&tlmm>;
88
+
interrupts = <121 IRQ_TYPE_EDGE_BOTH>;
89
+
90
+
pinctrl-0 = <&fg_alert_default>;
91
+
pinctrl-names = "default";
92
+
};
93
+
};
94
+
95
+
i2c-nfc {
96
+
compatible = "i2c-gpio";
97
+
sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
98
+
scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
99
+
100
+
pinctrl-0 = <&nfc_i2c_default>;
101
+
pinctrl-names = "default";
102
+
103
+
#address-cells = <1>;
104
+
#size-cells = <0>;
105
+
106
+
nfc@2b {
107
+
compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
108
+
reg = <0x2b>;
109
+
110
+
interrupt-parent = <&tlmm>;
111
+
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
112
+
113
+
enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
114
+
firmware-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
115
+
116
+
pinctrl-0 = <&nfc_default>;
117
+
pinctrl-names = "default";
118
+
};
119
+
};
120
+
121
+
i2c-sensor {
122
+
compatible = "i2c-gpio";
123
+
sda-gpios = <&tlmm 84 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
124
+
scl-gpios = <&tlmm 85 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
125
+
126
+
pinctrl-0 = <&sensor_i2c_default>;
127
+
pinctrl-names = "default";
128
+
129
+
#address-cells = <1>;
130
+
#size-cells = <0>;
131
+
132
+
accelerometer: accelerometer@10 {
133
+
compatible = "bosch,bmc150_accel";
134
+
reg = <0x10>;
135
+
interrupt-parent = <&tlmm>;
136
+
interrupts = <115 IRQ_TYPE_EDGE_RISING>;
137
+
138
+
vdd-supply = <&pm8916_l17>;
139
+
vddio-supply = <&pm8916_l5>;
140
+
141
+
pinctrl-0 = <&accel_int_default>;
142
+
pinctrl-names = "default";
143
+
144
+
mount-matrix = "-1", "0", "0",
145
+
"0", "-1", "0",
146
+
"0", "0", "1";
147
+
};
148
+
149
+
magnetometer@12 {
150
+
compatible = "bosch,bmc150_magn";
151
+
reg = <0x12>;
152
+
153
+
vdd-supply = <&pm8916_l17>;
154
+
vddio-supply = <&pm8916_l5>;
155
+
};
156
+
};
157
+
158
+
i2c-tkey {
159
+
compatible = "i2c-gpio";
160
+
sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
161
+
scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
162
+
163
+
pinctrl-0 = <&tkey_i2c_default>;
164
+
pinctrl-names = "default";
165
+
166
+
#address-cells = <1>;
167
+
#size-cells = <0>;
168
+
169
+
touchkey@20 {
170
+
/* Note: Actually an ABOV MCU that implements same interface */
171
+
compatible = "coreriver,tc360-touchkey";
172
+
reg = <0x20>;
173
+
174
+
interrupt-parent = <&tlmm>;
175
+
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
176
+
177
+
vcc-supply = <®_touch_key>;
178
+
vdd-supply = <®_keyled>;
179
+
vddio-supply = <&pm8916_l6>;
180
+
181
+
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
182
+
183
+
pinctrl-0 = <&tkey_default>;
184
+
pinctrl-names = "default";
185
+
};
186
+
};
187
+
188
+
pwm_vibrator: pwm-vibrator {
189
+
compatible = "clk-pwm";
190
+
#pwm-cells = <2>;
191
+
192
+
clocks = <&gcc GCC_GP2_CLK>;
193
+
194
+
pinctrl-0 = <&motor_pwm_default>;
195
+
pinctrl-names = "default";
196
+
};
197
+
198
+
reg_keyled: regulator-keyled {
199
+
compatible = "regulator-fixed";
200
+
regulator-name = "keyled";
201
+
regulator-min-microvolt = <3300000>;
202
+
regulator-max-microvolt = <3300000>;
203
+
204
+
/* NOTE: On some variants e.g. SM-A700FD it's GPIO 91 */
205
+
gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>;
206
+
enable-active-high;
207
+
208
+
pinctrl-0 = <&tkey_led_en_default>;
209
+
pinctrl-names = "default";
210
+
};
211
+
212
+
reg_touch_key: regulator-touch-key {
213
+
compatible = "regulator-fixed";
214
+
regulator-name = "touch_key";
215
+
regulator-min-microvolt = <2800000>;
216
+
regulator-max-microvolt = <2800000>;
217
+
218
+
gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
219
+
enable-active-high;
220
+
221
+
pinctrl-0 = <&tkey_en_default>;
222
+
pinctrl-names = "default";
223
+
};
224
+
225
+
reg_tsp_vdd: regulator-tsp-vdd {
226
+
compatible = "regulator-fixed";
227
+
regulator-name = "tsp_vdd";
228
+
regulator-min-microvolt = <1800000>;
229
+
regulator-max-microvolt = <1800000>;
230
+
vin-supply = <&pm8916_s4>;
231
+
232
+
gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>;
233
+
enable-active-high;
234
+
235
+
pinctrl-0 = <®_tsp_io_en_default>;
236
+
pinctrl-names = "default";
237
+
};
238
+
239
+
reg_vdd_tsp: regulator-vdd-tsp {
240
+
compatible = "regulator-fixed";
241
+
regulator-name = "vdd_tsp";
242
+
regulator-min-microvolt = <3300000>;
243
+
regulator-max-microvolt = <3300000>;
244
+
245
+
gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>;
246
+
enable-active-high;
247
+
248
+
pinctrl-0 = <®_tsp_en_default>;
249
+
pinctrl-names = "default";
250
+
};
251
+
252
+
reg_vibrator: regulator-vibrator {
253
+
compatible = "regulator-fixed";
254
+
regulator-name = "motor_en";
255
+
regulator-min-microvolt = <3000000>;
256
+
regulator-max-microvolt = <3000000>;
257
+
258
+
gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
259
+
enable-active-high;
260
+
261
+
pinctrl-0 = <&motor_en_default>;
262
+
pinctrl-names = "default";
263
+
};
264
+
265
+
vibrator {
266
+
compatible = "pwm-vibrator";
267
+
268
+
pwms = <&pwm_vibrator 0 100000>;
269
+
pwm-names = "enable";
270
+
271
+
vcc-supply = <®_vibrator>;
272
+
};
273
+
};
274
+
275
+
&blsp_i2c1 {
276
+
status = "okay";
277
+
278
+
muic: extcon@25 {
279
+
compatible = "siliconmitus,sm5502-muic";
280
+
reg = <0x25>;
281
+
282
+
interrupt-parent = <&tlmm>;
283
+
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
284
+
285
+
pinctrl-0 = <&muic_int_default>;
286
+
pinctrl-names = "default";
287
+
};
288
+
};
289
+
290
+
&blsp_i2c5 {
291
+
status = "okay";
292
+
293
+
touchscreen@24 {
294
+
compatible = "cypress,tt21000";
295
+
296
+
reg = <0x24>;
297
+
interrupt-parent = <&tlmm>;
298
+
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
299
+
300
+
vdd-supply = <®_vdd_tsp>;
301
+
vddio-supply = <®_tsp_vdd>;
302
+
303
+
pinctrl-0 = <&tsp_int_default>;
304
+
pinctrl-names = "default";
305
+
};
306
+
};
307
+
308
+
&blsp_uart2 {
309
+
status = "okay";
310
+
};
311
+
312
+
&pm8916_resin {
313
+
linux,code = <KEY_VOLUMEDOWN>;
314
+
status = "okay";
315
+
};
316
+
317
+
&pm8916_rpm_regulators {
318
+
pm8916_l17: l17 {
319
+
regulator-min-microvolt = <2850000>;
320
+
regulator-max-microvolt = <2850000>;
321
+
};
322
+
};
323
+
324
+
&sdhc_1 {
325
+
status = "okay";
326
+
};
327
+
328
+
&sdhc_2 {
329
+
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
330
+
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
331
+
pinctrl-names = "default", "sleep";
332
+
333
+
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
334
+
335
+
status = "okay";
336
+
};
337
+
338
+
&usb {
339
+
extcon = <&muic>, <&muic>;
340
+
status = "okay";
341
+
};
342
+
343
+
&usb_hs_phy {
344
+
extcon = <&muic>;
345
+
};
346
+
347
+
&wcnss {
348
+
status = "okay";
349
+
};
350
+
351
+
&wcnss_iris {
352
+
compatible = "qcom,wcn3660b";
353
+
};
354
+
355
+
&tlmm {
356
+
accel_int_default: accel-int-default-state {
357
+
pins = "gpio115";
358
+
function = "gpio";
359
+
drive-strength = <2>;
360
+
bias-disable;
361
+
};
362
+
363
+
fg_alert_default: fg-alert-default-state {
364
+
pins = "gpio121";
365
+
function = "gpio";
366
+
drive-strength = <2>;
367
+
bias-disable;
368
+
};
369
+
370
+
fg_i2c_default: fg-i2c-default-state {
371
+
pins = "gpio105", "gpio106";
372
+
function = "gpio";
373
+
drive-strength = <2>;
374
+
bias-disable;
375
+
};
376
+
377
+
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
378
+
pins = "gpio52";
379
+
function = "gpio";
380
+
drive-strength = <2>;
381
+
bias-disable;
382
+
};
383
+
384
+
gpio_keys_default: gpio-keys-default-state {
385
+
pins = "gpio107", "gpio109";
386
+
function = "gpio";
387
+
drive-strength = <2>;
388
+
bias-pull-up;
389
+
};
390
+
391
+
motor_en_default: motor-en-default-state {
392
+
pins = "gpio86";
393
+
function = "gpio";
394
+
drive-strength = <2>;
395
+
bias-disable;
396
+
};
397
+
398
+
motor_pwm_default: motor-pwm-default-state {
399
+
pins = "gpio50";
400
+
function = "gcc_gp2_clk_a";
401
+
};
402
+
403
+
muic_int_default: muic-int-default-state {
404
+
pins = "gpio12";
405
+
function = "gpio";
406
+
drive-strength = <2>;
407
+
bias-disable;
408
+
};
409
+
410
+
nfc_default: nfc-default-state {
411
+
irq-pins {
412
+
pins = "gpio21";
413
+
function = "gpio";
414
+
drive-strength = <2>;
415
+
bias-pull-down;
416
+
};
417
+
418
+
nfc-pins {
419
+
pins = "gpio49", "gpio116";
420
+
function = "gpio";
421
+
drive-strength = <2>;
422
+
bias-disable;
423
+
};
424
+
};
425
+
426
+
nfc_i2c_default: nfc-i2c-default-state {
427
+
pins = "gpio0", "gpio1";
428
+
function = "gpio";
429
+
drive-strength = <2>;
430
+
bias-disable;
431
+
};
432
+
433
+
reg_tsp_en_default: reg-tsp-en-default-state {
434
+
pins = "gpio73";
435
+
function = "gpio";
436
+
drive-strength = <2>;
437
+
bias-disable;
438
+
};
439
+
440
+
reg_tsp_io_en_default: reg-tsp-io-en-default-state {
441
+
pins = "gpio8";
442
+
function = "gpio";
443
+
drive-strength = <2>;
444
+
bias-disable;
445
+
};
446
+
447
+
sdc2_cd_default: sdc2-cd-default-state {
448
+
pins = "gpio38";
449
+
function = "gpio";
450
+
drive-strength = <2>;
451
+
bias-disable;
452
+
};
453
+
454
+
sensor_i2c_default: sensor-i2c-default-state {
455
+
pins = "gpio84", "gpio85";
456
+
function = "gpio";
457
+
drive-strength = <2>;
458
+
bias-disable;
459
+
};
460
+
461
+
tkey_default: tkey-default-state {
462
+
pins = "gpio20";
463
+
function = "gpio";
464
+
drive-strength = <2>;
465
+
bias-disable;
466
+
};
467
+
468
+
tkey_en_default: tkey-en-default-state {
469
+
pins = "gpio56";
470
+
function = "gpio";
471
+
drive-strength = <2>;
472
+
bias-disable;
473
+
};
474
+
475
+
tkey_i2c_default: tkey-i2c-default-state {
476
+
pins = "gpio16", "gpio17";
477
+
function = "gpio";
478
+
drive-strength = <2>;
479
+
bias-disable;
480
+
};
481
+
482
+
tkey_led_en_default: tkey-led-en-default-state {
483
+
pins = "gpio100";
484
+
function = "gpio";
485
+
drive-strength = <2>;
486
+
bias-disable;
487
+
};
488
+
489
+
tsp_int_default: tsp-int-default-state {
490
+
pins = "gpio13";
491
+
function = "gpio";
492
+
drive-strength = <2>;
493
+
bias-disable;
494
+
};
495
+
};
+2
-1
arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
+2
-1
arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
···
16
16
/ {
17
17
model = "Sony Xperia M4 Aqua";
18
18
compatible = "sony,kanuti-tulip", "qcom,msm8939";
19
+
chassis-type = "handset";
19
20
20
21
qcom,board-id = <QCOM_BOARD_ID_MTP 0>;
21
22
qcom,msm-id = <QCOM_ID_MSM8939 0>, <QCOM_ID_MSM8939 0x30000>;
···
33
32
34
33
usb_id: usb-id {
35
34
compatible = "linux,extcon-usb-gpio";
36
-
id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
35
+
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
37
36
pinctrl-0 = <&usb_id_default>;
38
37
pinctrl-names = "default";
39
38
};
+66
-66
arch/arm64/boot/dts/qcom/msm8939.dtsi
+66
-66
arch/arm64/boot/dts/qcom/msm8939.dtsi
···
55
55
L2_1: l2-cache {
56
56
compatible = "cache";
57
57
cache-level = <2>;
58
+
cache-unified;
58
59
};
59
60
};
60
61
···
112
111
L2_0: l2-cache {
113
112
compatible = "cache";
114
113
cache-level = <2>;
114
+
cache-unified;
115
115
};
116
116
};
117
117
···
157
155
158
156
idle-states {
159
157
CPU_SLEEP_0: cpu-sleep-0 {
160
-
compatible ="qcom,idle-state-spc", "arm,idle-state";
158
+
compatible = "arm,idle-state";
161
159
entry-latency-us = <130>;
162
160
exit-latency-us = <150>;
163
161
min-residency-us = <2000>;
···
242
240
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
243
241
};
244
242
243
+
rpm: remoteproc {
244
+
compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
245
+
246
+
smd-edge {
247
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
248
+
qcom,ipc = <&apcs1_mbox 8 0>;
249
+
qcom,smd-edge = <15>;
250
+
251
+
rpm_requests: rpm-requests {
252
+
compatible = "qcom,rpm-msm8936";
253
+
qcom,smd-channels = "rpm_requests";
254
+
255
+
rpmcc: clock-controller {
256
+
compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
257
+
#clock-cells = <1>;
258
+
clock-names = "xo";
259
+
clocks = <&xo_board>;
260
+
};
261
+
262
+
rpmpd: power-controller {
263
+
compatible = "qcom,msm8939-rpmpd";
264
+
#power-domain-cells = <1>;
265
+
operating-points-v2 = <&rpmpd_opp_table>;
266
+
267
+
rpmpd_opp_table: opp-table {
268
+
compatible = "operating-points-v2";
269
+
270
+
rpmpd_opp_ret: opp1 {
271
+
opp-level = <1>;
272
+
};
273
+
274
+
rpmpd_opp_svs_krait: opp2 {
275
+
opp-level = <2>;
276
+
};
277
+
278
+
rpmpd_opp_svs_soc: opp3 {
279
+
opp-level = <3>;
280
+
};
281
+
282
+
rpmpd_opp_nom: opp4 {
283
+
opp-level = <4>;
284
+
};
285
+
286
+
rpmpd_opp_turbo: opp5 {
287
+
opp-level = <5>;
288
+
};
289
+
290
+
rpmpd_opp_super_turbo: opp6 {
291
+
opp-level = <6>;
292
+
};
293
+
};
294
+
};
295
+
};
296
+
};
297
+
};
298
+
245
299
reserved-memory {
246
300
#address-cells = <2>;
247
301
#size-cells = <2>;
···
366
308
};
367
309
};
368
310
369
-
smd {
370
-
compatible = "qcom,smd";
371
-
372
-
rpm {
373
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
374
-
qcom,ipc = <&apcs1_mbox 8 0>;
375
-
qcom,smd-edge = <15>;
376
-
377
-
rpm_requests: rpm-requests {
378
-
compatible = "qcom,rpm-msm8936";
379
-
qcom,smd-channels = "rpm_requests";
380
-
381
-
rpmcc: clock-controller {
382
-
compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
383
-
#clock-cells = <1>;
384
-
clock-names = "xo";
385
-
clocks = <&xo_board>;
386
-
};
387
-
388
-
rpmpd: power-controller {
389
-
compatible = "qcom,msm8939-rpmpd";
390
-
#power-domain-cells = <1>;
391
-
operating-points-v2 = <&rpmpd_opp_table>;
392
-
393
-
rpmpd_opp_table: opp-table {
394
-
compatible = "operating-points-v2";
395
-
396
-
rpmpd_opp_ret: opp1 {
397
-
opp-level = <1>;
398
-
};
399
-
400
-
rpmpd_opp_svs_krait: opp2 {
401
-
opp-level = <2>;
402
-
};
403
-
404
-
rpmpd_opp_svs_soc: opp3 {
405
-
opp-level = <3>;
406
-
};
407
-
408
-
rpmpd_opp_nom: opp4 {
409
-
opp-level = <4>;
410
-
};
411
-
412
-
rpmpd_opp_turbo: opp5 {
413
-
opp-level = <5>;
414
-
};
415
-
416
-
rpmpd_opp_super_turbo: opp6 {
417
-
opp-level = <6>;
418
-
};
419
-
};
420
-
};
421
-
};
422
-
};
423
-
};
424
-
425
311
smp2p-hexagon {
426
312
compatible = "qcom,smp2p";
427
313
qcom,smem = <435>, <428>;
···
388
386
389
387
interrupt-controller;
390
388
#interrupt-cells = <2>;
391
-
#address-cells = <0>;
392
-
#size-cells = <0>;
393
389
};
394
390
};
395
391
···
1644
1644
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1645
1645
<&gcc GCC_SDCC2_APPS_CLK>,
1646
1646
<&rpmcc RPM_SMD_XO_CLK_SRC>;
1647
-
clock-names = "iface", "core", "xo";
1647
+
clock-names = "iface", "core", "xo";
1648
1648
resets = <&gcc GCC_SDCC2_BCR>;
1649
1649
pinctrl-0 = <&sdc2_default>;
1650
1650
pinctrl-1 = <&sdc2_sleep>;
···
1731
1731
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1732
1732
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1733
1733
<&gcc GCC_BLSP1_AHB_CLK>;
1734
-
clock-names = "core", "iface";
1734
+
clock-names = "core", "iface";
1735
1735
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1736
1736
dma-names = "tx", "rx";
1737
1737
pinctrl-0 = <&blsp_i2c2_default>;
···
1765
1765
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1766
1766
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1767
1767
<&gcc GCC_BLSP1_AHB_CLK>;
1768
-
clock-names = "core", "iface";
1768
+
clock-names = "core", "iface";
1769
1769
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1770
1770
dma-names = "tx", "rx";
1771
1771
pinctrl-0 = <&blsp_i2c3_default>;
···
1799
1799
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1800
1800
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1801
1801
<&gcc GCC_BLSP1_AHB_CLK>;
1802
-
clock-names = "core", "iface";
1802
+
clock-names = "core", "iface";
1803
1803
dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1804
1804
dma-names = "tx", "rx";
1805
1805
pinctrl-0 = <&blsp_i2c4_default>;
···
1833
1833
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1834
1834
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1835
1835
<&gcc GCC_BLSP1_AHB_CLK>;
1836
-
clock-names = "core", "iface";
1836
+
clock-names = "core", "iface";
1837
1837
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1838
1838
dma-names = "tx", "rx";
1839
1839
pinctrl-0 = <&blsp_i2c5_default>;
···
1867
1867
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1868
1868
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1869
1869
<&gcc GCC_BLSP1_AHB_CLK>;
1870
-
clock-names = "core", "iface";
1870
+
clock-names = "core", "iface";
1871
1871
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1872
1872
dma-names = "tx", "rx";
1873
1873
pinctrl-0 = <&blsp_i2c6_default>;
···
1975
1975
};
1976
1976
1977
1977
smd-edge {
1978
-
interrupts = <GIC_SPI 142 1>;
1978
+
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1979
1979
qcom,ipc = <&apcs1_mbox 8 17>;
1980
1980
qcom,smd-edge = <6>;
1981
1981
qcom,remote-pid = <4>;
+2
-2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts
+2
-2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts
···
17
17
compatible = "xiaomi,daisy", "qcom,msm8953";
18
18
chassis-type = "handset";
19
19
qcom,msm-id = <293 0>;
20
-
qcom,board-id= <0x1000b 0x9>;
20
+
qcom,board-id = <0x1000b 0x9>;
21
21
22
22
chosen {
23
23
#address-cells = <2>;
···
125
125
126
126
vmon-slot-no = <1>;
127
127
imon-slot-no = <1>;
128
-
interleave_mode = <0>;
128
+
maxim,interleave-mode;
129
129
130
130
#sound-dai-cells = <0>;
131
131
};
+1
-1
arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts
+1
-2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts
+1
-2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts
···
20
20
compatible = "xiaomi,vince", "qcom,msm8953";
21
21
chassis-type = "handset";
22
22
qcom,msm-id = <293 0>;
23
-
qcom,board-id= <0x1000b 0x08>;
23
+
qcom,board-id = <0x1000b 0x08>;
24
24
25
25
gpio-keys {
26
26
compatible = "gpio-keys";
···
132
132
touchscreen@20 {
133
133
reg = <0x20>;
134
134
compatible = "syna,rmi4-i2c";
135
-
interrupts-parent = <&tlmm>;
136
135
interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>;
137
136
138
137
#address-cells = <1>;
+68
-68
arch/arm64/boot/dts/qcom/msm8953.dtsi
+68
-68
arch/arm64/boot/dts/qcom/msm8953.dtsi
···
190
190
method = "smc";
191
191
};
192
192
193
+
rpm: remoteproc {
194
+
compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
195
+
196
+
smd-edge {
197
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
198
+
qcom,ipc = <&apcs 8 0>;
199
+
qcom,smd-edge = <15>;
200
+
201
+
rpm_requests: rpm-requests {
202
+
compatible = "qcom,rpm-msm8953";
203
+
qcom,smd-channels = "rpm_requests";
204
+
205
+
rpmcc: clock-controller {
206
+
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
207
+
clocks = <&xo_board>;
208
+
clock-names = "xo";
209
+
#clock-cells = <1>;
210
+
};
211
+
212
+
rpmpd: power-controller {
213
+
compatible = "qcom,msm8953-rpmpd";
214
+
#power-domain-cells = <1>;
215
+
operating-points-v2 = <&rpmpd_opp_table>;
216
+
217
+
rpmpd_opp_table: opp-table {
218
+
compatible = "operating-points-v2";
219
+
220
+
rpmpd_opp_ret: opp1 {
221
+
opp-level = <RPM_SMD_LEVEL_RETENTION>;
222
+
};
223
+
224
+
rpmpd_opp_ret_plus: opp2 {
225
+
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
226
+
};
227
+
228
+
rpmpd_opp_min_svs: opp3 {
229
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
230
+
};
231
+
232
+
rpmpd_opp_low_svs: opp4 {
233
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
234
+
};
235
+
236
+
rpmpd_opp_svs: opp5 {
237
+
opp-level = <RPM_SMD_LEVEL_SVS>;
238
+
};
239
+
240
+
rpmpd_opp_svs_plus: opp6 {
241
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
242
+
};
243
+
244
+
rpmpd_opp_nom: opp7 {
245
+
opp-level = <RPM_SMD_LEVEL_NOM>;
246
+
};
247
+
248
+
rpmpd_opp_nom_plus: opp8 {
249
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
250
+
};
251
+
252
+
rpmpd_opp_turbo: opp9 {
253
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
254
+
};
255
+
};
256
+
};
257
+
};
258
+
};
259
+
};
260
+
193
261
reserved-memory {
194
262
#address-cells = <2>;
195
263
#size-cells = <2>;
···
328
260
no-map;
329
261
330
262
qcom,client-id = <1>;
331
-
};
332
-
};
333
-
334
-
smd {
335
-
compatible = "qcom,smd";
336
-
337
-
rpm {
338
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
339
-
qcom,ipc = <&apcs 8 0>;
340
-
qcom,smd-edge = <15>;
341
-
342
-
rpm_requests: rpm-requests {
343
-
compatible = "qcom,rpm-msm8953";
344
-
qcom,smd-channels = "rpm_requests";
345
-
346
-
rpmcc: clock-controller {
347
-
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
348
-
clocks = <&xo_board>;
349
-
clock-names = "xo";
350
-
#clock-cells = <1>;
351
-
};
352
-
353
-
rpmpd: power-controller {
354
-
compatible = "qcom,msm8953-rpmpd";
355
-
#power-domain-cells = <1>;
356
-
operating-points-v2 = <&rpmpd_opp_table>;
357
-
358
-
rpmpd_opp_table: opp-table {
359
-
compatible = "operating-points-v2";
360
-
361
-
rpmpd_opp_ret: opp1 {
362
-
opp-level = <RPM_SMD_LEVEL_RETENTION>;
363
-
};
364
-
365
-
rpmpd_opp_ret_plus: opp2 {
366
-
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
367
-
};
368
-
369
-
rpmpd_opp_min_svs: opp3 {
370
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
371
-
};
372
-
373
-
rpmpd_opp_low_svs: opp4 {
374
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
375
-
};
376
-
377
-
rpmpd_opp_svs: opp5 {
378
-
opp-level = <RPM_SMD_LEVEL_SVS>;
379
-
};
380
-
381
-
rpmpd_opp_svs_plus: opp6 {
382
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
383
-
};
384
-
385
-
rpmpd_opp_nom: opp7 {
386
-
opp-level = <RPM_SMD_LEVEL_NOM>;
387
-
};
388
-
389
-
rpmpd_opp_nom_plus: opp8 {
390
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
391
-
};
392
-
393
-
rpmpd_opp_turbo: opp9 {
394
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
395
-
};
396
-
};
397
-
};
398
-
};
399
263
};
400
264
};
401
265
+77
-77
arch/arm64/boot/dts/qcom/msm8976.dtsi
+77
-77
arch/arm64/boot/dts/qcom/msm8976.dtsi
···
232
232
method = "smc";
233
233
};
234
234
235
+
rpm: remoteproc {
236
+
compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
237
+
238
+
smd-edge {
239
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
240
+
qcom,ipc = <&apcs 8 0>;
241
+
qcom,smd-edge = <15>;
242
+
243
+
rpm_requests: rpm-requests {
244
+
compatible = "qcom,rpm-msm8976";
245
+
qcom,smd-channels = "rpm_requests";
246
+
247
+
rpmcc: clock-controller {
248
+
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
249
+
clocks = <&xo_board>;
250
+
clock-names = "xo";
251
+
#clock-cells = <1>;
252
+
};
253
+
254
+
rpmpd: power-controller {
255
+
compatible = "qcom,msm8976-rpmpd";
256
+
#power-domain-cells = <1>;
257
+
operating-points-v2 = <&rpmpd_opp_table>;
258
+
259
+
rpmpd_opp_table: opp-table {
260
+
compatible = "operating-points-v2";
261
+
262
+
rpmpd_opp_ret: opp1 {
263
+
opp-level = <RPM_SMD_LEVEL_RETENTION>;
264
+
};
265
+
266
+
rpmpd_opp_ret_plus: opp2 {
267
+
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
268
+
};
269
+
270
+
rpmpd_opp_min_svs: opp3 {
271
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
272
+
};
273
+
274
+
rpmpd_opp_low_svs: opp4 {
275
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
276
+
};
277
+
278
+
rpmpd_opp_svs: opp5 {
279
+
opp-level = <RPM_SMD_LEVEL_SVS>;
280
+
};
281
+
282
+
rpmpd_opp_svs_plus: opp6 {
283
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
284
+
};
285
+
286
+
rpmpd_opp_nom: opp7 {
287
+
opp-level = <RPM_SMD_LEVEL_NOM>;
288
+
};
289
+
290
+
rpmpd_opp_nom_plus: opp8 {
291
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
292
+
};
293
+
294
+
rpmpd_opp_turbo: opp9 {
295
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
296
+
};
297
+
298
+
rpmpd_opp_turbo_no_cpr: opp10 {
299
+
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
300
+
};
301
+
302
+
rpmpd_opp_turbo_high: opp111 {
303
+
opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
304
+
};
305
+
};
306
+
};
307
+
};
308
+
};
309
+
};
310
+
235
311
reserved-memory {
236
312
#address-cells = <2>;
237
313
#size-cells = <2>;
···
422
346
};
423
347
};
424
348
425
-
smd {
426
-
compatible = "qcom,smd";
427
-
428
-
rpm {
429
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
430
-
qcom,ipc = <&apcs 8 0>;
431
-
qcom,smd-edge = <15>;
432
-
433
-
rpm_requests: rpm-requests {
434
-
compatible = "qcom,rpm-msm8976";
435
-
qcom,smd-channels = "rpm_requests";
436
-
437
-
rpmcc: clock-controller {
438
-
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
439
-
clocks = <&xo_board>;
440
-
clock-names = "xo";
441
-
#clock-cells = <1>;
442
-
};
443
-
444
-
rpmpd: power-controller {
445
-
compatible = "qcom,msm8976-rpmpd";
446
-
#power-domain-cells = <1>;
447
-
operating-points-v2 = <&rpmpd_opp_table>;
448
-
449
-
rpmpd_opp_table: opp-table {
450
-
compatible = "operating-points-v2";
451
-
452
-
rpmpd_opp_ret: opp1 {
453
-
opp-level = <RPM_SMD_LEVEL_RETENTION>;
454
-
};
455
-
456
-
rpmpd_opp_ret_plus: opp2 {
457
-
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
458
-
};
459
-
460
-
rpmpd_opp_min_svs: opp3 {
461
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
462
-
};
463
-
464
-
rpmpd_opp_low_svs: opp4 {
465
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
466
-
};
467
-
468
-
rpmpd_opp_svs: opp5 {
469
-
opp-level = <RPM_SMD_LEVEL_SVS>;
470
-
};
471
-
472
-
rpmpd_opp_svs_plus: opp6 {
473
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
474
-
};
475
-
476
-
rpmpd_opp_nom: opp7 {
477
-
opp-level = <RPM_SMD_LEVEL_NOM>;
478
-
};
479
-
480
-
rpmpd_opp_nom_plus: opp8 {
481
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
482
-
};
483
-
484
-
rpmpd_opp_turbo: opp9 {
485
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
486
-
};
487
-
488
-
rpmpd_opp_turbo_no_cpr: opp10 {
489
-
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
490
-
};
491
-
492
-
rpmpd_opp_turbo_high: opp111 {
493
-
opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
494
-
};
495
-
};
496
-
};
497
-
};
498
-
};
499
-
};
500
-
501
349
smsm {
502
350
compatible = "qcom,smsm";
503
351
···
439
439
440
440
hexagon_smsm: hexagon@1 {
441
441
reg = <1>;
442
-
interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
442
+
interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>;
443
443
444
444
interrupt-controller;
445
445
#interrupt-cells = <2>;
+51
-50
arch/arm64/boot/dts/qcom/msm8994.dtsi
+51
-50
arch/arm64/boot/dts/qcom/msm8994.dtsi
···
178
178
method = "hvc";
179
179
};
180
180
181
+
rpm: remoteproc {
182
+
compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";
183
+
184
+
smd-edge {
185
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
186
+
qcom,ipc = <&apcs 8 0>;
187
+
qcom,smd-edge = <15>;
188
+
qcom,remote-pid = <6>;
189
+
190
+
rpm_requests: rpm-requests {
191
+
compatible = "qcom,rpm-msm8994";
192
+
qcom,smd-channels = "rpm_requests";
193
+
194
+
rpmcc: clock-controller {
195
+
compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
196
+
#clock-cells = <1>;
197
+
};
198
+
199
+
rpmpd: power-controller {
200
+
compatible = "qcom,msm8994-rpmpd";
201
+
#power-domain-cells = <1>;
202
+
operating-points-v2 = <&rpmpd_opp_table>;
203
+
204
+
rpmpd_opp_table: opp-table {
205
+
compatible = "operating-points-v2";
206
+
207
+
rpmpd_opp_ret: opp1 {
208
+
opp-level = <1>;
209
+
};
210
+
rpmpd_opp_svs_krait: opp2 {
211
+
opp-level = <2>;
212
+
};
213
+
rpmpd_opp_svs_soc: opp3 {
214
+
opp-level = <3>;
215
+
};
216
+
rpmpd_opp_nom: opp4 {
217
+
opp-level = <4>;
218
+
};
219
+
rpmpd_opp_turbo: opp5 {
220
+
opp-level = <5>;
221
+
};
222
+
rpmpd_opp_super_turbo: opp6 {
223
+
opp-level = <6>;
224
+
};
225
+
};
226
+
};
227
+
};
228
+
};
229
+
};
230
+
181
231
reserved-memory {
182
232
#address-cells = <2>;
183
233
#size-cells = <2>;
···
284
234
reserved@6c00000 {
285
235
reg = <0 0x06c00000 0 0x400000>;
286
236
no-map;
287
-
};
288
-
};
289
-
290
-
smd {
291
-
compatible = "qcom,smd";
292
-
rpm {
293
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
294
-
qcom,ipc = <&apcs 8 0>;
295
-
qcom,smd-edge = <15>;
296
-
qcom,remote-pid = <6>;
297
-
298
-
rpm_requests: rpm-requests {
299
-
compatible = "qcom,rpm-msm8994";
300
-
qcom,smd-channels = "rpm_requests";
301
-
302
-
rpmcc: clock-controller {
303
-
compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
304
-
#clock-cells = <1>;
305
-
};
306
-
307
-
rpmpd: power-controller {
308
-
compatible = "qcom,msm8994-rpmpd";
309
-
#power-domain-cells = <1>;
310
-
operating-points-v2 = <&rpmpd_opp_table>;
311
-
312
-
rpmpd_opp_table: opp-table {
313
-
compatible = "operating-points-v2";
314
-
315
-
rpmpd_opp_ret: opp1 {
316
-
opp-level = <1>;
317
-
};
318
-
rpmpd_opp_svs_krait: opp2 {
319
-
opp-level = <2>;
320
-
};
321
-
rpmpd_opp_svs_soc: opp3 {
322
-
opp-level = <3>;
323
-
};
324
-
rpmpd_opp_nom: opp4 {
325
-
opp-level = <4>;
326
-
};
327
-
rpmpd_opp_turbo: opp5 {
328
-
opp-level = <5>;
329
-
};
330
-
rpmpd_opp_super_turbo: opp6 {
331
-
opp-level = <6>;
332
-
};
333
-
};
334
-
};
335
-
};
336
237
};
337
238
};
338
239
···
456
455
usb@f9200000 {
457
456
compatible = "snps,dwc3";
458
457
reg = <0xf9200000 0xcc00>;
459
-
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
458
+
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
460
459
snps,dis_u2_susphy_quirk;
461
460
snps,dis_enblslpm_quirk;
462
461
maximum-speed = "high-speed";
+1
arch/arm64/boot/dts/qcom/msm8996-mtp.dts
+1
arch/arm64/boot/dts/qcom/msm8996-mtp.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+1
-1
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+3
-5
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+3
-5
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
···
187
187
188
188
&blsp2_i2c2 {
189
189
status = "okay";
190
-
label = "NFC_I2C";
191
190
clock-frequency = <400000>;
192
191
193
-
nfc: pn548@28 {
192
+
nfc: nfc@28 {
194
193
compatible = "nxp,nxp-nci-i2c";
195
194
196
195
reg = <0x28>;
···
207
208
208
209
&blsp2_i2c3 {
209
210
status = "okay";
210
-
label = "TYPEC_I2C";
211
211
212
-
typec: tusb320l@47 {
212
+
typec: typec@47 {
213
213
compatible = "ti,tusb320l";
214
214
reg = <0x47>;
215
215
interrupt-parent = <&tlmm>;
···
218
220
219
221
&blsp2_i2c6 {
220
222
status = "okay";
221
-
label = "MSM_TS_I2C";
223
+
/* MSM_TS */
222
224
};
223
225
224
226
&blsp1_uart2 {
+1
-1
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
+124
-69
arch/arm64/boot/dts/qcom/msm8996.dtsi
+124
-69
arch/arm64/boot/dts/qcom/msm8996.dtsi
···
8
8
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9
9
#include <dt-bindings/clock/qcom,rpmcc.h>
10
10
#include <dt-bindings/interconnect/qcom,msm8996.h>
11
+
#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
11
12
#include <dt-bindings/gpio/gpio.h>
12
13
#include <dt-bindings/power/qcom-rpmpd.h>
13
14
#include <dt-bindings/soc/qcom,apr.h>
···
50
49
cpu-idle-states = <&CPU_SLEEP_0>;
51
50
capacity-dmips-mhz = <1024>;
52
51
clocks = <&kryocc 0>;
52
+
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
53
53
operating-points-v2 = <&cluster0_opp>;
54
54
#cooling-cells = <2>;
55
55
next-level-cache = <&L2_0>;
···
69
67
cpu-idle-states = <&CPU_SLEEP_0>;
70
68
capacity-dmips-mhz = <1024>;
71
69
clocks = <&kryocc 0>;
70
+
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
72
71
operating-points-v2 = <&cluster0_opp>;
73
72
#cooling-cells = <2>;
74
73
next-level-cache = <&L2_0>;
···
83
80
cpu-idle-states = <&CPU_SLEEP_0>;
84
81
capacity-dmips-mhz = <1024>;
85
82
clocks = <&kryocc 1>;
83
+
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
86
84
operating-points-v2 = <&cluster1_opp>;
87
85
#cooling-cells = <2>;
88
86
next-level-cache = <&L2_1>;
···
102
98
cpu-idle-states = <&CPU_SLEEP_0>;
103
99
capacity-dmips-mhz = <1024>;
104
100
clocks = <&kryocc 1>;
101
+
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
105
102
operating-points-v2 = <&cluster1_opp>;
106
103
#cooling-cells = <2>;
107
104
next-level-cache = <&L2_1>;
···
154
149
opp-hz = /bits/ 64 <307200000>;
155
150
opp-supported-hw = <0xf>;
156
151
clock-latency-ns = <200000>;
152
+
opp-peak-kBps = <307200>;
157
153
};
158
154
opp-422400000 {
159
155
opp-hz = /bits/ 64 <422400000>;
160
156
opp-supported-hw = <0xf>;
161
157
clock-latency-ns = <200000>;
158
+
opp-peak-kBps = <307200>;
162
159
};
163
160
opp-480000000 {
164
161
opp-hz = /bits/ 64 <480000000>;
165
162
opp-supported-hw = <0xf>;
166
163
clock-latency-ns = <200000>;
164
+
opp-peak-kBps = <307200>;
167
165
};
168
166
opp-556800000 {
169
167
opp-hz = /bits/ 64 <556800000>;
170
168
opp-supported-hw = <0xf>;
171
169
clock-latency-ns = <200000>;
170
+
opp-peak-kBps = <307200>;
172
171
};
173
172
opp-652800000 {
174
173
opp-hz = /bits/ 64 <652800000>;
175
174
opp-supported-hw = <0xf>;
176
175
clock-latency-ns = <200000>;
176
+
opp-peak-kBps = <384000>;
177
177
};
178
178
opp-729600000 {
179
179
opp-hz = /bits/ 64 <729600000>;
180
180
opp-supported-hw = <0xf>;
181
181
clock-latency-ns = <200000>;
182
+
opp-peak-kBps = <460800>;
182
183
};
183
184
opp-844800000 {
184
185
opp-hz = /bits/ 64 <844800000>;
185
186
opp-supported-hw = <0xf>;
186
187
clock-latency-ns = <200000>;
188
+
opp-peak-kBps = <537600>;
187
189
};
188
190
opp-960000000 {
189
191
opp-hz = /bits/ 64 <960000000>;
190
192
opp-supported-hw = <0xf>;
191
193
clock-latency-ns = <200000>;
194
+
opp-peak-kBps = <672000>;
192
195
};
193
196
opp-1036800000 {
194
197
opp-hz = /bits/ 64 <1036800000>;
195
198
opp-supported-hw = <0xf>;
196
199
clock-latency-ns = <200000>;
200
+
opp-peak-kBps = <672000>;
197
201
};
198
202
opp-1113600000 {
199
203
opp-hz = /bits/ 64 <1113600000>;
200
204
opp-supported-hw = <0xf>;
201
205
clock-latency-ns = <200000>;
206
+
opp-peak-kBps = <825600>;
202
207
};
203
208
opp-1190400000 {
204
209
opp-hz = /bits/ 64 <1190400000>;
205
210
opp-supported-hw = <0xf>;
206
211
clock-latency-ns = <200000>;
212
+
opp-peak-kBps = <825600>;
207
213
};
208
214
opp-1228800000 {
209
215
opp-hz = /bits/ 64 <1228800000>;
210
216
opp-supported-hw = <0xf>;
211
217
clock-latency-ns = <200000>;
218
+
opp-peak-kBps = <902400>;
212
219
};
213
220
opp-1324800000 {
214
221
opp-hz = /bits/ 64 <1324800000>;
215
222
opp-supported-hw = <0xd>;
216
223
clock-latency-ns = <200000>;
224
+
opp-peak-kBps = <1056000>;
217
225
};
218
226
opp-1363200000 {
219
227
opp-hz = /bits/ 64 <1363200000>;
220
228
opp-supported-hw = <0x2>;
221
229
clock-latency-ns = <200000>;
230
+
opp-peak-kBps = <1132800>;
222
231
};
223
232
opp-1401600000 {
224
233
opp-hz = /bits/ 64 <1401600000>;
225
234
opp-supported-hw = <0xd>;
226
235
clock-latency-ns = <200000>;
236
+
opp-peak-kBps = <1132800>;
227
237
};
228
238
opp-1478400000 {
229
239
opp-hz = /bits/ 64 <1478400000>;
230
240
opp-supported-hw = <0x9>;
231
241
clock-latency-ns = <200000>;
242
+
opp-peak-kBps = <1190400>;
232
243
};
233
244
opp-1497600000 {
234
245
opp-hz = /bits/ 64 <1497600000>;
235
246
opp-supported-hw = <0x04>;
236
247
clock-latency-ns = <200000>;
248
+
opp-peak-kBps = <1305600>;
237
249
};
238
250
opp-1593600000 {
239
251
opp-hz = /bits/ 64 <1593600000>;
240
252
opp-supported-hw = <0x9>;
241
253
clock-latency-ns = <200000>;
254
+
opp-peak-kBps = <1382400>;
242
255
};
243
256
};
244
257
···
270
247
opp-hz = /bits/ 64 <307200000>;
271
248
opp-supported-hw = <0xf>;
272
249
clock-latency-ns = <200000>;
250
+
opp-peak-kBps = <307200>;
273
251
};
274
252
opp-403200000 {
275
253
opp-hz = /bits/ 64 <403200000>;
276
254
opp-supported-hw = <0xf>;
277
255
clock-latency-ns = <200000>;
256
+
opp-peak-kBps = <307200>;
278
257
};
279
258
opp-480000000 {
280
259
opp-hz = /bits/ 64 <480000000>;
281
260
opp-supported-hw = <0xf>;
282
261
clock-latency-ns = <200000>;
262
+
opp-peak-kBps = <307200>;
283
263
};
284
264
opp-556800000 {
285
265
opp-hz = /bits/ 64 <556800000>;
286
266
opp-supported-hw = <0xf>;
287
267
clock-latency-ns = <200000>;
268
+
opp-peak-kBps = <307200>;
288
269
};
289
270
opp-652800000 {
290
271
opp-hz = /bits/ 64 <652800000>;
291
272
opp-supported-hw = <0xf>;
292
273
clock-latency-ns = <200000>;
274
+
opp-peak-kBps = <307200>;
293
275
};
294
276
opp-729600000 {
295
277
opp-hz = /bits/ 64 <729600000>;
296
278
opp-supported-hw = <0xf>;
297
279
clock-latency-ns = <200000>;
280
+
opp-peak-kBps = <307200>;
298
281
};
299
282
opp-806400000 {
300
283
opp-hz = /bits/ 64 <806400000>;
301
284
opp-supported-hw = <0xf>;
302
285
clock-latency-ns = <200000>;
286
+
opp-peak-kBps = <384000>;
303
287
};
304
288
opp-883200000 {
305
289
opp-hz = /bits/ 64 <883200000>;
306
290
opp-supported-hw = <0xf>;
307
291
clock-latency-ns = <200000>;
292
+
opp-peak-kBps = <460800>;
308
293
};
309
294
opp-940800000 {
310
295
opp-hz = /bits/ 64 <940800000>;
311
296
opp-supported-hw = <0xf>;
312
297
clock-latency-ns = <200000>;
298
+
opp-peak-kBps = <537600>;
313
299
};
314
300
opp-1036800000 {
315
301
opp-hz = /bits/ 64 <1036800000>;
316
302
opp-supported-hw = <0xf>;
317
303
clock-latency-ns = <200000>;
304
+
opp-peak-kBps = <595200>;
318
305
};
319
306
opp-1113600000 {
320
307
opp-hz = /bits/ 64 <1113600000>;
321
308
opp-supported-hw = <0xf>;
322
309
clock-latency-ns = <200000>;
310
+
opp-peak-kBps = <672000>;
323
311
};
324
312
opp-1190400000 {
325
313
opp-hz = /bits/ 64 <1190400000>;
326
314
opp-supported-hw = <0xf>;
327
315
clock-latency-ns = <200000>;
316
+
opp-peak-kBps = <672000>;
328
317
};
329
318
opp-1248000000 {
330
319
opp-hz = /bits/ 64 <1248000000>;
331
320
opp-supported-hw = <0xf>;
332
321
clock-latency-ns = <200000>;
322
+
opp-peak-kBps = <748800>;
333
323
};
334
324
opp-1324800000 {
335
325
opp-hz = /bits/ 64 <1324800000>;
336
326
opp-supported-hw = <0xf>;
337
327
clock-latency-ns = <200000>;
328
+
opp-peak-kBps = <825600>;
338
329
};
339
330
opp-1401600000 {
340
331
opp-hz = /bits/ 64 <1401600000>;
341
332
opp-supported-hw = <0xf>;
342
333
clock-latency-ns = <200000>;
334
+
opp-peak-kBps = <902400>;
343
335
};
344
336
opp-1478400000 {
345
337
opp-hz = /bits/ 64 <1478400000>;
346
338
opp-supported-hw = <0xf>;
347
339
clock-latency-ns = <200000>;
340
+
opp-peak-kBps = <979200>;
348
341
};
349
342
opp-1555200000 {
350
343
opp-hz = /bits/ 64 <1555200000>;
351
344
opp-supported-hw = <0xf>;
352
345
clock-latency-ns = <200000>;
346
+
opp-peak-kBps = <1056000>;
353
347
};
354
348
opp-1632000000 {
355
349
opp-hz = /bits/ 64 <1632000000>;
356
350
opp-supported-hw = <0xf>;
357
351
clock-latency-ns = <200000>;
352
+
opp-peak-kBps = <1190400>;
358
353
};
359
354
opp-1708800000 {
360
355
opp-hz = /bits/ 64 <1708800000>;
361
356
opp-supported-hw = <0xf>;
362
357
clock-latency-ns = <200000>;
358
+
opp-peak-kBps = <1228800>;
363
359
};
364
360
opp-1785600000 {
365
361
opp-hz = /bits/ 64 <1785600000>;
366
362
opp-supported-hw = <0xf>;
367
363
clock-latency-ns = <200000>;
364
+
opp-peak-kBps = <1305600>;
368
365
};
369
366
opp-1804800000 {
370
367
opp-hz = /bits/ 64 <1804800000>;
371
368
opp-supported-hw = <0xe>;
372
369
clock-latency-ns = <200000>;
370
+
opp-peak-kBps = <1305600>;
373
371
};
374
372
opp-1824000000 {
375
373
opp-hz = /bits/ 64 <1824000000>;
376
374
opp-supported-hw = <0x1>;
377
375
clock-latency-ns = <200000>;
376
+
opp-peak-kBps = <1382400>;
378
377
};
379
378
opp-1900800000 {
380
379
opp-hz = /bits/ 64 <1900800000>;
381
380
opp-supported-hw = <0x4>;
382
381
clock-latency-ns = <200000>;
382
+
opp-peak-kBps = <1305600>;
383
383
};
384
384
opp-1920000000 {
385
385
opp-hz = /bits/ 64 <1920000000>;
386
386
opp-supported-hw = <0x1>;
387
387
clock-latency-ns = <200000>;
388
+
opp-peak-kBps = <1459200>;
388
389
};
389
390
opp-1996800000 {
390
391
opp-hz = /bits/ 64 <1996800000>;
391
392
opp-supported-hw = <0x1>;
392
393
clock-latency-ns = <200000>;
394
+
opp-peak-kBps = <1593600>;
393
395
};
394
396
opp-2073600000 {
395
397
opp-hz = /bits/ 64 <2073600000>;
396
398
opp-supported-hw = <0x1>;
397
399
clock-latency-ns = <200000>;
400
+
opp-peak-kBps = <1593600>;
398
401
};
399
402
opp-2150400000 {
400
403
opp-hz = /bits/ 64 <2150400000>;
401
404
opp-supported-hw = <0x1>;
402
405
clock-latency-ns = <200000>;
406
+
opp-peak-kBps = <1593600>;
403
407
};
404
408
};
405
409
···
446
396
psci {
447
397
compatible = "arm,psci-1.0";
448
398
method = "smc";
399
+
};
400
+
401
+
rpm: remoteproc {
402
+
compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
403
+
404
+
glink-edge {
405
+
compatible = "qcom,glink-rpm";
406
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
407
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
408
+
mboxes = <&apcs_glb 0>;
409
+
410
+
rpm_requests: rpm-requests {
411
+
compatible = "qcom,rpm-msm8996";
412
+
qcom,glink-channels = "rpm_requests";
413
+
414
+
rpmcc: clock-controller {
415
+
compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
416
+
#clock-cells = <1>;
417
+
clocks = <&xo_board>;
418
+
clock-names = "xo";
419
+
};
420
+
421
+
rpmpd: power-controller {
422
+
compatible = "qcom,msm8996-rpmpd";
423
+
#power-domain-cells = <1>;
424
+
operating-points-v2 = <&rpmpd_opp_table>;
425
+
426
+
rpmpd_opp_table: opp-table {
427
+
compatible = "operating-points-v2";
428
+
429
+
rpmpd_opp1: opp1 {
430
+
opp-level = <1>;
431
+
};
432
+
433
+
rpmpd_opp2: opp2 {
434
+
opp-level = <2>;
435
+
};
436
+
437
+
rpmpd_opp3: opp3 {
438
+
opp-level = <3>;
439
+
};
440
+
441
+
rpmpd_opp4: opp4 {
442
+
opp-level = <4>;
443
+
};
444
+
445
+
rpmpd_opp5: opp5 {
446
+
opp-level = <5>;
447
+
};
448
+
449
+
rpmpd_opp6: opp6 {
450
+
opp-level = <6>;
451
+
};
452
+
};
453
+
};
454
+
};
455
+
};
449
456
};
450
457
451
458
reserved-memory {
···
579
472
};
580
473
};
581
474
582
-
rpm-glink {
583
-
compatible = "qcom,glink-rpm";
584
-
585
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
586
-
587
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
588
-
589
-
mboxes = <&apcs_glb 0>;
590
-
591
-
rpm_requests: rpm-requests {
592
-
compatible = "qcom,rpm-msm8996";
593
-
qcom,glink-channels = "rpm_requests";
594
-
595
-
rpmcc: clock-controller {
596
-
compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
597
-
#clock-cells = <1>;
598
-
clocks = <&xo_board>;
599
-
clock-names = "xo";
600
-
};
601
-
602
-
rpmpd: power-controller {
603
-
compatible = "qcom,msm8996-rpmpd";
604
-
#power-domain-cells = <1>;
605
-
operating-points-v2 = <&rpmpd_opp_table>;
606
-
607
-
rpmpd_opp_table: opp-table {
608
-
compatible = "operating-points-v2";
609
-
610
-
rpmpd_opp1: opp1 {
611
-
opp-level = <1>;
612
-
};
613
-
614
-
rpmpd_opp2: opp2 {
615
-
opp-level = <2>;
616
-
};
617
-
618
-
rpmpd_opp3: opp3 {
619
-
opp-level = <3>;
620
-
};
621
-
622
-
rpmpd_opp4: opp4 {
623
-
opp-level = <4>;
624
-
};
625
-
626
-
rpmpd_opp5: opp5 {
627
-
opp-level = <5>;
628
-
};
629
-
630
-
rpmpd_opp6: opp6 {
631
-
opp-level = <6>;
632
-
};
633
-
};
634
-
};
635
-
};
636
-
};
637
-
638
475
smem {
639
476
compatible = "qcom,smem";
640
477
memory-region = <&smem_mem>;
···
589
538
compatible = "qcom,smp2p";
590
539
qcom,smem = <443>, <429>;
591
540
592
-
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
541
+
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
593
542
594
543
mboxes = <&apcs_glb 10>;
595
544
···
1126
1075
reg-names = "dsi_ctrl";
1127
1076
1128
1077
interrupt-parent = <&mdss>;
1129
-
interrupts = <4>;
1078
+
interrupts = <5>;
1130
1079
1131
1080
clocks = <&mmcc MDSS_MDP_CLK>,
1132
1081
<&mmcc MDSS_BYTE1_CLK>,
···
1187
1136
status = "disabled";
1188
1137
};
1189
1138
1190
-
mdss_hdmi: mdss_hdmi-tx@9a0000 {
1191
-
compatible = "qcom,mdss_hdmi-tx-8996";
1192
-
reg = <0x009a0000 0x50c>,
1193
-
<0x00070000 0x6158>,
1194
-
<0x009e0000 0xfff>;
1139
+
mdss_hdmi: hdmi-tx@9a0000 {
1140
+
compatible = "qcom,hdmi-tx-8996";
1141
+
reg = <0x009a0000 0x50c>,
1142
+
<0x00070000 0x6158>,
1143
+
<0x009e0000 0xfff>;
1195
1144
reg-names = "core_physical",
1196
1145
"qfprom_physical",
1197
1146
"hdcp_physical";
···
1231
1180
1232
1181
mdss_hdmi_phy: phy@9a0600 {
1233
1182
#phy-cells = <0>;
1234
-
compatible = "qcom,mdss_hdmi-phy-8996";
1183
+
compatible = "qcom,hdmi-phy-8996";
1235
1184
reg = <0x009a0600 0x1c4>,
1236
1185
<0x009a0a00 0x124>,
1237
1186
<0x009a0c00 0x124>,
···
1264
1213
reg = <0x00b00000 0x3f000>;
1265
1214
reg-names = "kgsl_3d0_reg_memory";
1266
1215
1267
-
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1216
+
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1268
1217
1269
1218
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1270
1219
<&mmcc GPU_AHB_CLK>,
···
3054
3003
usb3_dwc3: usb@6a00000 {
3055
3004
compatible = "snps,dwc3";
3056
3005
reg = <0x06a00000 0xcc00>;
3057
-
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3006
+
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3058
3007
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3059
3008
phy-names = "usb2-phy", "usb3-phy";
3060
3009
snps,hird-threshold = /bits/ 8 <0>;
···
3387
3336
#size-cells = <1>;
3388
3337
ranges;
3389
3338
3339
+
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
3340
+
interrupt-names = "hs_phy_irq";
3341
+
3390
3342
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3391
3343
<&gcc GCC_USB20_MASTER_CLK>,
3392
3344
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
···
3412
3358
usb2_dwc3: usb@7600000 {
3413
3359
compatible = "snps,dwc3";
3414
3360
reg = <0x07600000 0xcc00>;
3415
-
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3361
+
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3416
3362
phys = <&hsusb_phy2>;
3417
3363
phy-names = "usb2-phy";
3418
3364
maximum-speed = "high-speed";
···
3426
3372
qcom,controlled-remotely;
3427
3373
reg = <0x09184000 0x32000>;
3428
3374
num-channels = <31>;
3429
-
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3375
+
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3430
3376
#dma-cells = <1>;
3431
3377
qcom,ee = <1>;
3432
3378
qcom,num-ees = <2>;
···
3435
3381
slim_msm: slim-ngd@91c0000 {
3436
3382
compatible = "qcom,slim-ngd-v1.5.0";
3437
3383
reg = <0x091c0000 0x2c000>;
3438
-
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3384
+
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3439
3385
dmas = <&slimbam 3>, <&slimbam 4>;
3440
3386
dma-names = "rx", "tx";
3441
3387
#address-cells = <1>;
···
3605
3551
reg = <0x09a11000 0x10000>;
3606
3552
clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3607
3553
#clock-cells = <0>;
3554
+
#interconnect-cells = <1>;
3608
3555
};
3609
3556
3610
3557
intc: interrupt-controller@9bc0000 {
+1
-1
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
+1
arch/arm64/boot/dts/qcom/msm8998-mtp.dts
+1
arch/arm64/boot/dts/qcom/msm8998-mtp.dts
+2
-2
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
+2
-2
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
···
89
89
90
90
extcon_usb: extcon-usb {
91
91
compatible = "linux,extcon-usb-gpio";
92
-
id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
93
-
vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>;
92
+
id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
93
+
vbus-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
94
94
pinctrl-names = "default";
95
95
pinctrl-0 = <&cc_dir_default &usb_detect_en>;
96
96
};
-1
arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
-1
arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
+351
-66
arch/arm64/boot/dts/qcom/msm8998.dtsi
+351
-66
arch/arm64/boot/dts/qcom/msm8998.dtsi
···
316
316
};
317
317
};
318
318
319
+
dsi_opp_table: opp-table-dsi {
320
+
compatible = "operating-points-v2";
321
+
322
+
opp-131250000 {
323
+
opp-hz = /bits/ 64 <131250000>;
324
+
required-opps = <&rpmpd_opp_low_svs>;
325
+
};
326
+
327
+
opp-210000000 {
328
+
opp-hz = /bits/ 64 <210000000>;
329
+
required-opps = <&rpmpd_opp_svs>;
330
+
};
331
+
332
+
opp-312500000 {
333
+
opp-hz = /bits/ 64 <312500000>;
334
+
required-opps = <&rpmpd_opp_nom>;
335
+
};
336
+
};
337
+
319
338
psci {
320
339
compatible = "arm,psci-1.0";
321
340
method = "smc";
322
341
};
323
342
324
-
rpm-glink {
325
-
compatible = "qcom,glink-rpm";
343
+
rpm: remoteproc {
344
+
compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
326
345
327
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
328
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
329
-
mboxes = <&apcs_glb 0>;
346
+
glink-edge {
347
+
compatible = "qcom,glink-rpm";
330
348
331
-
rpm_requests: rpm-requests {
332
-
compatible = "qcom,rpm-msm8998";
333
-
qcom,glink-channels = "rpm_requests";
349
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
350
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
351
+
mboxes = <&apcs_glb 0>;
334
352
335
-
rpmcc: clock-controller {
336
-
compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
337
-
#clock-cells = <1>;
338
-
};
353
+
rpm_requests: rpm-requests {
354
+
compatible = "qcom,rpm-msm8998";
355
+
qcom,glink-channels = "rpm_requests";
339
356
340
-
rpmpd: power-controller {
341
-
compatible = "qcom,msm8998-rpmpd";
342
-
#power-domain-cells = <1>;
343
-
operating-points-v2 = <&rpmpd_opp_table>;
357
+
rpmcc: clock-controller {
358
+
compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
359
+
clocks = <&xo>;
360
+
clock-names = "xo";
361
+
#clock-cells = <1>;
362
+
};
344
363
345
-
rpmpd_opp_table: opp-table {
346
-
compatible = "operating-points-v2";
364
+
rpmpd: power-controller {
365
+
compatible = "qcom,msm8998-rpmpd";
366
+
#power-domain-cells = <1>;
367
+
operating-points-v2 = <&rpmpd_opp_table>;
347
368
348
-
rpmpd_opp_ret: opp1 {
349
-
opp-level = <RPM_SMD_LEVEL_RETENTION>;
350
-
};
369
+
rpmpd_opp_table: opp-table {
370
+
compatible = "operating-points-v2";
351
371
352
-
rpmpd_opp_ret_plus: opp2 {
353
-
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
354
-
};
372
+
rpmpd_opp_ret: opp1 {
373
+
opp-level = <RPM_SMD_LEVEL_RETENTION>;
374
+
};
355
375
356
-
rpmpd_opp_min_svs: opp3 {
357
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
358
-
};
376
+
rpmpd_opp_ret_plus: opp2 {
377
+
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
378
+
};
359
379
360
-
rpmpd_opp_low_svs: opp4 {
361
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
362
-
};
380
+
rpmpd_opp_min_svs: opp3 {
381
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
382
+
};
363
383
364
-
rpmpd_opp_svs: opp5 {
365
-
opp-level = <RPM_SMD_LEVEL_SVS>;
366
-
};
384
+
rpmpd_opp_low_svs: opp4 {
385
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
386
+
};
367
387
368
-
rpmpd_opp_svs_plus: opp6 {
369
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
370
-
};
388
+
rpmpd_opp_svs: opp5 {
389
+
opp-level = <RPM_SMD_LEVEL_SVS>;
390
+
};
371
391
372
-
rpmpd_opp_nom: opp7 {
373
-
opp-level = <RPM_SMD_LEVEL_NOM>;
374
-
};
392
+
rpmpd_opp_svs_plus: opp6 {
393
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
394
+
};
375
395
376
-
rpmpd_opp_nom_plus: opp8 {
377
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
378
-
};
396
+
rpmpd_opp_nom: opp7 {
397
+
opp-level = <RPM_SMD_LEVEL_NOM>;
398
+
};
379
399
380
-
rpmpd_opp_turbo: opp9 {
381
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
382
-
};
400
+
rpmpd_opp_nom_plus: opp8 {
401
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
402
+
};
383
403
384
-
rpmpd_opp_turbo_plus: opp10 {
385
-
opp-level = <RPM_SMD_LEVEL_BINNING>;
404
+
rpmpd_opp_turbo: opp9 {
405
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
406
+
};
407
+
408
+
rpmpd_opp_turbo_plus: opp10 {
409
+
opp-level = <RPM_SMD_LEVEL_BINNING>;
410
+
};
386
411
};
387
412
};
388
413
};
···
934
909
935
910
pcie0: pci@1c00000 {
936
911
compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
937
-
reg = <0x01c00000 0x2000>,
938
-
<0x1b000000 0xf1d>,
939
-
<0x1b000f20 0xa8>,
940
-
<0x1b100000 0x100000>;
912
+
reg = <0x01c00000 0x2000>,
913
+
<0x1b000000 0xf1d>,
914
+
<0x1b000f20 0xa8>,
915
+
<0x1b100000 0x100000>;
941
916
reg-names = "parf", "dbi", "elbi", "config";
942
917
device_type = "pci";
943
918
linux,pci-domain = <0>;
···
1513
1488
"rbcpr",
1514
1489
"core";
1515
1490
1516
-
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1491
+
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1517
1492
iommus = <&adreno_smmu 0>;
1518
1493
operating-points-v2 = <&gpu_opp_table>;
1519
1494
power-domains = <&rpmpd MSM8998_VDDMX>;
···
1599
1574
reg = <0x05065000 0x9000>;
1600
1575
1601
1576
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1602
-
<&gcc GPLL0_OUT_MAIN>;
1577
+
<&gcc GCC_GPU_GPLL0_CLK>;
1603
1578
clock-names = "xo",
1604
1579
"gpll0";
1605
1580
};
···
2099
2074
2100
2075
spmi_bus: spmi@800f000 {
2101
2076
compatible = "qcom,spmi-pmic-arb";
2102
-
reg = <0x0800f000 0x1000>,
2103
-
<0x08400000 0x1000000>,
2104
-
<0x09400000 0x1000000>,
2105
-
<0x0a400000 0x220000>,
2106
-
<0x0800a000 0x3000>;
2077
+
reg = <0x0800f000 0x1000>,
2078
+
<0x08400000 0x1000000>,
2079
+
<0x09400000 0x1000000>,
2080
+
<0x0a400000 0x220000>,
2081
+
<0x0800a000 0x3000>;
2107
2082
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2108
2083
interrupt-names = "periph_irq";
2109
2084
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
···
2743
2718
"dsi1byte",
2744
2719
"hdmipll",
2745
2720
"dplink",
2746
-
"dpvco";
2721
+
"dpvco",
2722
+
"gpll0_div";
2747
2723
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2748
2724
<&gcc GCC_MMSS_GPLL0_CLK>,
2725
+
<&mdss_dsi0_phy 1>,
2726
+
<&mdss_dsi0_phy 0>,
2727
+
<&mdss_dsi1_phy 1>,
2728
+
<&mdss_dsi1_phy 0>,
2749
2729
<0>,
2750
2730
<0>,
2751
2731
<0>,
2752
-
<0>,
2753
-
<0>,
2754
-
<0>,
2755
-
<0>;
2732
+
<&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2733
+
};
2734
+
2735
+
mdss: display-subsystem@c900000 {
2736
+
compatible = "qcom,msm8998-mdss";
2737
+
reg = <0x0c900000 0x1000>;
2738
+
reg-names = "mdss";
2739
+
2740
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2741
+
interrupt-controller;
2742
+
#interrupt-cells = <1>;
2743
+
2744
+
clocks = <&mmcc MDSS_AHB_CLK>,
2745
+
<&mmcc MDSS_AXI_CLK>,
2746
+
<&mmcc MDSS_MDP_CLK>;
2747
+
clock-names = "iface",
2748
+
"bus",
2749
+
"core";
2750
+
2751
+
power-domains = <&mmcc MDSS_GDSC>;
2752
+
iommus = <&mmss_smmu 0>;
2753
+
2754
+
#address-cells = <1>;
2755
+
#size-cells = <1>;
2756
+
ranges;
2757
+
2758
+
status = "disabled";
2759
+
2760
+
mdss_mdp: display-controller@c901000 {
2761
+
compatible = "qcom,msm8998-dpu";
2762
+
reg = <0x0c901000 0x8f000>,
2763
+
<0x0c9a8e00 0xf0>,
2764
+
<0x0c9b0000 0x2008>,
2765
+
<0x0c9b8000 0x1040>;
2766
+
reg-names = "mdp",
2767
+
"regdma",
2768
+
"vbif",
2769
+
"vbif_nrt";
2770
+
2771
+
interrupt-parent = <&mdss>;
2772
+
interrupts = <0>;
2773
+
2774
+
clocks = <&mmcc MDSS_AHB_CLK>,
2775
+
<&mmcc MDSS_AXI_CLK>,
2776
+
<&mmcc MNOC_AHB_CLK>,
2777
+
<&mmcc MDSS_MDP_CLK>,
2778
+
<&mmcc MDSS_VSYNC_CLK>;
2779
+
clock-names = "iface",
2780
+
"bus",
2781
+
"mnoc",
2782
+
"core",
2783
+
"vsync";
2784
+
2785
+
assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2786
+
assigned-clock-rates = <19200000>;
2787
+
2788
+
operating-points-v2 = <&mdp_opp_table>;
2789
+
power-domains = <&rpmpd MSM8998_VDDMX>;
2790
+
2791
+
mdp_opp_table: opp-table {
2792
+
compatible = "operating-points-v2";
2793
+
2794
+
opp-171430000 {
2795
+
opp-hz = /bits/ 64 <171430000>;
2796
+
required-opps = <&rpmpd_opp_low_svs>;
2797
+
};
2798
+
2799
+
opp-275000000 {
2800
+
opp-hz = /bits/ 64 <275000000>;
2801
+
required-opps = <&rpmpd_opp_svs>;
2802
+
};
2803
+
2804
+
opp-330000000 {
2805
+
opp-hz = /bits/ 64 <330000000>;
2806
+
required-opps = <&rpmpd_opp_nom>;
2807
+
};
2808
+
2809
+
opp-412500000 {
2810
+
opp-hz = /bits/ 64 <412500000>;
2811
+
required-opps = <&rpmpd_opp_turbo>;
2812
+
};
2813
+
};
2814
+
2815
+
ports {
2816
+
#address-cells = <1>;
2817
+
#size-cells = <0>;
2818
+
2819
+
port@0 {
2820
+
reg = <0>;
2821
+
2822
+
dpu_intf1_out: endpoint {
2823
+
remote-endpoint = <&mdss_dsi0_in>;
2824
+
};
2825
+
};
2826
+
2827
+
port@1 {
2828
+
reg = <1>;
2829
+
2830
+
dpu_intf2_out: endpoint {
2831
+
remote-endpoint = <&mdss_dsi1_in>;
2832
+
};
2833
+
};
2834
+
};
2835
+
};
2836
+
2837
+
mdss_dsi0: dsi@c994000 {
2838
+
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2839
+
reg = <0x0c994000 0x400>;
2840
+
reg-names = "dsi_ctrl";
2841
+
2842
+
interrupt-parent = <&mdss>;
2843
+
interrupts = <4>;
2844
+
2845
+
clocks = <&mmcc MDSS_BYTE0_CLK>,
2846
+
<&mmcc MDSS_BYTE0_INTF_CLK>,
2847
+
<&mmcc MDSS_PCLK0_CLK>,
2848
+
<&mmcc MDSS_ESC0_CLK>,
2849
+
<&mmcc MDSS_AHB_CLK>,
2850
+
<&mmcc MDSS_AXI_CLK>;
2851
+
clock-names = "byte",
2852
+
"byte_intf",
2853
+
"pixel",
2854
+
"core",
2855
+
"iface",
2856
+
"bus";
2857
+
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2858
+
<&mmcc PCLK0_CLK_SRC>;
2859
+
assigned-clock-parents = <&mdss_dsi0_phy 0>,
2860
+
<&mdss_dsi0_phy 1>;
2861
+
2862
+
operating-points-v2 = <&dsi_opp_table>;
2863
+
power-domains = <&rpmpd MSM8998_VDDCX>;
2864
+
2865
+
phys = <&mdss_dsi0_phy>;
2866
+
phy-names = "dsi";
2867
+
2868
+
#address-cells = <1>;
2869
+
#size-cells = <0>;
2870
+
2871
+
status = "disabled";
2872
+
2873
+
ports {
2874
+
#address-cells = <1>;
2875
+
#size-cells = <0>;
2876
+
2877
+
port@0 {
2878
+
reg = <0>;
2879
+
2880
+
mdss_dsi0_in: endpoint {
2881
+
remote-endpoint = <&dpu_intf1_out>;
2882
+
};
2883
+
};
2884
+
2885
+
port@1 {
2886
+
reg = <1>;
2887
+
2888
+
mdss_dsi0_out: endpoint {
2889
+
};
2890
+
};
2891
+
};
2892
+
};
2893
+
2894
+
mdss_dsi0_phy: phy@c994400 {
2895
+
compatible = "qcom,dsi-phy-10nm-8998";
2896
+
reg = <0x0c994400 0x200>,
2897
+
<0x0c994600 0x280>,
2898
+
<0x0c994a00 0x1e0>;
2899
+
reg-names = "dsi_phy",
2900
+
"dsi_phy_lane",
2901
+
"dsi_pll";
2902
+
2903
+
clocks = <&mmcc MDSS_AHB_CLK>,
2904
+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
2905
+
clock-names = "iface", "ref";
2906
+
2907
+
#clock-cells = <1>;
2908
+
#phy-cells = <0>;
2909
+
2910
+
status = "disabled";
2911
+
};
2912
+
2913
+
mdss_dsi1: dsi@c996000 {
2914
+
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2915
+
reg = <0x0c996000 0x400>;
2916
+
reg-names = "dsi_ctrl";
2917
+
2918
+
interrupt-parent = <&mdss>;
2919
+
interrupts = <5>;
2920
+
2921
+
clocks = <&mmcc MDSS_BYTE1_CLK>,
2922
+
<&mmcc MDSS_BYTE1_INTF_CLK>,
2923
+
<&mmcc MDSS_PCLK1_CLK>,
2924
+
<&mmcc MDSS_ESC1_CLK>,
2925
+
<&mmcc MDSS_AHB_CLK>,
2926
+
<&mmcc MDSS_AXI_CLK>;
2927
+
clock-names = "byte",
2928
+
"byte_intf",
2929
+
"pixel",
2930
+
"core",
2931
+
"iface",
2932
+
"bus";
2933
+
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2934
+
<&mmcc PCLK1_CLK_SRC>;
2935
+
assigned-clock-parents = <&mdss_dsi1_phy 0>,
2936
+
<&mdss_dsi1_phy 1>;
2937
+
2938
+
operating-points-v2 = <&dsi_opp_table>;
2939
+
power-domains = <&rpmpd MSM8998_VDDCX>;
2940
+
2941
+
phys = <&mdss_dsi1_phy>;
2942
+
phy-names = "dsi";
2943
+
2944
+
#address-cells = <1>;
2945
+
#size-cells = <0>;
2946
+
2947
+
status = "disabled";
2948
+
2949
+
ports {
2950
+
#address-cells = <1>;
2951
+
#size-cells = <0>;
2952
+
2953
+
port@0 {
2954
+
reg = <0>;
2955
+
2956
+
mdss_dsi1_in: endpoint {
2957
+
remote-endpoint = <&dpu_intf2_out>;
2958
+
};
2959
+
};
2960
+
2961
+
port@1 {
2962
+
reg = <1>;
2963
+
2964
+
mdss_dsi1_out: endpoint {
2965
+
};
2966
+
};
2967
+
};
2968
+
};
2969
+
2970
+
mdss_dsi1_phy: phy@c996400 {
2971
+
compatible = "qcom,dsi-phy-10nm-8998";
2972
+
reg = <0x0c996400 0x200>,
2973
+
<0x0c996600 0x280>,
2974
+
<0x0c996a00 0x10e>;
2975
+
reg-names = "dsi_phy",
2976
+
"dsi_phy_lane",
2977
+
"dsi_pll";
2978
+
2979
+
clocks = <&mmcc MDSS_AHB_CLK>,
2980
+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
2981
+
clock-names = "iface",
2982
+
"ref";
2983
+
2984
+
#clock-cells = <1>;
2985
+
#phy-cells = <0>;
2986
+
2987
+
status = "disabled";
2988
+
};
2756
2989
};
2757
2990
2758
2991
mmss_smmu: iommu@cd00000 {
···
3020
2737
3021
2738
clocks = <&mmcc MNOC_AHB_CLK>,
3022
2739
<&mmcc BIMC_SMMU_AHB_CLK>,
3023
-
<&rpmcc RPM_SMD_MMAXI_CLK>,
3024
2740
<&mmcc BIMC_SMMU_AXI_CLK>;
3025
-
clock-names = "iface-mm", "iface-smmu",
3026
-
"bus-mm", "bus-smmu";
2741
+
clock-names = "iface-mm",
2742
+
"iface-smmu",
2743
+
"bus-smmu";
3027
2744
3028
2745
#global-interrupts = <0>;
3029
2746
interrupts =
···
3047
2764
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3048
2765
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3049
2766
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2767
+
2768
+
power-domains = <&mmcc BIMC_SMMU_GDSC>;
3050
2769
};
3051
2770
3052
2771
remoteproc_adsp: remoteproc@17300000 {
+12
-6
arch/arm64/boot/dts/qcom/pm6125.dtsi
+12
-6
arch/arm64/boot/dts/qcom/pm6125.dtsi
···
85
85
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
86
86
#io-channel-cells = <1>;
87
87
88
-
ref-gnd@0 {
88
+
channel@0 {
89
89
reg = <ADC5_REF_GND>;
90
90
qcom,pre-scaling = <1 1>;
91
+
label = "ref_gnd";
91
92
};
92
93
93
-
vref-1p25@1 {
94
+
channel@1 {
94
95
reg = <ADC5_1P25VREF>;
95
96
qcom,pre-scaling = <1 1>;
97
+
label = "vref_1p25";
96
98
};
97
99
98
-
die-temp@6 {
100
+
channel@6 {
99
101
reg = <ADC5_DIE_TEMP>;
100
102
qcom,pre-scaling = <1 1>;
103
+
label = "die_temp";
101
104
};
102
105
103
-
vph-pwr@83 {
106
+
channel@83 {
104
107
reg = <ADC5_VPH_PWR>;
105
108
qcom,pre-scaling = <1 3>;
109
+
label = "vph_pwr";
106
110
};
107
111
108
-
vcoin@85 {
112
+
channel@85 {
109
113
reg = <ADC5_VCOIN>;
110
114
qcom,pre-scaling = <1 3>;
115
+
label = "vcoin";
111
116
};
112
117
113
-
xo-therm@4c {
118
+
channel@4c {
114
119
reg = <ADC5_XO_THERM_100K_PU>;
115
120
qcom,pre-scaling = <1 1>;
116
121
qcom,hw-settle-time = <200>;
117
122
qcom,ratiometric;
123
+
label = "xo_therm";
118
124
};
119
125
};
120
126
+1
-1
arch/arm64/boot/dts/qcom/pm6150.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm6150.dtsi
+7
-6
arch/arm64/boot/dts/qcom/pm6150l.dtsi
+7
-6
arch/arm64/boot/dts/qcom/pm6150l.dtsi
···
60
60
#size-cells = <0>;
61
61
#io-channel-cells = <1>;
62
62
63
-
adc-chan@0 {
63
+
channel@0 {
64
64
reg = <ADC5_REF_GND>;
65
65
qcom,pre-scaling = <1 1>;
66
66
label = "ref_gnd";
67
67
};
68
68
69
-
adc-chan@1 {
69
+
channel@1 {
70
70
reg = <ADC5_1P25VREF>;
71
71
qcom,pre-scaling = <1 1>;
72
72
label = "vref_1p25";
73
73
};
74
74
75
-
adc-chan@6 {
75
+
channel@6 {
76
76
reg = <ADC5_DIE_TEMP>;
77
77
qcom,pre-scaling = <1 1>;
78
78
label = "die_temp";
79
79
};
80
80
81
-
adc-chan@83 {
81
+
channel@83 {
82
82
reg = <ADC5_VPH_PWR>;
83
83
qcom,pre-scaling = <1 3>;
84
84
label = "vph_pwr";
···
121
121
pm6150l_wled: leds@d800 {
122
122
compatible = "qcom,pm6150l-wled";
123
123
reg = <0xd800>, <0xd900>;
124
-
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
125
-
interrupt-names = "ovp";
124
+
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
125
+
<0x5 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
126
+
interrupt-names = "ovp", "short";
126
127
label = "backlight";
127
128
128
129
status = "disabled";
+22
-11
arch/arm64/boot/dts/qcom/pm660.dtsi
+22
-11
arch/arm64/boot/dts/qcom/pm660.dtsi
···
91
91
#size-cells = <0>;
92
92
#io-channel-cells = <1>;
93
93
94
-
ref_gnd: ref_gnd@0 {
94
+
channel@0 {
95
95
reg = <ADC5_REF_GND>;
96
96
qcom,decimation = <1024>;
97
97
qcom,pre-scaling = <1 1>;
98
+
label = "ref_gnd";
98
99
};
99
100
100
-
vref_1p25: vref_1p25@1 {
101
+
channel@1 {
101
102
reg = <ADC5_1P25VREF>;
102
103
qcom,decimation = <1024>;
103
104
qcom,pre-scaling = <1 1>;
105
+
label = "vref_1p25";
104
106
};
105
107
106
-
die_temp: die_temp@6 {
108
+
channel@6 {
107
109
reg = <ADC5_DIE_TEMP>;
108
110
qcom,decimation = <1024>;
109
111
qcom,pre-scaling = <1 1>;
112
+
label = "die_temp";
110
113
};
111
114
112
-
xo_therm: xo_therm@4c {
115
+
channel@4c {
113
116
reg = <ADC5_XO_THERM_100K_PU>;
114
117
qcom,pre-scaling = <1 1>;
115
118
qcom,decimation = <1024>;
116
119
qcom,hw-settle-time = <200>;
117
120
qcom,ratiometric;
121
+
label = "xo_therm";
118
122
};
119
123
120
-
msm_therm: msm_therm@4d {
124
+
channel@4d {
121
125
reg = <ADC5_AMUX_THM1_100K_PU>;
122
126
qcom,pre-scaling = <1 1>;
123
127
qcom,decimation = <1024>;
124
128
qcom,hw-settle-time = <200>;
125
129
qcom,ratiometric;
130
+
label = "msm_therm";
126
131
};
127
132
128
-
emmc_therm: emmc_therm@4e {
133
+
channel@4e {
129
134
reg = <ADC5_AMUX_THM2_100K_PU>;
130
135
qcom,pre-scaling = <1 1>;
131
136
qcom,decimation = <1024>;
132
137
qcom,hw-settle-time = <200>;
133
138
qcom,ratiometric;
139
+
label = "emmc_therm";
134
140
};
135
141
136
-
pa_therm0: thermistor0@4f {
142
+
channel@4f {
137
143
reg = <ADC5_AMUX_THM3_100K_PU>;
138
144
qcom,pre-scaling = <1 1>;
139
145
qcom,decimation = <1024>;
140
146
qcom,hw-settle-time = <200>;
141
147
qcom,ratiometric;
148
+
label = "pa_therm0";
142
149
};
143
150
144
-
pa_therm1: thermistor1@50 {
151
+
channel@50 {
145
152
reg = <ADC5_AMUX_THM4_100K_PU>;
146
153
qcom,pre-scaling = <1 1>;
147
154
qcom,decimation = <1024>;
148
155
qcom,hw-settle-time = <200>;
149
156
qcom,ratiometric;
157
+
label = "pa_therm1";
150
158
};
151
159
152
-
quiet_therm: quiet_therm@51 {
160
+
channel@51 {
153
161
reg = <ADC5_AMUX_THM5_100K_PU>;
154
162
qcom,pre-scaling = <1 1>;
155
163
qcom,decimation = <1024>;
156
164
qcom,hw-settle-time = <200>;
157
165
qcom,ratiometric;
166
+
label = "quiet_therm";
158
167
};
159
168
160
-
vadc_vph_pwr: vph_pwr@83 {
169
+
channel@83 {
161
170
reg = <ADC5_VPH_PWR>;
162
171
qcom,decimation = <1024>;
163
172
qcom,pre-scaling = <1 3>;
173
+
label = "vph_pwr";
164
174
};
165
175
166
-
vcoin: vcoin@85 {
176
+
channel@85 {
167
177
reg = <ADC5_VCOIN>;
168
178
qcom,decimation = <1024>;
169
179
qcom,pre-scaling = <1 3>;
180
+
label = "vcoin";
170
181
};
171
182
};
172
183
+3
-2
arch/arm64/boot/dts/qcom/pm660l.dtsi
+3
-2
arch/arm64/boot/dts/qcom/pm660l.dtsi
···
74
74
pm660l_wled: leds@d800 {
75
75
compatible = "qcom,pm660l-wled";
76
76
reg = <0xd800>, <0xd900>;
77
-
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
78
-
interrupt-names = "ovp";
77
+
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
78
+
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
79
+
interrupt-names = "ovp", "short";
79
80
label = "backlight";
80
81
81
82
status = "disabled";
+22
-12
arch/arm64/boot/dts/qcom/pm7250b.dtsi
+22
-12
arch/arm64/boot/dts/qcom/pm7250b.dtsi
···
62
62
#io-channel-cells = <1>;
63
63
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
64
64
65
-
adc-chan@0 {
65
+
channel@0 {
66
66
reg = <ADC5_REF_GND>;
67
67
qcom,pre-scaling = <1 1>;
68
68
label = "ref_gnd";
69
69
};
70
70
71
-
adc-chan@1 {
71
+
channel@1 {
72
72
reg = <ADC5_1P25VREF>;
73
73
qcom,pre-scaling = <1 1>;
74
74
label = "vref_1p25";
75
75
};
76
76
77
-
adc-chan@2 {
77
+
channel@2 {
78
78
reg = <ADC5_DIE_TEMP>;
79
79
qcom,pre-scaling = <1 1>;
80
80
label = "die_temp";
81
81
};
82
82
83
-
adc-chan@7 {
83
+
channel@7 {
84
84
reg = <ADC5_USB_IN_I>;
85
85
qcom,pre-scaling = <1 1>;
86
86
label = "usb_in_i_uv";
87
87
};
88
88
89
-
adc-chan@8 {
89
+
channel@8 {
90
90
reg = <ADC5_USB_IN_V_16>;
91
91
qcom,pre-scaling = <1 16>;
92
92
label = "usb_in_v_div_16";
93
93
};
94
94
95
-
adc-chan@9 {
95
+
channel@9 {
96
96
reg = <ADC5_CHG_TEMP>;
97
97
qcom,pre-scaling = <1 1>;
98
98
label = "chg_temp";
99
99
};
100
100
101
-
adc-chan@e {
101
+
channel@e {
102
102
reg = <ADC5_AMUX_THM2>;
103
103
qcom,hw-settle-time = <200>;
104
104
qcom,pre-scaling = <1 1>;
105
105
label = "smb1390_therm";
106
106
};
107
107
108
-
adc-chan@1e {
108
+
channel@1e {
109
109
reg = <ADC5_MID_CHG_DIV6>;
110
110
qcom,pre-scaling = <1 6>;
111
111
label = "chg_mid";
112
112
};
113
113
114
-
adc-chan@4b {
114
+
channel@4b {
115
115
reg = <ADC5_BAT_ID_100K_PU>;
116
116
qcom,hw-settle-time = <200>;
117
117
qcom,pre-scaling = <1 1>;
···
119
119
label = "bat_id";
120
120
};
121
121
122
-
adc-chan@83 {
122
+
channel@83 {
123
123
reg = <ADC5_VPH_PWR>;
124
124
qcom,pre-scaling = <1 3>;
125
125
label = "vph_pwr";
126
126
};
127
127
128
-
adc-chan@84 {
128
+
channel@84 {
129
129
reg = <ADC5_VBAT_SNS>;
130
130
qcom,pre-scaling = <1 3>;
131
131
label = "vbat_sns";
132
132
};
133
133
134
-
adc-chan@99 {
134
+
channel@99 {
135
135
reg = <ADC5_SBUx>;
136
136
qcom,pre-scaling = <1 3>;
137
137
label = "chg_sbux";
···
146
146
#address-cells = <1>;
147
147
#size-cells = <0>;
148
148
status = "disabled";
149
+
};
150
+
151
+
pm7250b_gpios: pinctrl@c000 {
152
+
compatible = "qcom,pm7250b-gpio", "qcom,spmi-gpio";
153
+
reg = <0xc000>;
154
+
gpio-controller;
155
+
gpio-ranges = <&pm7250b_gpios 0 0 12>;
156
+
#gpio-cells = <2>;
157
+
interrupt-controller;
158
+
#interrupt-cells = <2>;
149
159
};
150
160
};
151
161
+70
arch/arm64/boot/dts/qcom/pm7550ba.dtsi
+70
arch/arm64/boot/dts/qcom/pm7550ba.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <dt-bindings/interrupt-controller/irq.h>
7
+
#include <dt-bindings/spmi/spmi.h>
8
+
9
+
/ {
10
+
thermal-zones {
11
+
pm7550ba-thermal {
12
+
polling-delay-passive = <100>;
13
+
polling-delay = <0>;
14
+
15
+
thermal-sensors = <&pm7550ba_temp_alarm>;
16
+
17
+
trips {
18
+
trip0 {
19
+
temperature = <95000>;
20
+
hysteresis = <0>;
21
+
type = "passive";
22
+
};
23
+
24
+
trip1 {
25
+
temperature = <115000>;
26
+
hysteresis = <0>;
27
+
type = "hot";
28
+
};
29
+
30
+
trip2 {
31
+
temperature = <145000>;
32
+
hysteresis = <0>;
33
+
type = "critical";
34
+
};
35
+
};
36
+
};
37
+
};
38
+
};
39
+
40
+
&spmi_bus {
41
+
pm7550ba: pmic@7 {
42
+
compatible = "qcom,pm7550ba", "qcom,spmi-pmic";
43
+
reg = <7 SPMI_USID>;
44
+
#address-cells = <1>;
45
+
#size-cells = <0>;
46
+
47
+
pm7550ba_temp_alarm: temp-alarm@a00 {
48
+
compatible = "qcom,spmi-temp-alarm";
49
+
reg = <0xa00>;
50
+
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
51
+
#thermal-sensor-cells = <0>;
52
+
};
53
+
54
+
pm7550ba_gpios: gpio@8800 {
55
+
compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio";
56
+
reg = <0x8800>;
57
+
gpio-controller;
58
+
gpio-ranges = <&pm7550ba_gpios 0 0 8>;
59
+
#gpio-cells = <2>;
60
+
interrupt-controller;
61
+
#interrupt-cells = <2>;
62
+
};
63
+
64
+
pm7550ba_eusb2_repeater: phy@fd00 {
65
+
compatible = "qcom,pm7550ba-eusb2-repeater", "qcom,pm8550b-eusb2-repeater";
66
+
reg = <0xfd00>;
67
+
#phy-cells = <0>;
68
+
};
69
+
};
70
+
};
+3
-3
arch/arm64/boot/dts/qcom/pm8150.dtsi
+3
-3
arch/arm64/boot/dts/qcom/pm8150.dtsi
···
90
90
#io-channel-cells = <1>;
91
91
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
92
92
93
-
ref-gnd@0 {
93
+
channel@0 {
94
94
reg = <ADC5_REF_GND>;
95
95
qcom,pre-scaling = <1 1>;
96
96
label = "ref_gnd";
97
97
};
98
98
99
-
vref-1p25@1 {
99
+
channel@1 {
100
100
reg = <ADC5_1P25VREF>;
101
101
qcom,pre-scaling = <1 1>;
102
102
label = "vref_1p25";
103
103
};
104
104
105
-
die-temp@6 {
105
+
channel@6 {
106
106
reg = <ADC5_DIE_TEMP>;
107
107
qcom,pre-scaling = <1 1>;
108
108
label = "die_temp";
+4
-4
arch/arm64/boot/dts/qcom/pm8150b.dtsi
+4
-4
arch/arm64/boot/dts/qcom/pm8150b.dtsi
···
76
76
#io-channel-cells = <1>;
77
77
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
78
78
79
-
ref-gnd@0 {
79
+
channel@0 {
80
80
reg = <ADC5_REF_GND>;
81
81
qcom,pre-scaling = <1 1>;
82
82
label = "ref_gnd";
83
83
};
84
84
85
-
vref-1p25@1 {
85
+
channel@1 {
86
86
reg = <ADC5_1P25VREF>;
87
87
qcom,pre-scaling = <1 1>;
88
88
label = "vref_1p25";
89
89
};
90
90
91
-
die-temp@6 {
91
+
channel@6 {
92
92
reg = <ADC5_DIE_TEMP>;
93
93
qcom,pre-scaling = <1 1>;
94
94
label = "die_temp";
95
95
};
96
96
97
-
chg-temp@9 {
97
+
channel@9 {
98
98
reg = <ADC5_CHG_TEMP>;
99
99
qcom,pre-scaling = <1 1>;
100
100
label = "chg_temp";
+3
-3
arch/arm64/boot/dts/qcom/pm8150l.dtsi
+3
-3
arch/arm64/boot/dts/qcom/pm8150l.dtsi
···
70
70
#io-channel-cells = <1>;
71
71
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
72
72
73
-
ref-gnd@0 {
73
+
channel@0 {
74
74
reg = <ADC5_REF_GND>;
75
75
qcom,pre-scaling = <1 1>;
76
76
label = "ref_gnd";
77
77
};
78
78
79
-
vref-1p25@1 {
79
+
channel@1 {
80
80
reg = <ADC5_1P25VREF>;
81
81
qcom,pre-scaling = <1 1>;
82
82
label = "vref_1p25";
83
83
};
84
84
85
-
die-temp@6 {
85
+
channel@6 {
86
86
reg = <ADC5_DIE_TEMP>;
87
87
qcom,pre-scaling = <1 1>;
88
88
label = "die_temp";
+1
-1
arch/arm64/boot/dts/qcom/pm8350.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm8350.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm8350b.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm8350b.dtsi
+7
-7
arch/arm64/boot/dts/qcom/pm8916.dtsi
+7
-7
arch/arm64/boot/dts/qcom/pm8916.dtsi
···
66
66
#size-cells = <0>;
67
67
#io-channel-cells = <1>;
68
68
69
-
adc-chan@0 {
69
+
channel@0 {
70
70
reg = <VADC_USBIN>;
71
71
qcom,pre-scaling = <1 10>;
72
72
};
73
-
adc-chan@7 {
73
+
channel@7 {
74
74
reg = <VADC_VSYS>;
75
75
qcom,pre-scaling = <1 3>;
76
76
};
77
-
adc-chan@8 {
77
+
channel@8 {
78
78
reg = <VADC_DIE_TEMP>;
79
79
};
80
-
adc-chan@9 {
80
+
channel@9 {
81
81
reg = <VADC_REF_625MV>;
82
82
};
83
-
adc-chan@a {
83
+
channel@a {
84
84
reg = <VADC_REF_1250MV>;
85
85
};
86
-
adc-chan@e {
86
+
channel@e {
87
87
reg = <VADC_GND_REF>;
88
88
};
89
-
adc-chan@f {
89
+
channel@f {
90
90
reg = <VADC_VDD_VADC>;
91
91
};
92
92
};
+26
-13
arch/arm64/boot/dts/qcom/pm8950.dtsi
+26
-13
arch/arm64/boot/dts/qcom/pm8950.dtsi
···
50
50
#size-cells = <0>;
51
51
#io-channel-cells = <1>;
52
52
53
-
vcoin@5 {
53
+
channel@5 {
54
54
reg = <VADC_VCOIN>;
55
55
qcom,pre-scaling = <1 1>;
56
+
label = "vcoin";
56
57
};
57
58
58
-
vph-pwr@7 {
59
+
channel@7 {
59
60
reg = <VADC_VSYS>;
60
61
qcom,pre-scaling = <1 1>;
62
+
label = "vph_pwr";
61
63
};
62
64
63
-
die-temp@8 {
65
+
channel@8 {
64
66
reg = <VADC_DIE_TEMP>;
65
67
qcom,pre-scaling = <1 1>;
68
+
label = "die_temp";
66
69
};
67
70
68
-
ref-625mv@9 {
71
+
channel@9 {
69
72
reg = <VADC_REF_625MV>;
70
73
qcom,pre-scaling = <1 1>;
74
+
label = "ref_625mv";
71
75
};
72
76
73
-
ref-1250mv@a {
77
+
channel@a {
74
78
reg = <VADC_REF_1250MV>;
75
79
qcom,pre-scaling = <1 1>;
80
+
label = "ref_1250mv";
76
81
};
77
82
78
-
ref-buf-625mv@c {
83
+
channel@c {
79
84
reg = <VADC_SPARE1>;
80
85
qcom,pre-scaling = <1 1>;
86
+
label = "ref_buf_625mv";
81
87
};
82
88
83
-
ref-gnd@e {
89
+
channel@e {
84
90
reg = <VADC_GND_REF>;
91
+
label = "ref_gnd";
85
92
};
86
93
87
-
ref-vdd@f {
94
+
channel@f {
88
95
reg = <VADC_VDD_VADC>;
96
+
label = "ref_vdd";
89
97
};
90
98
91
-
pa-therm1@11 {
99
+
channel@11 {
92
100
reg = <VADC_P_MUX2_1_1>;
93
101
qcom,pre-scaling = <1 1>;
94
102
qcom,ratiometric;
95
103
qcom,hw-settle-time = <200>;
104
+
label = "pa_therm1";
96
105
};
97
106
98
-
case-therm@13 {
107
+
channel@13 {
99
108
reg = <VADC_P_MUX4_1_1>;
100
109
qcom,pre-scaling = <1 1>;
101
110
qcom,ratiometric;
102
111
qcom,hw-settle-time = <200>;
112
+
label = "case_therm";
103
113
};
104
114
105
-
xo-therm@32 {
115
+
channel@32 {
106
116
reg = <VADC_LR_MUX3_XO_THERM>;
107
117
qcom,pre-scaling = <1 1>;
108
118
qcom,ratiometric;
109
119
qcom,hw-settle-time = <200>;
120
+
label = "xo_therm";
110
121
};
111
122
112
-
pa-therm0@36 {
123
+
channel@36 {
113
124
reg = <VADC_LR_MUX7_HW_ID>;
114
125
qcom,pre-scaling = <1 1>;
115
126
qcom,ratiometric;
116
127
qcom,hw-settle-time = <200>;
128
+
label = "pa_therm0";
117
129
};
118
130
119
-
xo-therm-buf@3c {
131
+
channel@3c {
120
132
reg = <VADC_LR_MUX3_BUF_XO_THERM>;
121
133
qcom,pre-scaling = <1 1>;
122
134
qcom,ratiometric;
123
135
qcom,hw-settle-time = <200>;
136
+
label = "xo_therm_buf";
124
137
};
125
138
};
126
139
+38
-7
arch/arm64/boot/dts/qcom/pm8953.dtsi
+38
-7
arch/arm64/boot/dts/qcom/pm8953.dtsi
···
6
6
#include <dt-bindings/input/linux-event-codes.h>
7
7
#include <dt-bindings/spmi/spmi.h>
8
8
9
+
/ {
10
+
thermal-zones {
11
+
pm8953-thermal {
12
+
polling-delay-passive = <0>;
13
+
polling-delay = <0>;
14
+
15
+
thermal-sensors = <&pm8953_temp>;
16
+
17
+
trips {
18
+
trip0 {
19
+
temperature = <105000>;
20
+
hysteresis = <0>;
21
+
type = "passive";
22
+
};
23
+
24
+
trip1 {
25
+
temperature = <125000>;
26
+
hysteresis = <0>;
27
+
type = "hot";
28
+
};
29
+
30
+
trip2 {
31
+
temperature = <145000>;
32
+
hysteresis = <0>;
33
+
type = "critical";
34
+
};
35
+
};
36
+
};
37
+
};
38
+
};
39
+
9
40
&spmi_bus {
10
41
pmic@0 {
11
42
compatible = "qcom,pm8953", "qcom,spmi-pmic";
···
67
36
};
68
37
};
69
38
70
-
temp-alarm@2400 {
39
+
pm8953_temp: temp-alarm@2400 {
71
40
compatible = "qcom,spmi-temp-alarm";
72
41
reg = <0x2400>;
73
42
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
···
84
53
#size-cells = <0>;
85
54
#io-channel-cells = <1>;
86
55
87
-
adc-chan@8 {
56
+
channel@8 {
88
57
reg = <VADC_DIE_TEMP>;
89
58
};
90
-
adc-chan@9 {
59
+
channel@9 {
91
60
reg = <VADC_REF_625MV>;
92
61
};
93
-
adc-chan@a {
62
+
channel@a {
94
63
reg = <VADC_REF_1250MV>;
95
64
};
96
-
adc-chan@c {
65
+
channel@c {
97
66
reg = <VADC_SPARE1>;
98
67
};
99
-
adc-chan@e {
68
+
channel@e {
100
69
reg = <VADC_GND_REF>;
101
70
};
102
-
adc-chan@f {
71
+
channel@f {
103
72
reg = <VADC_VDD_VADC>;
104
73
};
105
74
};
+6
-6
arch/arm64/boot/dts/qcom/pm8994.dtsi
+6
-6
arch/arm64/boot/dts/qcom/pm8994.dtsi
···
83
83
#size-cells = <0>;
84
84
#io-channel-cells = <1>;
85
85
86
-
adc-chan@7 {
86
+
channel@7 {
87
87
reg = <VADC_VSYS>;
88
88
qcom,pre-scaling = <1 3>;
89
89
label = "vph_pwr";
90
90
};
91
-
adc-chan@8 {
91
+
channel@8 {
92
92
reg = <VADC_DIE_TEMP>;
93
93
label = "die_temp";
94
94
};
95
-
adc-chan@9 {
95
+
channel@9 {
96
96
reg = <VADC_REF_625MV>;
97
97
label = "ref_625mv";
98
98
};
99
-
adc-chan@a {
99
+
channel@a {
100
100
reg = <VADC_REF_1250MV>;
101
101
label = "ref_1250mv";
102
102
};
103
-
adc-chan@e {
103
+
channel@e {
104
104
reg = <VADC_GND_REF>;
105
105
};
106
-
adc-chan@f {
106
+
channel@f {
107
107
reg = <VADC_VDD_VADC>;
108
108
};
109
109
};
+1
-1
arch/arm64/boot/dts/qcom/pm8998.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm8998.dtsi
+9
-8
arch/arm64/boot/dts/qcom/pmi8950.dtsi
+9
-8
arch/arm64/boot/dts/qcom/pmi8950.dtsi
···
20
20
#size-cells = <0>;
21
21
#io-channel-cells = <1>;
22
22
23
-
adc-chan@0 {
23
+
channel@0 {
24
24
reg = <VADC_USBIN>;
25
25
qcom,pre-scaling = <1 4>;
26
26
label = "usbin";
27
27
};
28
28
29
-
adc-chan@1 {
29
+
channel@1 {
30
30
reg = <VADC_DCIN>;
31
31
qcom,pre-scaling = <1 4>;
32
32
label = "dcin";
33
33
};
34
34
35
-
adc-chan@2 {
35
+
channel@2 {
36
36
reg = <VADC_VCHG_SNS>;
37
37
qcom,pre-scaling = <1 1>;
38
38
label = "vchg_sns";
39
39
};
40
40
41
-
adc-chan@9 {
41
+
channel@9 {
42
42
reg = <VADC_REF_625MV>;
43
43
qcom,pre-scaling = <1 1>;
44
44
label = "ref_625mv";
45
45
};
46
46
47
-
adc-chan@a {
47
+
channel@a {
48
48
reg = <VADC_REF_1250MV>;
49
49
qcom,pre-scaling = <1 1>;
50
50
label = "ref_1250mv";
51
51
};
52
52
53
-
adc-chan@d {
53
+
channel@d {
54
54
reg = <VADC_SPARE2>;
55
55
qcom,pre-scaling = <1 1>;
56
56
label = "chg_temp";
···
87
87
pmi8950_wled: leds@d800 {
88
88
compatible = "qcom,pmi8950-wled";
89
89
reg = <0xd800>, <0xd900>;
90
-
interrupts = <0x3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
91
-
interrupt-names = "short";
90
+
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
91
+
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
92
+
interrupt-names = "ovp", "short";
92
93
label = "backlight";
93
94
94
95
status = "disabled";
+3
-2
arch/arm64/boot/dts/qcom/pmi8994.dtsi
+3
-2
arch/arm64/boot/dts/qcom/pmi8994.dtsi
···
54
54
pmi8994_wled: wled@d800 {
55
55
compatible = "qcom,pmi8994-wled";
56
56
reg = <0xd800>, <0xd900>;
57
-
interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
58
-
interrupt-names = "short";
57
+
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
58
+
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
59
+
interrupt-names = "ovp", "short";
59
60
qcom,cabc;
60
61
qcom,external-pfet;
61
62
status = "disabled";
+1
-1
arch/arm64/boot/dts/qcom/pmk8350.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pmk8350.dtsi
+3
-3
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
+3
-3
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
···
77
77
#io-channel-cells = <1>;
78
78
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
79
79
80
-
ref-gnd@0 {
80
+
channel@0 {
81
81
reg = <ADC5_REF_GND>;
82
82
qcom,pre-scaling = <1 1>;
83
83
label = "ref_gnd";
84
84
};
85
85
86
-
vref-1p25@1 {
86
+
channel@1 {
87
87
reg = <ADC5_1P25VREF>;
88
88
qcom,pre-scaling = <1 1>;
89
89
label = "vref_1p25";
90
90
};
91
91
92
-
die-temp@6 {
92
+
channel@6 {
93
93
reg = <ADC5_DIE_TEMP>;
94
94
qcom,pre-scaling = <1 1>;
95
95
label = "die_temp";
+3
-3
arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
+3
-3
arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
···
69
69
#io-channel-cells = <1>;
70
70
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
71
71
72
-
ref-gnd@0 {
72
+
channel@0 {
73
73
reg = <ADC5_REF_GND>;
74
74
qcom,pre-scaling = <1 1>;
75
75
label = "ref_gnd";
76
76
};
77
77
78
-
vref-1p25@1 {
78
+
channel@1 {
79
79
reg = <ADC5_1P25VREF>;
80
80
qcom,pre-scaling = <1 1>;
81
81
label = "vref_1p25";
82
82
};
83
83
84
-
die-temp@6 {
84
+
channel@6 {
85
85
reg = <ADC5_DIE_TEMP>;
86
86
qcom,pre-scaling = <1 1>;
87
87
label = "die_temp";
+18
-9
arch/arm64/boot/dts/qcom/pmp8074.dtsi
+18
-9
arch/arm64/boot/dts/qcom/pmp8074.dtsi
···
18
18
#size-cells = <0>;
19
19
#io-channel-cells = <1>;
20
20
21
-
ref-gnd@0 {
21
+
channel@0 {
22
22
reg = <ADC5_REF_GND>;
23
23
qcom,pre-scaling = <1 1>;
24
+
label = "ref_gnd";
24
25
};
25
26
26
-
vref-1p25@1 {
27
+
channel@1 {
27
28
reg = <ADC5_1P25VREF>;
28
29
qcom,pre-scaling = <1 1>;
30
+
label = "vref_1p25";
29
31
};
30
32
31
-
vref-vadc@2 {
33
+
channel@2 {
32
34
reg = <ADC5_VREF_VADC>;
33
35
qcom,pre-scaling = <1 1>;
36
+
label = "vref_vadc";
34
37
};
35
38
36
-
pmic_die: die-temp@6 {
39
+
channel@6 {
37
40
reg = <ADC5_DIE_TEMP>;
38
41
qcom,pre-scaling = <1 1>;
42
+
label = "pmic_die";
39
43
};
40
44
41
-
xo_therm: xo-temp@76 {
45
+
channel@76 {
42
46
reg = <ADC5_XO_THERM_100K_PU>;
43
47
qcom,ratiometric;
44
48
qcom,hw-settle-time = <200>;
45
49
qcom,pre-scaling = <1 1>;
50
+
label = "xo_therm";
46
51
};
47
52
48
-
pa_therm1: thermistor1@77 {
53
+
channel@77 {
49
54
reg = <ADC5_AMUX_THM1_100K_PU>;
50
55
qcom,ratiometric;
51
56
qcom,hw-settle-time = <200>;
52
57
qcom,pre-scaling = <1 1>;
58
+
label = "pa_therm1";
53
59
};
54
60
55
-
pa_therm2: thermistor2@78 {
61
+
channel@78 {
56
62
reg = <ADC5_AMUX_THM2_100K_PU>;
57
63
qcom,ratiometric;
58
64
qcom,hw-settle-time = <200>;
59
65
qcom,pre-scaling = <1 1>;
66
+
label = "pa_therm2";
60
67
};
61
68
62
-
pa_therm3: thermistor3@79 {
69
+
channel@79 {
63
70
reg = <ADC5_AMUX_THM3_100K_PU>;
64
71
qcom,ratiometric;
65
72
qcom,hw-settle-time = <200>;
66
73
qcom,pre-scaling = <1 1>;
74
+
label = "pa_therm3";
67
75
};
68
76
69
-
vph-pwr@131 {
77
+
channel@131 {
70
78
reg = <ADC5_VPH_PWR>;
71
79
qcom,pre-scaling = <1 3>;
80
+
label = "vph_pwr";
72
81
};
73
82
};
74
83
+1
-1
arch/arm64/boot/dts/qcom/pmr735b.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pmr735b.dtsi
+14
-7
arch/arm64/boot/dts/qcom/pms405.dtsi
+14
-7
arch/arm64/boot/dts/qcom/pms405.dtsi
···
81
81
#size-cells = <0>;
82
82
#io-channel-cells = <1>;
83
83
84
-
ref_gnd@0 {
84
+
channel@0 {
85
85
reg = <ADC5_REF_GND>;
86
86
qcom,pre-scaling = <1 1>;
87
+
label = "ref_gnd";
87
88
};
88
89
89
-
vref_1p25@1 {
90
+
channel@1 {
90
91
reg = <ADC5_1P25VREF>;
91
92
qcom,pre-scaling = <1 1>;
93
+
label = "vref_1p25";
92
94
};
93
95
94
-
pon_1: vph_pwr@131 {
96
+
channel@131 {
95
97
reg = <ADC5_VPH_PWR>;
96
98
qcom,pre-scaling = <1 3>;
99
+
label = "vph_pwr";
97
100
};
98
101
99
-
die_temp@6 {
102
+
channel@6 {
100
103
reg = <ADC5_DIE_TEMP>;
101
104
qcom,pre-scaling = <1 1>;
105
+
label = "die_temp";
102
106
};
103
107
104
-
pa_therm1: thermistor1@77 {
108
+
channel@77 {
105
109
reg = <ADC5_AMUX_THM1_100K_PU>;
106
110
qcom,ratiometric;
107
111
qcom,hw-settle-time = <200>;
108
112
qcom,pre-scaling = <1 1>;
113
+
label = "pa_therm1";
109
114
};
110
115
111
-
pa_therm3: thermistor3@79 {
116
+
channel@79 {
112
117
reg = <ADC5_AMUX_THM3_100K_PU>;
113
118
qcom,ratiometric;
114
119
qcom,hw-settle-time = <200>;
115
120
qcom,pre-scaling = <1 1>;
121
+
label = "pa_therm3";
116
122
};
117
123
118
-
xo_therm: xo_temp@76 {
124
+
channel@76 {
119
125
reg = <ADC5_XO_THERM_100K_PU>;
120
126
qcom,ratiometric;
121
127
qcom,hw-settle-time = <200>;
122
128
qcom,pre-scaling = <1 1>;
129
+
label = "xo_therm";
123
130
};
124
131
};
125
132
+64
arch/arm64/boot/dts/qcom/pmx75.dtsi
+64
arch/arm64/boot/dts/qcom/pmx75.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <dt-bindings/interrupt-controller/irq.h>
7
+
#include <dt-bindings/spmi/spmi.h>
8
+
9
+
/ {
10
+
thermal-zones {
11
+
pmx75-thermal {
12
+
polling-delay-passive = <100>;
13
+
polling-delay = <0>;
14
+
15
+
thermal-sensors = <&pmx75_temp_alarm>;
16
+
17
+
trips {
18
+
trip0 {
19
+
temperature = <95000>;
20
+
hysteresis = <0>;
21
+
type = "passive";
22
+
};
23
+
24
+
trip1 {
25
+
temperature = <115000>;
26
+
hysteresis = <0>;
27
+
type = "hot";
28
+
};
29
+
30
+
trip2 {
31
+
temperature = <145000>;
32
+
hysteresis = <0>;
33
+
type = "critical";
34
+
};
35
+
};
36
+
};
37
+
};
38
+
};
39
+
40
+
&spmi_bus {
41
+
pmx75: pmic@1 {
42
+
compatible = "qcom,pmx75", "qcom,spmi-pmic";
43
+
reg = <1 SPMI_USID>;
44
+
#address-cells = <1>;
45
+
#size-cells = <0>;
46
+
47
+
pmx75_temp_alarm: temp-alarm@a00 {
48
+
compatible = "qcom,spmi-temp-alarm";
49
+
reg = <0xa00>;
50
+
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
51
+
#thermal-sensor-cells = <0>;
52
+
};
53
+
54
+
pmx75_gpios: gpio@8800 {
55
+
compatible = "qcom,pmx75-gpio", "qcom,spmi-gpio";
56
+
reg = <0x8800>;
57
+
gpio-controller;
58
+
gpio-ranges = <&pmx75_gpios 0 0 16>;
59
+
#gpio-cells = <2>;
60
+
interrupt-controller;
61
+
#interrupt-cells = <2>;
62
+
};
63
+
};
64
+
};
+94
-64
arch/arm64/boot/dts/qcom/qcm2290.dtsi
+94
-64
arch/arm64/boot/dts/qcom/qcm2290.dtsi
···
198
198
};
199
199
};
200
200
201
+
rpm: remoteproc {
202
+
compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
203
+
204
+
glink-edge {
205
+
compatible = "qcom,glink-rpm";
206
+
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
207
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
208
+
mboxes = <&apcs_glb 0>;
209
+
210
+
rpm_requests: rpm-requests {
211
+
compatible = "qcom,rpm-qcm2290";
212
+
qcom,glink-channels = "rpm_requests";
213
+
214
+
rpmcc: clock-controller {
215
+
compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
216
+
clocks = <&xo_board>;
217
+
clock-names = "xo";
218
+
#clock-cells = <1>;
219
+
};
220
+
221
+
rpmpd: power-controller {
222
+
compatible = "qcom,qcm2290-rpmpd";
223
+
#power-domain-cells = <1>;
224
+
operating-points-v2 = <&rpmpd_opp_table>;
225
+
226
+
rpmpd_opp_table: opp-table {
227
+
compatible = "operating-points-v2";
228
+
229
+
rpmpd_opp_min_svs: opp1 {
230
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
231
+
};
232
+
233
+
rpmpd_opp_low_svs: opp2 {
234
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
235
+
};
236
+
237
+
rpmpd_opp_svs: opp3 {
238
+
opp-level = <RPM_SMD_LEVEL_SVS>;
239
+
};
240
+
241
+
rpmpd_opp_svs_plus: opp4 {
242
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
243
+
};
244
+
245
+
rpmpd_opp_nom: opp5 {
246
+
opp-level = <RPM_SMD_LEVEL_NOM>;
247
+
};
248
+
249
+
rpmpd_opp_nom_plus: opp6 {
250
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
251
+
};
252
+
253
+
rpmpd_opp_turbo: opp7 {
254
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
255
+
};
256
+
257
+
rpmpd_opp_turbo_plus: opp8 {
258
+
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
259
+
};
260
+
};
261
+
};
262
+
};
263
+
};
264
+
};
265
+
201
266
reserved_memory: reserved-memory {
202
267
#address-cells = <2>;
203
268
#size-cells = <2>;
···
350
285
351
286
qcom,client-id = <1>;
352
287
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
353
-
};
354
-
};
355
-
356
-
rpm-glink {
357
-
compatible = "qcom,glink-rpm";
358
-
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
359
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
360
-
mboxes = <&apcs_glb 0>;
361
-
362
-
rpm_requests: rpm-requests {
363
-
compatible = "qcom,rpm-qcm2290";
364
-
qcom,glink-channels = "rpm_requests";
365
-
366
-
rpmcc: clock-controller {
367
-
compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
368
-
clocks = <&xo_board>;
369
-
clock-names = "xo";
370
-
#clock-cells = <1>;
371
-
};
372
-
373
-
rpmpd: power-controller {
374
-
compatible = "qcom,qcm2290-rpmpd";
375
-
#power-domain-cells = <1>;
376
-
operating-points-v2 = <&rpmpd_opp_table>;
377
-
378
-
rpmpd_opp_table: opp-table {
379
-
compatible = "operating-points-v2";
380
-
381
-
rpmpd_opp_min_svs: opp1 {
382
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383
-
};
384
-
385
-
rpmpd_opp_low_svs: opp2 {
386
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387
-
};
388
-
389
-
rpmpd_opp_svs: opp3 {
390
-
opp-level = <RPM_SMD_LEVEL_SVS>;
391
-
};
392
-
393
-
rpmpd_opp_svs_plus: opp4 {
394
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395
-
};
396
-
397
-
rpmpd_opp_nom: opp5 {
398
-
opp-level = <RPM_SMD_LEVEL_NOM>;
399
-
};
400
-
401
-
rpmpd_opp_nom_plus: opp6 {
402
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403
-
};
404
-
405
-
rpmpd_opp_turbo: opp7 {
406
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
407
-
};
408
-
409
-
rpmpd_opp_turbo_plus: opp8 {
410
-
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
411
-
};
412
-
};
413
-
};
414
288
};
415
289
};
416
290
···
642
638
status = "disabled";
643
639
};
644
640
641
+
usb_qmpphy: phy@1615000 {
642
+
compatible = "qcom,qcm2290-qmp-usb3-phy";
643
+
reg = <0x0 0x01615000 0x0 0x1000>;
644
+
645
+
clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
646
+
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
647
+
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
648
+
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
649
+
clock-names = "cfg_ahb",
650
+
"ref",
651
+
"com_aux",
652
+
"pipe";
653
+
654
+
resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
655
+
<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
656
+
reset-names = "phy",
657
+
"phy_phy";
658
+
659
+
#clock-cells = <0>;
660
+
clock-output-names = "usb3_phy_pipe_clk_src";
661
+
662
+
#phy-cells = <0>;
663
+
664
+
status = "disabled";
665
+
};
666
+
645
667
qfprom@1b44000 {
646
668
compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
647
669
reg = <0x0 0x01b44000 0x0 0x3000>;
···
820
790
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
821
791
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
822
792
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
823
-
dma-channels = <10>;
793
+
dma-channels = <10>;
824
794
dma-channel-mask = <0x1f>;
825
795
iommus = <&apps_smmu 0xf6 0x0>;
826
796
#dma-cells = <3>;
···
1092
1062
compatible = "snps,dwc3";
1093
1063
reg = <0x0 0x04e00000 0x0 0xcd00>;
1094
1064
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1095
-
phys = <&usb_hsphy>;
1096
-
phy-names = "usb2-phy";
1065
+
phys = <&usb_hsphy>, <&usb_qmpphy>;
1066
+
phy-names = "usb2-phy", "usb3-phy";
1097
1067
iommus = <&apps_smmu 0x120 0x0>;
1098
1068
snps,dis_u2_susphy_quirk;
1099
1069
snps,dis_enblslpm_quirk;
+82
-78
arch/arm64/boot/dts/qcom/qcs404.dtsi
+82
-78
arch/arm64/boot/dts/qcom/qcs404.dtsi
···
166
166
method = "smc";
167
167
};
168
168
169
+
rpm: remoteproc {
170
+
compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
171
+
172
+
glink-edge {
173
+
compatible = "qcom,glink-rpm";
174
+
175
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
176
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
177
+
mboxes = <&apcs_glb 0>;
178
+
179
+
rpm_requests: rpm-requests {
180
+
compatible = "qcom,rpm-qcs404";
181
+
qcom,glink-channels = "rpm_requests";
182
+
183
+
rpmcc: clock-controller {
184
+
compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
185
+
#clock-cells = <1>;
186
+
clocks = <&xo_board>;
187
+
clock-names = "xo";
188
+
};
189
+
190
+
rpmpd: power-controller {
191
+
compatible = "qcom,qcs404-rpmpd";
192
+
#power-domain-cells = <1>;
193
+
operating-points-v2 = <&rpmpd_opp_table>;
194
+
195
+
rpmpd_opp_table: opp-table {
196
+
compatible = "operating-points-v2";
197
+
198
+
rpmpd_opp_ret: opp1 {
199
+
opp-level = <16>;
200
+
};
201
+
202
+
rpmpd_opp_ret_plus: opp2 {
203
+
opp-level = <32>;
204
+
};
205
+
206
+
rpmpd_opp_min_svs: opp3 {
207
+
opp-level = <48>;
208
+
};
209
+
210
+
rpmpd_opp_low_svs: opp4 {
211
+
opp-level = <64>;
212
+
};
213
+
214
+
rpmpd_opp_svs: opp5 {
215
+
opp-level = <128>;
216
+
};
217
+
218
+
rpmpd_opp_svs_plus: opp6 {
219
+
opp-level = <192>;
220
+
};
221
+
222
+
rpmpd_opp_nom: opp7 {
223
+
opp-level = <256>;
224
+
};
225
+
226
+
rpmpd_opp_nom_plus: opp8 {
227
+
opp-level = <320>;
228
+
};
229
+
230
+
rpmpd_opp_turbo: opp9 {
231
+
opp-level = <384>;
232
+
};
233
+
234
+
rpmpd_opp_turbo_no_cpr: opp10 {
235
+
opp-level = <416>;
236
+
};
237
+
238
+
rpmpd_opp_turbo_plus: opp11 {
239
+
opp-level = <512>;
240
+
};
241
+
};
242
+
};
243
+
};
244
+
};
245
+
};
246
+
169
247
reserved-memory {
170
248
#address-cells = <2>;
171
249
#size-cells = <2>;
···
292
214
uefi_mem: memory@9f800000 {
293
215
reg = <0 0x9f800000 0 0x800000>;
294
216
no-map;
295
-
};
296
-
};
297
-
298
-
rpm-glink {
299
-
compatible = "qcom,glink-rpm";
300
-
301
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
302
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
303
-
mboxes = <&apcs_glb 0>;
304
-
305
-
rpm_requests: rpm-requests {
306
-
compatible = "qcom,rpm-qcs404";
307
-
qcom,glink-channels = "rpm_requests";
308
-
309
-
rpmcc: clock-controller {
310
-
compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
311
-
#clock-cells = <1>;
312
-
clocks = <&xo_board>;
313
-
clock-names = "xo";
314
-
};
315
-
316
-
rpmpd: power-controller {
317
-
compatible = "qcom,qcs404-rpmpd";
318
-
#power-domain-cells = <1>;
319
-
operating-points-v2 = <&rpmpd_opp_table>;
320
-
321
-
rpmpd_opp_table: opp-table {
322
-
compatible = "operating-points-v2";
323
-
324
-
rpmpd_opp_ret: opp1 {
325
-
opp-level = <16>;
326
-
};
327
-
328
-
rpmpd_opp_ret_plus: opp2 {
329
-
opp-level = <32>;
330
-
};
331
-
332
-
rpmpd_opp_min_svs: opp3 {
333
-
opp-level = <48>;
334
-
};
335
-
336
-
rpmpd_opp_low_svs: opp4 {
337
-
opp-level = <64>;
338
-
};
339
-
340
-
rpmpd_opp_svs: opp5 {
341
-
opp-level = <128>;
342
-
};
343
-
344
-
rpmpd_opp_svs_plus: opp6 {
345
-
opp-level = <192>;
346
-
};
347
-
348
-
rpmpd_opp_nom: opp7 {
349
-
opp-level = <256>;
350
-
};
351
-
352
-
rpmpd_opp_nom_plus: opp8 {
353
-
opp-level = <320>;
354
-
};
355
-
356
-
rpmpd_opp_turbo: opp9 {
357
-
opp-level = <384>;
358
-
};
359
-
360
-
rpmpd_opp_turbo_no_cpr: opp10 {
361
-
opp-level = <416>;
362
-
};
363
-
364
-
rpmpd_opp_turbo_plus: opp11 {
365
-
opp-level = <512>;
366
-
};
367
-
};
368
-
};
369
217
};
370
218
};
371
219
···
1463
1459
1464
1460
pcie: pci@10000000 {
1465
1461
compatible = "qcom,pcie-qcs404";
1466
-
reg = <0x10000000 0xf1d>,
1467
-
<0x10000f20 0xa8>,
1468
-
<0x07780000 0x2000>,
1469
-
<0x10001000 0x2000>;
1462
+
reg = <0x10000000 0xf1d>,
1463
+
<0x10000f20 0xa8>,
1464
+
<0x07780000 0x2000>,
1465
+
<0x10001000 0x2000>;
1470
1466
reg-names = "dbi", "elbi", "parf", "config";
1471
1467
device_type = "pci";
1472
1468
linux,pci-domain = <0>;
+26
arch/arm64/boot/dts/qcom/qdu1000-idp.dts
+26
arch/arm64/boot/dts/qcom/qdu1000-idp.dts
···
448
448
status = "okay";
449
449
};
450
450
451
+
&reserved_memory {
452
+
ecc_meta_data_mem: ecc-meta-data@e0000000 {
453
+
reg = <0x0 0xe0000000 0x0 0x20000000>;
454
+
no-map;
455
+
};
456
+
457
+
harq_buffer_mem: harq-buffer@800000000 {
458
+
reg = <0x8 0x0 0x0 0x80000000>;
459
+
no-map;
460
+
};
461
+
462
+
tenx_sp_buffer_mem: tenx-sp-buffer@880000000 {
463
+
reg = <0x8 0x80000000 0x0 0x50000000>;
464
+
no-map;
465
+
};
466
+
467
+
fapi_buffer_mem: fapi-buffer@8d0000000 {
468
+
reg = <0x8 0xd0000000 0x0 0x20000000>;
469
+
no-map;
470
+
};
471
+
};
472
+
451
473
&sdhc {
452
474
pinctrl-0 = <&sdc_on_state>;
453
475
pinctrl-1 = <&sdc_off_state>;
···
491
469
vqmmc-supply = <&vreg_l7a_1p8>;
492
470
493
471
status = "okay";
472
+
};
473
+
474
+
&tlmm {
475
+
gpio-reserved-ranges = <28 2>;
494
476
};
495
477
496
478
&uart7 {
+266
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
+266
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
···
38
38
wakeup-source;
39
39
};
40
40
};
41
+
42
+
vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 {
43
+
compatible = "regulator-fixed";
44
+
regulator-name = "VREG_HDMI_OUT_1P2";
45
+
regulator-min-microvolt = <1200000>;
46
+
regulator-max-microvolt = <1200000>;
47
+
vin-supply = <&vdc_1v2>;
48
+
regulator-always-on;
49
+
regulator-boot-on;
50
+
};
51
+
52
+
lt9611_3v3: regulator-lt9611-3v3 {
53
+
compatible = "regulator-fixed";
54
+
regulator-name = "LT9611_3V3";
55
+
regulator-min-microvolt = <3300000>;
56
+
regulator-max-microvolt = <3300000>;
57
+
vin-supply = <&vdc_3v3>;
58
+
regulator-always-on;
59
+
regulator-boot-on;
60
+
};
61
+
62
+
/* Main barrel jack input */
63
+
vdc_12v: regulator-vdc-12v {
64
+
compatible = "regulator-fixed";
65
+
regulator-name = "DC_12V";
66
+
regulator-min-microvolt = <12000000>;
67
+
regulator-max-microvolt = <12000000>;
68
+
regulator-always-on;
69
+
regulator-boot-on;
70
+
};
71
+
72
+
/* 1.2V supply stepped down from the barrel jack input */
73
+
vdc_1v2: regulator-vdc-1v2 {
74
+
compatible = "regulator-fixed";
75
+
regulator-name = "VDC_1V2";
76
+
regulator-min-microvolt = <1200000>;
77
+
regulator-max-microvolt = <1200000>;
78
+
vin-supply = <&vdc_12v>;
79
+
regulator-always-on;
80
+
regulator-boot-on;
81
+
};
82
+
83
+
/* 3.3V supply stepped down from the barrel jack input */
84
+
vdc_3v3: regulator-vdc-3v3 {
85
+
compatible = "regulator-fixed";
86
+
regulator-name = "VDC_3V3";
87
+
regulator-min-microvolt = <3300000>;
88
+
regulator-max-microvolt = <3300000>;
89
+
vin-supply = <&vdc_12v>;
90
+
regulator-always-on;
91
+
regulator-boot-on;
92
+
};
93
+
94
+
/* 5V supply stepped down from the barrel jack input */
95
+
vdc_5v: regulator-vdc-5v {
96
+
compatible = "regulator-fixed";
97
+
regulator-name = "VDC_5V";
98
+
99
+
regulator-min-microvolt = <5000000>;
100
+
regulator-max-microvolt = <5000000>;
101
+
regulator-always-on;
102
+
regulator-boot-on;
103
+
};
104
+
105
+
/* "Battery" voltage for the SoM, stepped down from the barrel jack input */
106
+
vdc_vbat_som: regulator-vdc-vbat {
107
+
compatible = "regulator-fixed";
108
+
regulator-name = "VBAT_SOM";
109
+
regulator-min-microvolt = <4200000>;
110
+
regulator-max-microvolt = <4200000>;
111
+
regulator-always-on;
112
+
regulator-boot-on;
113
+
};
114
+
115
+
/* PM2250 charger out, supplied by VBAT */
116
+
vph_pwr: regulator-vph-pwr {
117
+
compatible = "regulator-fixed";
118
+
regulator-name = "vph_pwr";
119
+
regulator-min-microvolt = <3700000>;
120
+
regulator-max-microvolt = <3700000>;
121
+
vin-supply = <&vdc_vbat_som>;
122
+
123
+
regulator-always-on;
124
+
regulator-boot-on;
125
+
};
41
126
};
42
127
43
128
&pm2250_resin {
···
134
49
status = "okay";
135
50
};
136
51
52
+
&rpm_requests {
53
+
regulators {
54
+
compatible = "qcom,rpm-pm2250-regulators";
55
+
vdd_s3-supply = <&vph_pwr>;
56
+
vdd_s4-supply = <&vph_pwr>;
57
+
vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>;
58
+
vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>;
59
+
vdd_l13_l14_l15_l16-supply = <&pm2250_s4>;
60
+
61
+
/*
62
+
* S1 - VDD_APC
63
+
* S2 - VDD_CX
64
+
*/
65
+
66
+
pm2250_s3: s3 {
67
+
/* 0.4V-1.6625V -> 1.3V (Power tree requirements) */
68
+
regulator-min-microvolts = <1350000>;
69
+
regulator-max-microvolts = <1350000>;
70
+
regulator-boot-on;
71
+
};
72
+
73
+
pm2250_s4: s4 {
74
+
/* 1.2V-2.35V -> 2.05V (Power tree requirements) */
75
+
regulator-min-microvolts = <2072000>;
76
+
regulator-max-microvolts = <2072000>;
77
+
regulator-boot-on;
78
+
};
79
+
80
+
/* L1 - VDD_MX */
81
+
82
+
pm2250_l2: l2 {
83
+
/* LPDDR4X VDD2 */
84
+
regulator-min-microvolts = <1136000>;
85
+
regulator-max-microvolts = <1136000>;
86
+
regulator-always-on;
87
+
regulator-boot-on;
88
+
};
89
+
90
+
pm2250_l3: l3 {
91
+
/* LPDDR4X VDDQ */
92
+
regulator-min-microvolts = <616000>;
93
+
regulator-max-microvolts = <616000>;
94
+
regulator-always-on;
95
+
regulator-boot-on;
96
+
};
97
+
98
+
pm2250_l4: l4 {
99
+
/* max = 3.05V -> max = just below 3V (SDHCI2) */
100
+
regulator-min-microvolts = <1648000>;
101
+
regulator-max-microvolts = <2992000>;
102
+
regulator-allow-set-load;
103
+
};
104
+
105
+
pm2250_l5: l5 {
106
+
/* CSI/DSI */
107
+
regulator-min-microvolts = <1232000>;
108
+
regulator-max-microvolts = <1232000>;
109
+
regulator-allow-set-load;
110
+
regulator-boot-on;
111
+
};
112
+
113
+
pm2250_l6: l6 {
114
+
/* DRAM PLL */
115
+
regulator-min-microvolts = <928000>;
116
+
regulator-max-microvolts = <928000>;
117
+
regulator-always-on;
118
+
regulator-boot-on;
119
+
};
120
+
121
+
pm2250_l7: l7 {
122
+
/* Wi-Fi CX/MX */
123
+
regulator-min-microvolts = <664000>;
124
+
regulator-max-microvolts = <664000>;
125
+
};
126
+
127
+
/*
128
+
* L8 - VDD_LPI_CX
129
+
* L9 - VDD_LPI_MX
130
+
*/
131
+
132
+
pm2250_l10: l10 {
133
+
/* Wi-Fi RFA */
134
+
regulator-min-microvolts = <1300000>;
135
+
regulator-max-microvolts = <1300000>;
136
+
};
137
+
138
+
pm2250_l11: l11 {
139
+
/* GPS RF1 */
140
+
regulator-min-microvolts = <1000000>;
141
+
regulator-max-microvolts = <1000000>;
142
+
regulator-boot-on;
143
+
};
144
+
145
+
pm2250_l12: l12 {
146
+
/* USB PHYs */
147
+
regulator-min-microvolts = <928000>;
148
+
regulator-max-microvolts = <928000>;
149
+
regulator-allow-set-load;
150
+
regulator-boot-on;
151
+
};
152
+
153
+
pm2250_l13: l13 {
154
+
/* USB/QFPROM/PLLs */
155
+
regulator-min-microvolts = <1800000>;
156
+
regulator-max-microvolts = <1800000>;
157
+
regulator-allow-set-load;
158
+
regulator-boot-on;
159
+
};
160
+
161
+
pm2250_l14: l14 {
162
+
/* SDHCI1 VQMMC */
163
+
regulator-min-microvolts = <1800000>;
164
+
regulator-max-microvolts = <1800000>;
165
+
regulator-allow-set-load;
166
+
/* Broken hardware, never turn it off! */
167
+
regulator-always-on;
168
+
};
169
+
170
+
pm2250_l15: l15 {
171
+
/* WCD/DSI/BT VDDIO */
172
+
regulator-min-microvolts = <1800000>;
173
+
regulator-max-microvolts = <1800000>;
174
+
regulator-allow-set-load;
175
+
regulator-always-on;
176
+
regulator-boot-on;
177
+
};
178
+
179
+
pm2250_l16: l16 {
180
+
/* GPS RF2 */
181
+
regulator-min-microvolts = <1800000>;
182
+
regulator-max-microvolts = <1800000>;
183
+
regulator-boot-on;
184
+
};
185
+
186
+
pm2250_l17: l17 {
187
+
regulator-min-microvolts = <3000000>;
188
+
regulator-max-microvolts = <3000000>;
189
+
};
190
+
191
+
pm2250_l18: l18 {
192
+
/* VDD_PXn */
193
+
regulator-min-microvolts = <1800000>;
194
+
regulator-max-microvolts = <1800000>;
195
+
};
196
+
197
+
pm2250_l19: l19 {
198
+
/* VDD_PXn */
199
+
regulator-min-microvolts = <1800000>;
200
+
regulator-max-microvolts = <1800000>;
201
+
};
202
+
203
+
pm2250_l20: l20 {
204
+
/* SDHCI1 VMMC */
205
+
regulator-min-microvolts = <2856000>;
206
+
regulator-max-microvolts = <2856000>;
207
+
regulator-allow-set-load;
208
+
};
209
+
210
+
pm2250_l21: l21 {
211
+
/* SDHCI2 VMMC */
212
+
regulator-min-microvolts = <2960000>;
213
+
regulator-max-microvolts = <3300000>;
214
+
regulator-allow-set-load;
215
+
regulator-boot-on;
216
+
};
217
+
218
+
pm2250_l22: l22 {
219
+
/* Wi-Fi */
220
+
regulator-min-microvolts = <3312000>;
221
+
regulator-max-microvolts = <3312000>;
222
+
};
223
+
};
224
+
};
225
+
137
226
&sdhc_1 {
227
+
vmmc-supply = <&pm2250_l20>;
228
+
vqmmc-supply = <&pm2250_l14>;
138
229
pinctrl-0 = <&sdc1_state_on>;
139
230
pinctrl-1 = <&sdc1_state_off>;
140
231
pinctrl-names = "default", "sleep";
···
322
61
};
323
62
324
63
&sdhc_2 {
64
+
vmmc-supply = <&pm2250_l21>;
65
+
vqmmc-supply = <&pm2250_l4>;
325
66
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
326
67
pinctrl-0 = <&sdc2_state_on &sd_det_in_on>;
327
68
pinctrl-1 = <&sdc2_state_off &sd_det_in_off>;
···
367
104
};
368
105
369
106
&usb_hsphy {
107
+
vdd-supply = <&pm2250_l12>;
108
+
vdda-pll-supply = <&pm2250_l13>;
109
+
vdda-phy-dpdm-supply = <&pm2250_l21>;
370
110
status = "okay";
371
111
};
372
112
+8
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
+8
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
+10
-5
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+10
-5
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
···
640
640
};
641
641
642
642
&pm8150_adc {
643
-
xo-therm@4c {
643
+
channel@4c {
644
644
reg = <ADC5_XO_THERM_100K_PU>;
645
645
qcom,ratiometric;
646
646
qcom,hw-settle-time = <200>;
647
+
label = "xo_therm";
647
648
};
648
649
649
-
wifi-therm@4e {
650
+
channel@4e {
650
651
reg = <ADC5_AMUX_THM2_100K_PU>;
651
652
qcom,ratiometric;
652
653
qcom,hw-settle-time = <200>;
654
+
label = "wifi_therm";
653
655
};
654
656
};
655
657
···
719
717
};
720
718
721
719
&pm8150b_adc {
722
-
conn-therm@4f {
720
+
channel@4f {
723
721
reg = <ADC5_AMUX_THM3_100K_PU>;
724
722
qcom,ratiometric;
725
723
qcom,hw-settle-time = <200>;
724
+
label = "conn_therm";
726
725
};
727
726
};
728
727
···
755
752
};
756
753
757
754
&pm8150l_adc {
758
-
skin-msm-therm@4e {
755
+
channel@4e {
759
756
reg = <ADC5_AMUX_THM2_100K_PU>;
760
757
qcom,ratiometric;
761
758
qcom,hw-settle-time = <200>;
759
+
label = "skin_msm_therm";
762
760
};
763
761
764
-
pm8150l-therm@4f {
762
+
channel@4f {
765
763
reg = <ADC5_AMUX_THM3_100K_PU>;
766
764
qcom,ratiometric;
767
765
qcom,hw-settle-time = <200>;
766
+
label = "pm8150l_therm";
768
767
};
769
768
};
770
769
+16
arch/arm64/boot/dts/qcom/qru1000-idp.dts
+16
arch/arm64/boot/dts/qcom/qru1000-idp.dts
···
448
448
status = "okay";
449
449
};
450
450
451
+
&reserved_memory {
452
+
ecc_meta_data_mem: ecc-meta-data@f0000000 {
453
+
reg = <0x0 0xf0000000 0x0 0x10000000>;
454
+
no-map;
455
+
};
456
+
457
+
tenx_sp_mem: tenx-sp-buffer@800000000 {
458
+
reg = <0x8 0x0 0x0 0x80000000>;
459
+
no-map;
460
+
};
461
+
};
462
+
463
+
&tlmm {
464
+
gpio-reserved-ranges = <28 2>;
465
+
};
466
+
451
467
&uart7 {
452
468
status = "okay";
453
469
};
+10
-1
arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi
+10
-1
arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi
···
14
14
#address-cells = <1>;
15
15
#size-cells = <0>;
16
16
17
-
rtc@6000 {
17
+
pmm8540a_rtc: rtc@6000 {
18
18
compatible = "qcom,pm8941-rtc";
19
19
reg = <0x6000>, <0x6100>;
20
20
reg-names = "rtc", "alarm";
···
38
38
reg = <0x4 SPMI_USID>;
39
39
#address-cells = <1>;
40
40
#size-cells = <0>;
41
+
42
+
pmm8540c_sdam_2: nvram@b110 {
43
+
compatible = "qcom,spmi-sdam";
44
+
reg = <0xb110>;
45
+
#address-cells = <1>;
46
+
#size-cells = <1>;
47
+
ranges = <0 0xb110 0xb0>;
48
+
status = "disabled";
49
+
};
41
50
42
51
pmm8540c_gpios: gpio@c000 {
43
52
compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
+15
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+15
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
···
407
407
status = "okay";
408
408
};
409
409
410
+
&pmm8540a_rtc {
411
+
nvmem-cells = <&rtc_offset>;
412
+
nvmem-cell-names = "offset";
413
+
414
+
status = "okay";
415
+
};
416
+
417
+
&pmm8540c_sdam_2 {
418
+
status = "okay";
419
+
420
+
rtc_offset: rtc-offset@a0 {
421
+
reg = <0xa0 0x4>;
422
+
};
423
+
};
424
+
410
425
&qup0 {
411
426
status = "okay";
412
427
};
+1
-1
arch/arm64/boot/dts/qcom/sa8540p.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sa8540p.dtsi
+277
-2
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+277
-2
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
···
16
16
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
17
17
18
18
aliases {
19
+
ethernet0 = ðernet0;
20
+
ethernet1 = ðernet1;
21
+
i2c11 = &i2c11;
22
+
i2c18 = &i2c18;
19
23
serial0 = &uart10;
20
24
serial1 = &uart12;
21
25
serial2 = &uart17;
22
-
i2c11 = &i2c11;
23
-
i2c18 = &i2c18;
24
26
spi16 = &spi16;
25
27
ufshc1 = &ufs_mem_hc;
26
28
};
···
263
261
};
264
262
};
265
263
264
+
ðernet0 {
265
+
phy-mode = "sgmii";
266
+
phy-handle = <&sgmii_phy0>;
267
+
268
+
pinctrl-0 = <ðernet0_default>;
269
+
pinctrl-names = "default";
270
+
271
+
snps,mtl-rx-config = <&mtl_rx_setup>;
272
+
snps,mtl-tx-config = <&mtl_tx_setup>;
273
+
snps,ps-speed = <1000>;
274
+
275
+
status = "okay";
276
+
277
+
mdio {
278
+
compatible = "snps,dwmac-mdio";
279
+
#address-cells = <1>;
280
+
#size-cells = <0>;
281
+
282
+
sgmii_phy0: phy@8 {
283
+
compatible = "ethernet-phy-id0141.0dd4";
284
+
reg = <0x8>;
285
+
device_type = "ethernet-phy";
286
+
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
287
+
reset-assert-us = <11000>;
288
+
reset-deassert-us = <70000>;
289
+
};
290
+
291
+
sgmii_phy1: phy@a {
292
+
compatible = "ethernet-phy-id0141.0dd4";
293
+
reg = <0xa>;
294
+
device_type = "ethernet-phy";
295
+
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
296
+
reset-assert-us = <11000>;
297
+
reset-deassert-us = <70000>;
298
+
};
299
+
};
300
+
301
+
mtl_rx_setup: rx-queues-config {
302
+
snps,rx-queues-to-use = <4>;
303
+
snps,rx-sched-sp;
304
+
305
+
queue0 {
306
+
snps,dcb-algorithm;
307
+
snps,map-to-dma-channel = <0x0>;
308
+
snps,route-up;
309
+
snps,priority = <0x1>;
310
+
};
311
+
312
+
queue1 {
313
+
snps,dcb-algorithm;
314
+
snps,map-to-dma-channel = <0x1>;
315
+
snps,route-ptp;
316
+
};
317
+
318
+
queue2 {
319
+
snps,avb-algorithm;
320
+
snps,map-to-dma-channel = <0x2>;
321
+
snps,route-avcp;
322
+
};
323
+
324
+
queue3 {
325
+
snps,avb-algorithm;
326
+
snps,map-to-dma-channel = <0x3>;
327
+
snps,priority = <0xc>;
328
+
};
329
+
};
330
+
331
+
mtl_tx_setup: tx-queues-config {
332
+
snps,tx-queues-to-use = <4>;
333
+
snps,tx-sched-sp;
334
+
335
+
queue0 {
336
+
snps,dcb-algorithm;
337
+
};
338
+
339
+
queue1 {
340
+
snps,dcb-algorithm;
341
+
};
342
+
343
+
queue2 {
344
+
snps,avb-algorithm;
345
+
snps,send_slope = <0x1000>;
346
+
snps,idle_slope = <0x1000>;
347
+
snps,high_credit = <0x3e800>;
348
+
snps,low_credit = <0xffc18000>;
349
+
};
350
+
351
+
queue3 {
352
+
snps,avb-algorithm;
353
+
snps,send_slope = <0x1000>;
354
+
snps,idle_slope = <0x1000>;
355
+
snps,high_credit = <0x3e800>;
356
+
snps,low_credit = <0xffc18000>;
357
+
};
358
+
};
359
+
};
360
+
361
+
ðernet1 {
362
+
phy-mode = "sgmii";
363
+
phy-handle = <&sgmii_phy1>;
364
+
365
+
snps,mtl-rx-config = <&mtl_rx_setup1>;
366
+
snps,mtl-tx-config = <&mtl_tx_setup1>;
367
+
snps,ps-speed = <1000>;
368
+
369
+
status = "okay";
370
+
371
+
mtl_rx_setup1: rx-queues-config {
372
+
snps,rx-queues-to-use = <4>;
373
+
snps,rx-sched-sp;
374
+
375
+
queue0 {
376
+
snps,dcb-algorithm;
377
+
snps,map-to-dma-channel = <0x0>;
378
+
snps,route-up;
379
+
snps,priority = <0x1>;
380
+
};
381
+
382
+
queue1 {
383
+
snps,dcb-algorithm;
384
+
snps,map-to-dma-channel = <0x1>;
385
+
snps,route-ptp;
386
+
};
387
+
388
+
queue2 {
389
+
snps,avb-algorithm;
390
+
snps,map-to-dma-channel = <0x2>;
391
+
snps,route-avcp;
392
+
};
393
+
394
+
queue3 {
395
+
snps,avb-algorithm;
396
+
snps,map-to-dma-channel = <0x3>;
397
+
snps,priority = <0xc>;
398
+
};
399
+
};
400
+
401
+
mtl_tx_setup1: tx-queues-config {
402
+
snps,tx-queues-to-use = <4>;
403
+
snps,tx-sched-sp;
404
+
405
+
queue0 {
406
+
snps,dcb-algorithm;
407
+
};
408
+
409
+
queue1 {
410
+
snps,dcb-algorithm;
411
+
};
412
+
413
+
queue2 {
414
+
snps,avb-algorithm;
415
+
snps,send_slope = <0x1000>;
416
+
snps,idle_slope = <0x1000>;
417
+
snps,high_credit = <0x3e800>;
418
+
snps,low_credit = <0xffc18000>;
419
+
};
420
+
421
+
queue3 {
422
+
snps,avb-algorithm;
423
+
snps,send_slope = <0x1000>;
424
+
snps,idle_slope = <0x1000>;
425
+
snps,high_credit = <0x3e800>;
426
+
snps,low_credit = <0xffc18000>;
427
+
};
428
+
};
429
+
};
430
+
266
431
&i2c11 {
267
432
clock-frequency = <400000>;
268
433
pinctrl-0 = <&qup_i2c11_default>;
···
524
355
status = "okay";
525
356
};
526
357
358
+
&serdes0 {
359
+
phy-supply = <&vreg_l5a>;
360
+
status = "okay";
361
+
};
362
+
363
+
&serdes1 {
364
+
phy-supply = <&vreg_l5a>;
365
+
status = "okay";
366
+
};
367
+
527
368
&sleep_clk {
528
369
clock-frequency = <32764>;
529
370
};
···
545
366
};
546
367
547
368
&tlmm {
369
+
ethernet0_default: ethernet0-default-state {
370
+
ethernet0_mdc: ethernet0-mdc-pins {
371
+
pins = "gpio8";
372
+
function = "emac0_mdc";
373
+
drive-strength = <16>;
374
+
bias-pull-up;
375
+
};
376
+
377
+
ethernet0_mdio: ethernet0-mdio-pins {
378
+
pins = "gpio9";
379
+
function = "emac0_mdio";
380
+
drive-strength = <16>;
381
+
bias-pull-up;
382
+
};
383
+
};
384
+
548
385
qup_uart10_default: qup-uart10-state {
549
386
pins = "gpio46", "gpio47";
550
387
function = "qup1_se3";
···
638
443
bias-pull-down;
639
444
};
640
445
};
446
+
447
+
pcie0_default_state: pcie0-default-state {
448
+
perst-pins {
449
+
pins = "gpio2";
450
+
function = "gpio";
451
+
drive-strength = <2>;
452
+
bias-pull-down;
453
+
};
454
+
455
+
clkreq-pins {
456
+
pins = "gpio1";
457
+
function = "pcie0_clkreq";
458
+
drive-strength = <2>;
459
+
bias-pull-up;
460
+
};
461
+
462
+
wake-pins {
463
+
pins = "gpio0";
464
+
function = "gpio";
465
+
drive-strength = <2>;
466
+
bias-pull-up;
467
+
};
468
+
};
469
+
470
+
pcie1_default_state: pcie1-default-state {
471
+
perst-pins {
472
+
pins = "gpio4";
473
+
function = "gpio";
474
+
drive-strength = <2>;
475
+
bias-pull-down;
476
+
};
477
+
478
+
clkreq-pins {
479
+
pins = "gpio3";
480
+
function = "pcie1_clkreq";
481
+
drive-strength = <2>;
482
+
bias-pull-up;
483
+
};
484
+
485
+
wake-pins {
486
+
pins = "gpio5";
487
+
function = "gpio";
488
+
drive-strength = <2>;
489
+
bias-pull-up;
490
+
};
491
+
};
492
+
};
493
+
494
+
&pcie0 {
495
+
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
496
+
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
497
+
498
+
pinctrl-names = "default";
499
+
pinctrl-0 = <&pcie0_default_state>;
500
+
501
+
status = "okay";
502
+
};
503
+
504
+
&pcie1 {
505
+
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
506
+
wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
507
+
508
+
pinctrl-names = "default";
509
+
pinctrl-0 = <&pcie1_default_state>;
510
+
511
+
status = "okay";
512
+
};
513
+
514
+
&pcie0_phy {
515
+
vdda-phy-supply = <&vreg_l5a>;
516
+
vdda-pll-supply = <&vreg_l1c>;
517
+
518
+
status = "okay";
519
+
};
520
+
521
+
&pcie1_phy {
522
+
vdda-phy-supply = <&vreg_l5a>;
523
+
vdda-pll-supply = <&vreg_l1c>;
524
+
525
+
status = "okay";
641
526
};
642
527
643
528
&uart10 {
+287
-2
arch/arm64/boot/dts/qcom/sa8775p.dtsi
+287
-2
arch/arm64/boot/dts/qcom/sa8775p.dtsi
···
481
481
<0>,
482
482
<0>,
483
483
<0>,
484
-
<0>,
485
-
<0>,
484
+
<&pcie0_phy>,
485
+
<&pcie1_phy>,
486
486
<0>,
487
487
<0>,
488
488
<0>;
···
1837
1837
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1838
1838
};
1839
1839
1840
+
serdes0: phy@8901000 {
1841
+
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
1842
+
reg = <0x0 0x08901000 0x0 0xe10>;
1843
+
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
1844
+
clock-names = "sgmi_ref";
1845
+
#phy-cells = <0>;
1846
+
status = "disabled";
1847
+
};
1848
+
1849
+
serdes1: phy@8902000 {
1850
+
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
1851
+
reg = <0x0 0x08902000 0x0 0xe10>;
1852
+
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
1853
+
clock-names = "sgmi_ref";
1854
+
#phy-cells = <0>;
1855
+
status = "disabled";
1856
+
};
1857
+
1840
1858
pdc: interrupt-controller@b220000 {
1841
1859
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
1842
1860
reg = <0x0 0x0b220000 0x0 0x30000>,
···
1943
1925
interrupt-controller;
1944
1926
#interrupt-cells = <2>;
1945
1927
gpio-ranges = <&tlmm 0 0 149>;
1928
+
wakeup-parent = <&pdc>;
1946
1929
};
1947
1930
1948
1931
apps_smmu: iommu@15000000 {
···
2325
2306
2326
2307
#freq-domain-cells = <1>;
2327
2308
};
2309
+
2310
+
ethernet1: ethernet@23000000 {
2311
+
compatible = "qcom,sa8775p-ethqos";
2312
+
reg = <0x0 0x23000000 0x0 0x10000>,
2313
+
<0x0 0x23016000 0x0 0x100>;
2314
+
reg-names = "stmmaceth", "rgmii";
2315
+
2316
+
interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
2317
+
interrupt-names = "macirq";
2318
+
2319
+
clocks = <&gcc GCC_EMAC1_AXI_CLK>,
2320
+
<&gcc GCC_EMAC1_SLV_AHB_CLK>,
2321
+
<&gcc GCC_EMAC1_PTP_CLK>,
2322
+
<&gcc GCC_EMAC1_PHY_AUX_CLK>;
2323
+
clock-names = "stmmaceth",
2324
+
"pclk",
2325
+
"ptp_ref",
2326
+
"phyaux";
2327
+
2328
+
power-domains = <&gcc EMAC1_GDSC>;
2329
+
2330
+
phys = <&serdes1>;
2331
+
phy-names = "serdes";
2332
+
2333
+
iommus = <&apps_smmu 0x140 0xf>;
2334
+
2335
+
snps,tso;
2336
+
snps,pbl = <32>;
2337
+
rx-fifo-depth = <16384>;
2338
+
tx-fifo-depth = <16384>;
2339
+
2340
+
status = "disabled";
2341
+
};
2342
+
2343
+
ethernet0: ethernet@23040000 {
2344
+
compatible = "qcom,sa8775p-ethqos";
2345
+
reg = <0x0 0x23040000 0x0 0x10000>,
2346
+
<0x0 0x23056000 0x0 0x100>;
2347
+
reg-names = "stmmaceth", "rgmii";
2348
+
2349
+
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
2350
+
interrupt-names = "macirq";
2351
+
2352
+
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
2353
+
<&gcc GCC_EMAC0_SLV_AHB_CLK>,
2354
+
<&gcc GCC_EMAC0_PTP_CLK>,
2355
+
<&gcc GCC_EMAC0_PHY_AUX_CLK>;
2356
+
clock-names = "stmmaceth",
2357
+
"pclk",
2358
+
"ptp_ref",
2359
+
"phyaux";
2360
+
2361
+
power-domains = <&gcc EMAC0_GDSC>;
2362
+
2363
+
phys = <&serdes0>;
2364
+
phy-names = "serdes";
2365
+
2366
+
iommus = <&apps_smmu 0x120 0xf>;
2367
+
2368
+
snps,tso;
2369
+
snps,pbl = <32>;
2370
+
rx-fifo-depth = <16384>;
2371
+
tx-fifo-depth = <16384>;
2372
+
2373
+
status = "disabled";
2374
+
};
2328
2375
};
2329
2376
2330
2377
arch_timer: timer {
···
2399
2314
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2400
2315
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2401
2316
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2317
+
};
2318
+
2319
+
pcie0: pci@1c00000{
2320
+
compatible = "qcom,pcie-sa8775p";
2321
+
reg = <0x0 0x01c00000 0x0 0x3000>,
2322
+
<0x0 0x40000000 0x0 0xf20>,
2323
+
<0x0 0x40000f20 0x0 0xa8>,
2324
+
<0x0 0x40001000 0x0 0x4000>,
2325
+
<0x0 0x40100000 0x0 0x100000>,
2326
+
<0x0 0x01c03000 0x0 0x1000>;
2327
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2328
+
device_type = "pci";
2329
+
2330
+
#address-cells = <3>;
2331
+
#size-cells = <2>;
2332
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2333
+
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2334
+
bus-range = <0x00 0xff>;
2335
+
2336
+
dma-coherent;
2337
+
2338
+
linux,pci-domain = <0>;
2339
+
num-lanes = <2>;
2340
+
2341
+
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2342
+
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2343
+
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2344
+
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2345
+
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2346
+
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2347
+
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2348
+
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2349
+
interrupt-names = "msi0", "msi1", "msi2", "msi3",
2350
+
"msi4", "msi5", "msi6", "msi7";
2351
+
#interrupt-cells = <1>;
2352
+
interrupt-map-mask = <0 0 0 0x7>;
2353
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2354
+
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2355
+
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
2356
+
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
2357
+
2358
+
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2359
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2360
+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2361
+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2362
+
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
2363
+
2364
+
clock-names = "aux",
2365
+
"cfg",
2366
+
"bus_master",
2367
+
"bus_slave",
2368
+
"slave_q2a";
2369
+
2370
+
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
2371
+
assigned-clock-rates = <19200000>;
2372
+
2373
+
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
2374
+
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
2375
+
interconnect-names = "pcie-mem", "cpu-pcie";
2376
+
2377
+
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
2378
+
<0x100 &pcie_smmu 0x0001 0x1>;
2379
+
2380
+
resets = <&gcc GCC_PCIE_0_BCR>;
2381
+
reset-names = "pci";
2382
+
power-domains = <&gcc PCIE_0_GDSC>;
2383
+
2384
+
phys = <&pcie0_phy>;
2385
+
phy-names = "pciephy";
2386
+
2387
+
status = "disabled";
2388
+
};
2389
+
2390
+
pcie0_phy: phy@1c04000 {
2391
+
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
2392
+
reg = <0x0 0x1c04000 0x0 0x2000>;
2393
+
2394
+
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2395
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396
+
<&gcc GCC_PCIE_CLKREF_EN>,
2397
+
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
2398
+
<&gcc GCC_PCIE_0_PIPE_CLK>,
2399
+
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
2400
+
<&gcc GCC_PCIE_0_PHY_AUX_CLK>;
2401
+
2402
+
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
2403
+
"pipediv2", "phy_aux";
2404
+
2405
+
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2406
+
assigned-clock-rates = <100000000>;
2407
+
2408
+
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2409
+
reset-names = "phy";
2410
+
2411
+
#clock-cells = <0>;
2412
+
clock-output-names = "pcie_0_pipe_clk";
2413
+
2414
+
#phy-cells = <0>;
2415
+
2416
+
status = "disabled";
2417
+
};
2418
+
2419
+
pcie1: pci@1c10000{
2420
+
compatible = "qcom,pcie-sa8775p";
2421
+
reg = <0x0 0x01c10000 0x0 0x3000>,
2422
+
<0x0 0x60000000 0x0 0xf20>,
2423
+
<0x0 0x60000f20 0x0 0xa8>,
2424
+
<0x0 0x60001000 0x0 0x4000>,
2425
+
<0x0 0x60100000 0x0 0x100000>,
2426
+
<0x0 0x01c13000 0x0 0x1000>;
2427
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2428
+
device_type = "pci";
2429
+
2430
+
#address-cells = <3>;
2431
+
#size-cells = <2>;
2432
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2433
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
2434
+
bus-range = <0x00 0xff>;
2435
+
2436
+
dma-coherent;
2437
+
2438
+
linux,pci-domain = <1>;
2439
+
num-lanes = <4>;
2440
+
2441
+
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
2442
+
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2443
+
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2444
+
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2445
+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2446
+
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2447
+
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2448
+
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2449
+
interrupt-names = "msi0", "msi1", "msi2", "msi3",
2450
+
"msi4", "msi5", "msi6", "msi7";
2451
+
#interrupt-cells = <1>;
2452
+
interrupt-map-mask = <0 0 0 0x7>;
2453
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2454
+
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2455
+
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2456
+
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2457
+
2458
+
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2459
+
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2460
+
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2461
+
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2462
+
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
2463
+
2464
+
clock-names = "aux",
2465
+
"cfg",
2466
+
"bus_master",
2467
+
"bus_slave",
2468
+
"slave_q2a";
2469
+
2470
+
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2471
+
assigned-clock-rates = <19200000>;
2472
+
2473
+
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
2474
+
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
2475
+
interconnect-names = "pcie-mem", "cpu-pcie";
2476
+
2477
+
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
2478
+
<0x100 &pcie_smmu 0x0081 0x1>;
2479
+
2480
+
resets = <&gcc GCC_PCIE_1_BCR>;
2481
+
reset-names = "pci";
2482
+
power-domains = <&gcc PCIE_1_GDSC>;
2483
+
2484
+
phys = <&pcie1_phy>;
2485
+
phy-names = "pciephy";
2486
+
2487
+
status = "disabled";
2488
+
};
2489
+
2490
+
pcie1_phy: phy@1c14000 {
2491
+
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
2492
+
reg = <0x0 0x1c14000 0x0 0x4000>;
2493
+
2494
+
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2495
+
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2496
+
<&gcc GCC_PCIE_CLKREF_EN>,
2497
+
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2498
+
<&gcc GCC_PCIE_1_PIPE_CLK>,
2499
+
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
2500
+
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
2501
+
2502
+
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
2503
+
"pipediv2", "phy_aux";
2504
+
2505
+
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2506
+
assigned-clock-rates = <100000000>;
2507
+
2508
+
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2509
+
reset-names = "phy";
2510
+
2511
+
#clock-cells = <0>;
2512
+
clock-output-names = "pcie_1_pipe_clk";
2513
+
2514
+
#phy-cells = <0>;
2515
+
2516
+
status = "disabled";
2402
2517
};
2403
2518
};
+4
-2
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+4
-2
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
···
314
314
};
315
315
316
316
&pm6150_adc {
317
-
thermistor@4e {
317
+
channel@4e {
318
318
reg = <ADC5_AMUX_THM2_100K_PU>;
319
319
qcom,ratiometric;
320
320
qcom,hw-settle-time = <200>;
321
+
label = "thermistor";
321
322
};
322
323
323
-
charger-thermistor@4f {
324
+
channel@4f {
324
325
reg = <ADC5_AMUX_THM3_100K_PU>;
325
326
qcom,ratiometric;
326
327
qcom,hw-settle-time = <200>;
328
+
label = "charger_thermistor";
327
329
};
328
330
};
329
331
+107
arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
+107
arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
3
+
/*
4
+
* Devices that use SC7180 with TrustedFirmware-A
5
+
* need PSCI PC mode instead of the OSI mode provided
6
+
* by Qualcomm firmware.
7
+
*/
8
+
9
+
&CPU0 {
10
+
/delete-property/ power-domains;
11
+
/delete-property/ power-domain-names;
12
+
13
+
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
14
+
&LITTLE_CPU_SLEEP_1
15
+
&CLUSTER_SLEEP_0>;
16
+
};
17
+
18
+
&CPU1 {
19
+
/delete-property/ power-domains;
20
+
/delete-property/ power-domain-names;
21
+
22
+
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
23
+
&LITTLE_CPU_SLEEP_1
24
+
&CLUSTER_SLEEP_0>;
25
+
};
26
+
27
+
&CPU2 {
28
+
/delete-property/ power-domains;
29
+
/delete-property/ power-domain-names;
30
+
31
+
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
32
+
&LITTLE_CPU_SLEEP_1
33
+
&CLUSTER_SLEEP_0>;
34
+
};
35
+
36
+
&CPU3 {
37
+
/delete-property/ power-domains;
38
+
/delete-property/ power-domain-names;
39
+
40
+
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
41
+
&LITTLE_CPU_SLEEP_1
42
+
&CLUSTER_SLEEP_0>;
43
+
};
44
+
45
+
&CPU4 {
46
+
/delete-property/ power-domains;
47
+
/delete-property/ power-domain-names;
48
+
49
+
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
50
+
&LITTLE_CPU_SLEEP_1
51
+
&CLUSTER_SLEEP_0>;
52
+
};
53
+
54
+
&CPU5 {
55
+
/delete-property/ power-domains;
56
+
/delete-property/ power-domain-names;
57
+
58
+
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
59
+
&LITTLE_CPU_SLEEP_1
60
+
&CLUSTER_SLEEP_0>;
61
+
};
62
+
63
+
&CPU6 {
64
+
/delete-property/ power-domains;
65
+
/delete-property/ power-domain-names;
66
+
67
+
cpu-idle-states = <&BIG_CPU_SLEEP_0
68
+
&BIG_CPU_SLEEP_1
69
+
&CLUSTER_SLEEP_0>;
70
+
};
71
+
72
+
&CPU7 {
73
+
/delete-property/ power-domains;
74
+
/delete-property/ power-domain-names;
75
+
76
+
cpu-idle-states = <&BIG_CPU_SLEEP_0
77
+
&BIG_CPU_SLEEP_1
78
+
&CLUSTER_SLEEP_0>;
79
+
};
80
+
81
+
/delete-node/ &domain_idle_states;
82
+
83
+
&idle_states {
84
+
CLUSTER_SLEEP_0: cluster-sleep-0 {
85
+
compatible = "arm,idle-state";
86
+
idle-state-name = "cluster-power-down";
87
+
arm,psci-suspend-param = <0x40003444>;
88
+
entry-latency-us = <3263>;
89
+
exit-latency-us = <6562>;
90
+
min-residency-us = <9926>;
91
+
local-timer-stop;
92
+
};
93
+
};
94
+
95
+
/delete-node/ &CPU_PD0;
96
+
/delete-node/ &CPU_PD1;
97
+
/delete-node/ &CPU_PD2;
98
+
/delete-node/ &CPU_PD3;
99
+
/delete-node/ &CPU_PD4;
100
+
/delete-node/ &CPU_PD5;
101
+
/delete-node/ &CPU_PD6;
102
+
/delete-node/ &CPU_PD7;
103
+
/delete-node/ &CLUSTER_PD;
104
+
105
+
&apps_rsc {
106
+
/delete-property/ power-domains;
107
+
};
+1
arch/arm64/boot/dts/qcom/sc7180-idp.dts
+1
arch/arm64/boot/dts/qcom/sc7180-idp.dts
+2
-2
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
+2
-2
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
+2
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
+3
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+3
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
···
13
13
#include <dt-bindings/sound/sc7180-lpass.h>
14
14
15
15
#include "sc7180.dtsi"
16
+
#include "sc7180-firmware-tfa.dtsi"
16
17
/* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */
17
18
#include "pm6150.dtsi"
18
19
#include "pm6150l.dtsi"
···
838
837
};
839
838
840
839
&pm6150_adc {
841
-
charger-thermistor@4f {
840
+
channel@4f {
842
841
reg = <ADC5_AMUX_THM3_100K_PU>;
843
842
qcom,ratiometric;
844
843
qcom,hw-settle-time = <200>;
844
+
label = "charger_therm";
845
845
};
846
846
};
847
847
+184
-32
arch/arm64/boot/dts/qcom/sc7180.dtsi
+184
-32
arch/arm64/boot/dts/qcom/sc7180.dtsi
···
11
11
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12
12
#include <dt-bindings/clock/qcom,rpmh.h>
13
13
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
14
+
#include <dt-bindings/interconnect/qcom,icc.h>
14
15
#include <dt-bindings/interconnect/qcom,osm-l3.h>
15
16
#include <dt-bindings/interconnect/qcom,sc7180.h>
16
17
#include <dt-bindings/interrupt-controller/arm-gic.h>
···
79
78
reg = <0x0 0x0>;
80
79
clocks = <&cpufreq_hw 0>;
81
80
enable-method = "psci";
82
-
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
83
-
&LITTLE_CPU_SLEEP_1
84
-
&CLUSTER_SLEEP_0>;
81
+
power-domains = <&CPU_PD0>;
82
+
power-domain-names = "psci";
85
83
capacity-dmips-mhz = <415>;
86
84
dynamic-power-coefficient = <137>;
87
85
operating-points-v2 = <&cpu0_opp_table>;
···
108
108
reg = <0x0 0x100>;
109
109
clocks = <&cpufreq_hw 0>;
110
110
enable-method = "psci";
111
-
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
112
-
&LITTLE_CPU_SLEEP_1
113
-
&CLUSTER_SLEEP_0>;
111
+
power-domains = <&CPU_PD1>;
112
+
power-domain-names = "psci";
114
113
capacity-dmips-mhz = <415>;
115
114
dynamic-power-coefficient = <137>;
116
115
next-level-cache = <&L2_100>;
···
132
133
reg = <0x0 0x200>;
133
134
clocks = <&cpufreq_hw 0>;
134
135
enable-method = "psci";
135
-
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
136
-
&LITTLE_CPU_SLEEP_1
137
-
&CLUSTER_SLEEP_0>;
136
+
power-domains = <&CPU_PD2>;
137
+
power-domain-names = "psci";
138
138
capacity-dmips-mhz = <415>;
139
139
dynamic-power-coefficient = <137>;
140
140
next-level-cache = <&L2_200>;
···
156
158
reg = <0x0 0x300>;
157
159
clocks = <&cpufreq_hw 0>;
158
160
enable-method = "psci";
159
-
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
160
-
&LITTLE_CPU_SLEEP_1
161
-
&CLUSTER_SLEEP_0>;
161
+
power-domains = <&CPU_PD3>;
162
+
power-domain-names = "psci";
162
163
capacity-dmips-mhz = <415>;
163
164
dynamic-power-coefficient = <137>;
164
165
next-level-cache = <&L2_300>;
···
180
183
reg = <0x0 0x400>;
181
184
clocks = <&cpufreq_hw 0>;
182
185
enable-method = "psci";
183
-
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
184
-
&LITTLE_CPU_SLEEP_1
185
-
&CLUSTER_SLEEP_0>;
186
+
power-domains = <&CPU_PD4>;
187
+
power-domain-names = "psci";
186
188
capacity-dmips-mhz = <415>;
187
189
dynamic-power-coefficient = <137>;
188
190
next-level-cache = <&L2_400>;
···
204
208
reg = <0x0 0x500>;
205
209
clocks = <&cpufreq_hw 0>;
206
210
enable-method = "psci";
207
-
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
208
-
&LITTLE_CPU_SLEEP_1
209
-
&CLUSTER_SLEEP_0>;
211
+
power-domains = <&CPU_PD5>;
212
+
power-domain-names = "psci";
210
213
capacity-dmips-mhz = <415>;
211
214
dynamic-power-coefficient = <137>;
212
215
next-level-cache = <&L2_500>;
···
228
233
reg = <0x0 0x600>;
229
234
clocks = <&cpufreq_hw 1>;
230
235
enable-method = "psci";
231
-
cpu-idle-states = <&BIG_CPU_SLEEP_0
232
-
&BIG_CPU_SLEEP_1
233
-
&CLUSTER_SLEEP_0>;
236
+
power-domains = <&CPU_PD6>;
237
+
power-domain-names = "psci";
234
238
capacity-dmips-mhz = <1024>;
235
239
dynamic-power-coefficient = <480>;
236
240
next-level-cache = <&L2_600>;
···
252
258
reg = <0x0 0x700>;
253
259
clocks = <&cpufreq_hw 1>;
254
260
enable-method = "psci";
255
-
cpu-idle-states = <&BIG_CPU_SLEEP_0
256
-
&BIG_CPU_SLEEP_1
257
-
&CLUSTER_SLEEP_0>;
261
+
power-domains = <&CPU_PD7>;
262
+
power-domain-names = "psci";
258
263
capacity-dmips-mhz = <1024>;
259
264
dynamic-power-coefficient = <480>;
260
265
next-level-cache = <&L2_700>;
···
306
313
};
307
314
};
308
315
309
-
idle-states {
316
+
idle_states: idle-states {
310
317
entry-method = "psci";
311
318
312
319
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
···
348
355
min-residency-us = <5555>;
349
356
local-timer-stop;
350
357
};
358
+
};
351
359
352
-
CLUSTER_SLEEP_0: cluster-sleep-0 {
353
-
compatible = "arm,idle-state";
360
+
domain_idle_states: domain-idle-states {
361
+
CLUSTER_SLEEP_PC: cluster-sleep-0 {
362
+
compatible = "domain-idle-state";
363
+
idle-state-name = "cluster-l3-power-collapse";
364
+
arm,psci-suspend-param = <0x41000044>;
365
+
entry-latency-us = <2752>;
366
+
exit-latency-us = <3048>;
367
+
min-residency-us = <6118>;
368
+
};
369
+
370
+
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
371
+
compatible = "domain-idle-state";
372
+
idle-state-name = "cluster-cx-retention";
373
+
arm,psci-suspend-param = <0x41001244>;
374
+
entry-latency-us = <3638>;
375
+
exit-latency-us = <4562>;
376
+
min-residency-us = <8467>;
377
+
};
378
+
379
+
CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
380
+
compatible = "domain-idle-state";
354
381
idle-state-name = "cluster-power-down";
355
-
arm,psci-suspend-param = <0x40003444>;
382
+
arm,psci-suspend-param = <0x4100b244>;
356
383
entry-latency-us = <3263>;
357
384
exit-latency-us = <6562>;
358
-
min-residency-us = <9926>;
359
-
local-timer-stop;
385
+
min-residency-us = <9826>;
360
386
};
361
387
};
362
388
};
···
578
566
psci {
579
567
compatible = "arm,psci-1.0";
580
568
method = "smc";
569
+
570
+
CPU_PD0: cpu0 {
571
+
#power-domain-cells = <0>;
572
+
power-domains = <&CLUSTER_PD>;
573
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
574
+
};
575
+
576
+
CPU_PD1: cpu1 {
577
+
#power-domain-cells = <0>;
578
+
power-domains = <&CLUSTER_PD>;
579
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
580
+
};
581
+
582
+
CPU_PD2: cpu2 {
583
+
#power-domain-cells = <0>;
584
+
power-domains = <&CLUSTER_PD>;
585
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
586
+
};
587
+
588
+
CPU_PD3: cpu3 {
589
+
#power-domain-cells = <0>;
590
+
power-domains = <&CLUSTER_PD>;
591
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
592
+
};
593
+
594
+
CPU_PD4: cpu4 {
595
+
#power-domain-cells = <0>;
596
+
power-domains = <&CLUSTER_PD>;
597
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
598
+
};
599
+
600
+
CPU_PD5: cpu5 {
601
+
#power-domain-cells = <0>;
602
+
power-domains = <&CLUSTER_PD>;
603
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
604
+
};
605
+
606
+
CPU_PD6: cpu6 {
607
+
#power-domain-cells = <0>;
608
+
power-domains = <&CLUSTER_PD>;
609
+
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
610
+
};
611
+
612
+
CPU_PD7: cpu7 {
613
+
#power-domain-cells = <0>;
614
+
power-domains = <&CLUSTER_PD>;
615
+
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
616
+
};
617
+
618
+
CLUSTER_PD: cpu-cluster0 {
619
+
#power-domain-cells = <0>;
620
+
domain-idle-states = <&CLUSTER_SLEEP_PC
621
+
&CLUSTER_SLEEP_CX_RET
622
+
&CLUSTER_AOSS_SLEEP>;
623
+
};
581
624
};
582
625
583
626
reserved_memory: reserved-memory {
···
2840
2773
};
2841
2774
};
2842
2775
2776
+
pmu@90b6300 {
2777
+
compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2778
+
reg = <0 0x090b6300 0 0x600>;
2779
+
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2780
+
2781
+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2782
+
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
2783
+
operating-points-v2 = <&cpu_bwmon_opp_table>;
2784
+
2785
+
cpu_bwmon_opp_table: opp-table {
2786
+
compatible = "operating-points-v2";
2787
+
2788
+
opp-0 {
2789
+
opp-peak-kBps = <2288000>;
2790
+
};
2791
+
2792
+
opp-1 {
2793
+
opp-peak-kBps = <4577000>;
2794
+
};
2795
+
2796
+
opp-2 {
2797
+
opp-peak-kBps = <7110000>;
2798
+
};
2799
+
2800
+
opp-3 {
2801
+
opp-peak-kBps = <9155000>;
2802
+
};
2803
+
2804
+
opp-4 {
2805
+
opp-peak-kBps = <12298000>;
2806
+
};
2807
+
2808
+
opp-5 {
2809
+
opp-peak-kBps = <14236000>;
2810
+
};
2811
+
};
2812
+
};
2813
+
2814
+
pmu@90cd000 {
2815
+
compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2816
+
reg = <0 0x090cd000 0 0x1000>;
2817
+
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
2818
+
2819
+
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
2820
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
2821
+
operating-points-v2 = <&llcc_bwmon_opp_table>;
2822
+
2823
+
llcc_bwmon_opp_table: opp-table {
2824
+
compatible = "operating-points-v2";
2825
+
2826
+
opp-0 {
2827
+
opp-peak-kBps = <1144000>;
2828
+
};
2829
+
2830
+
opp-1 {
2831
+
opp-peak-kBps = <1720000>;
2832
+
};
2833
+
2834
+
opp-2 {
2835
+
opp-peak-kBps = <2086000>;
2836
+
};
2837
+
2838
+
opp-3 {
2839
+
opp-peak-kBps = <2929000>;
2840
+
};
2841
+
2842
+
opp-4 {
2843
+
opp-peak-kBps = <3879000>;
2844
+
};
2845
+
2846
+
opp-5 {
2847
+
opp-peak-kBps = <5931000>;
2848
+
};
2849
+
2850
+
opp-6 {
2851
+
opp-peak-kBps = <6881000>;
2852
+
};
2853
+
2854
+
opp-7 {
2855
+
opp-peak-kBps = <8137000>;
2856
+
};
2857
+
};
2858
+
};
2859
+
2843
2860
dc_noc: interconnect@9160000 {
2844
2861
compatible = "qcom,sc7180-dc-noc";
2845
2862
reg = <0 0x09160000 0 0x03200>;
···
3271
3120
reg = <0 0x0ae94400 0 0x200>,
3272
3121
<0 0x0ae94600 0 0x280>,
3273
3122
<0 0x0ae94a00 0 0x1e0>;
3274
-
reg-names = "dsi0_phy",
3275
-
"dsi0_phy_lane",
3123
+
reg-names = "dsi_phy",
3124
+
"dsi_phy_lane",
3276
3125
"dsi_pll";
3277
3126
3278
3127
#clock-cells = <1>;
···
3663
3512
<SLEEP_TCS 3>,
3664
3513
<WAKE_TCS 3>,
3665
3514
<CONTROL_TCS 1>;
3515
+
power-domains = <&CLUSTER_PD>;
3666
3516
3667
3517
rpmhcc: clock-controller {
3668
3518
compatible = "qcom,sc7180-rpmh-clk";
+1
-1
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280-idp.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7280-idp.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
···
383
383
};
384
384
385
385
&pmk8350_vadc {
386
-
pmk8350-die-temp@3 {
386
+
channel@3 {
387
387
reg = <PMK8350_ADC7_DIE_TEMP>;
388
388
label = "pmk8350_die_temp";
389
389
qcom,pre-scaling = <1 1>;
390
390
};
391
391
392
-
pmr735a-die-temp@403 {
392
+
channel@403 {
393
393
reg = <PMR735A_ADC7_DIE_TEMP>;
394
394
label = "pmr735a_die_temp";
395
395
qcom,pre-scaling = <1 1>;
+1
-1
arch/arm64/boot/dts/qcom/sc7280.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280.dtsi
+200
-9
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+200
-9
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
···
36
36
pinctrl-0 = <&hall_int_active_state>;
37
37
pinctrl-names = "default";
38
38
39
-
lid {
39
+
lid-switch {
40
40
gpios = <&tlmm 121 GPIO_ACTIVE_LOW>;
41
41
linux,input-type = <EV_SW>;
42
42
linux,code = <SW_LID>;
43
43
wakeup-source;
44
44
wakeup-event-action = <EV_ACT_DEASSERTED>;
45
+
};
46
+
};
47
+
48
+
pmic-glink {
49
+
compatible = "qcom,sc8180x-pmic-glink", "qcom,pmic-glink";
50
+
51
+
#address-cells = <1>;
52
+
#size-cells = <0>;
53
+
54
+
connector@0 {
55
+
compatible = "usb-c-connector";
56
+
reg = <0>;
57
+
power-role = "dual";
58
+
data-role = "dual";
59
+
60
+
ports {
61
+
#address-cells = <1>;
62
+
#size-cells = <0>;
63
+
64
+
port@0 {
65
+
reg = <0>;
66
+
67
+
pmic_glink_con0_hs: endpoint {
68
+
remote-endpoint = <&usb_prim_role_switch>;
69
+
};
70
+
};
71
+
72
+
port@1 {
73
+
reg = <1>;
74
+
75
+
pmic_glink_con0_ss: endpoint {
76
+
remote-endpoint = <&usb_prim_qmpphy_out>;
77
+
};
78
+
};
79
+
80
+
port@2 {
81
+
reg = <2>;
82
+
83
+
pmic_glink_con0_sbu: endpoint {
84
+
remote-endpoint = <&usbprim_sbu_mux>;
85
+
};
86
+
};
87
+
};
88
+
};
89
+
90
+
connector@1 {
91
+
compatible = "usb-c-connector";
92
+
reg = <1>;
93
+
power-role = "dual";
94
+
data-role = "dual";
95
+
96
+
ports {
97
+
#address-cells = <1>;
98
+
#size-cells = <0>;
99
+
port@0 {
100
+
reg = <0>;
101
+
102
+
pmic_glink_con1_hs: endpoint {
103
+
remote-endpoint = <&usb_sec_role_switch>;
104
+
};
105
+
};
106
+
107
+
port@1 {
108
+
reg = <1>;
109
+
110
+
pmic_glink_con1_ss: endpoint {
111
+
remote-endpoint = <&usb_sec_qmpphy_out>;
112
+
};
113
+
};
114
+
115
+
port@2 {
116
+
reg = <2>;
117
+
118
+
pmic_glink_con1_sbu: endpoint {
119
+
remote-endpoint = <&usbsec_sbu_mux>;
120
+
};
121
+
};
122
+
};
45
123
};
46
124
};
47
125
···
177
99
regulator-boot-on;
178
100
179
101
vin-supply = <&vph_pwr>;
102
+
};
103
+
104
+
usbprim-sbu-mux {
105
+
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
106
+
107
+
enable-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
108
+
select-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
109
+
110
+
pinctrl-names = "default";
111
+
pinctrl-0 = <&usbprim_sbu_default>;
112
+
113
+
mode-switch;
114
+
orientation-switch;
115
+
116
+
port {
117
+
usbprim_sbu_mux: endpoint {
118
+
remote-endpoint = <&pmic_glink_con0_sbu>;
119
+
};
120
+
};
121
+
};
122
+
123
+
usbsec-sbu-mux {
124
+
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
125
+
126
+
enable-gpios = <&tlmm 188 GPIO_ACTIVE_LOW>;
127
+
select-gpios = <&tlmm 187 GPIO_ACTIVE_HIGH>;
128
+
129
+
pinctrl-names = "default";
130
+
pinctrl-0 = <&usbsec_sbu_default>;
131
+
132
+
mode-switch;
133
+
orientation-switch;
134
+
135
+
port {
136
+
usbsec_sbu_mux: endpoint {
137
+
remote-endpoint = <&pmic_glink_con1_sbu>;
138
+
};
139
+
};
180
140
};
181
141
};
182
142
···
399
283
status = "okay";
400
284
};
401
285
286
+
&mdss_dp0 {
287
+
status = "okay";
288
+
};
289
+
290
+
&mdss_dp0_out {
291
+
data-lanes = <0 1>;
292
+
remote-endpoint = <&usb_prim_qmpphy_dp_in>;
293
+
};
294
+
295
+
&mdss_dp1 {
296
+
status = "okay";
297
+
};
298
+
299
+
&mdss_dp1_out {
300
+
data-lanes = <0 1>;
301
+
remote-endpoint = <&usb_sec_qmpphy_dp_in>;
302
+
};
303
+
402
304
&mdss_edp {
403
305
data-lanes = <0 1 2 3>;
404
306
···
432
298
433
299
backlight = <&backlight>;
434
300
435
-
ports {
436
-
port {
437
-
auo_b140han06_in: endpoint {
438
-
remote-endpoint = <&mdss_edp_out>;
439
-
};
301
+
port {
302
+
auo_b140han06_in: endpoint {
303
+
remote-endpoint = <&mdss_edp_out>;
440
304
};
441
305
};
442
306
};
···
551
419
vdda-phy-supply = <&vreg_l3c_1p2>;
552
420
vdda-pll-supply = <&vreg_l5e_0p88>;
553
421
422
+
orientation-switch;
423
+
554
424
status = "okay";
555
425
};
556
426
···
562
428
563
429
&usb_prim_dwc3 {
564
430
dr_mode = "host";
431
+
};
432
+
433
+
&usb_prim_qmpphy_dp_in {
434
+
remote-endpoint = <&mdss_dp0_out>;
435
+
};
436
+
437
+
&usb_prim_qmpphy_out {
438
+
remote-endpoint = <&pmic_glink_con0_ss>;
439
+
};
440
+
441
+
&usb_prim_role_switch {
442
+
remote-endpoint = <&pmic_glink_con0_hs>;
565
443
};
566
444
567
445
&usb_sec_hsphy {
···
588
442
vdda-phy-supply = <&vreg_l3c_1p2>;
589
443
vdda-pll-supply = <&vreg_l5e_0p88>;
590
444
445
+
orientation-switch;
446
+
591
447
status = "okay";
448
+
};
449
+
450
+
&usb_sec_qmpphy_dp_in {
451
+
remote-endpoint = <&mdss_dp1_out>;
452
+
};
453
+
454
+
&usb_sec_qmpphy_out {
455
+
remote-endpoint = <&pmic_glink_con1_ss>;
456
+
};
457
+
458
+
&usb_sec_role_switch {
459
+
remote-endpoint = <&pmic_glink_con1_hs>;
592
460
};
593
461
594
462
&usb_sec {
···
657
497
pins = "gpio121";
658
498
function = "gpio";
659
499
660
-
input-enable;
661
500
bias-disable;
662
501
};
663
502
···
672
513
pins = "gpio122";
673
514
function = "gpio";
674
515
675
-
input-enable;
676
516
bias-pull-up;
677
517
drive-strength = <2>;
678
518
};
···
688
530
pins = "gpio37", "gpio24";
689
531
function = "gpio";
690
532
691
-
input-enable;
692
533
bias-pull-up;
693
534
drive-strength = <2>;
694
535
};
···
714
557
715
558
drive-strength = <2>;
716
559
bias-pull-up;
560
+
};
561
+
};
562
+
563
+
usbprim_sbu_default: usbprim-sbu-state {
564
+
oe-n-pins {
565
+
pins = "gpio152";
566
+
function = "gpio";
567
+
bias-disable;
568
+
drive-strength = <16>;
569
+
output-high;
570
+
};
571
+
572
+
sel-pins {
573
+
pins = "gpio100";
574
+
function = "gpio";
575
+
bias-disable;
576
+
drive-strength = <16>;
577
+
};
578
+
};
579
+
580
+
usbsec_sbu_default: usbsec-sbu-state {
581
+
oe-n-pins {
582
+
pins = "gpio188";
583
+
function = "gpio";
584
+
bias-disable;
585
+
drive-strength = <16>;
586
+
output-high;
587
+
};
588
+
589
+
sel-pins {
590
+
pins = "gpio187";
591
+
function = "gpio";
592
+
bias-disable;
593
+
drive-strength = <16>;
717
594
};
718
595
};
719
596
+19
-17
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
+19
-17
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
···
74
74
#address-cells = <1>;
75
75
#size-cells = <0>;
76
76
77
-
pon: power-on@800 {
77
+
pon: pon@800 {
78
78
compatible = "qcom,pm8916-pon";
79
79
reg = <0x0800>;
80
80
pwrkey {
···
105
105
#io-channel-cells = <1>;
106
106
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
107
107
108
-
ref-gnd@0 {
108
+
channel@0 {
109
109
reg = <ADC5_REF_GND>;
110
110
qcom,pre-scaling = <1 1>;
111
111
label = "ref_gnd";
112
112
};
113
113
114
-
vref-1p25@1 {
114
+
channel@1 {
115
115
reg = <ADC5_1P25VREF>;
116
116
qcom,pre-scaling = <1 1>;
117
117
label = "vref_1p25";
118
118
};
119
119
120
-
die-temp@6 {
120
+
channel@6 {
121
121
reg = <ADC5_DIE_TEMP>;
122
122
qcom,pre-scaling = <1 1>;
123
123
label = "die_temp";
···
142
142
};
143
143
144
144
pmc8180_gpios: gpio@c000 {
145
-
compatible = "qcom,pmc8180-gpio";
145
+
compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio";
146
146
reg = <0xc000>;
147
147
gpio-controller;
148
+
gpio-ranges = <&pmc8180_gpios 0 0 10>;
148
149
#gpio-cells = <2>;
149
150
interrupt-controller;
150
151
#interrupt-cells = <2>;
···
173
172
#io-channel-cells = <1>;
174
173
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
175
174
176
-
ref-gnd@0 {
175
+
channel@0 {
177
176
reg = <ADC5_REF_GND>;
178
177
qcom,pre-scaling = <1 1>;
179
178
label = "ref_gnd";
180
179
};
181
180
182
-
vref-1p25@1 {
181
+
channel@1 {
183
182
reg = <ADC5_1P25VREF>;
184
183
qcom,pre-scaling = <1 1>;
185
184
label = "vref_1p25";
186
185
};
187
186
188
-
vcoin@85 {
187
+
channel@85 {
189
188
reg = <0x85>;
190
189
qcom,pre-scaling = <1 1>;
191
190
label = "vcoin2";
···
221
220
#io-channel-cells = <1>;
222
221
interrupts = <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
223
222
224
-
ref-gnd@0 {
223
+
channel@0 {
225
224
reg = <ADC5_REF_GND>;
226
225
qcom,pre-scaling = <1 1>;
227
226
label = "ref_gnd";
228
227
};
229
228
230
-
vref-1p25@1 {
229
+
channel@1 {
231
230
reg = <ADC5_1P25VREF>;
232
231
qcom,pre-scaling = <1 1>;
233
232
label = "vref_1p25";
234
233
};
235
234
236
-
vcoin@85 {
235
+
channel@85 {
237
236
reg = <0x85>;
238
237
qcom,pre-scaling = <1 1>;
239
238
label = "vcoin";
···
247
246
#address-cells = <1>;
248
247
#size-cells = <0>;
249
248
250
-
power-on@800 {
249
+
pon@800 {
251
250
compatible = "qcom,pm8916-pon";
252
251
reg = <0x0800>;
253
252
···
271
270
#io-channel-cells = <1>;
272
271
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
273
272
274
-
ref-gnd@0 {
273
+
channel@0 {
275
274
reg = <ADC5_REF_GND>;
276
275
qcom,pre-scaling = <1 1>;
277
276
label = "ref_gnd";
278
277
};
279
278
280
-
vref-1p25@1 {
279
+
channel@1 {
281
280
reg = <ADC5_1P25VREF>;
282
281
qcom,pre-scaling = <1 1>;
283
282
label = "vref_1p25";
284
283
};
285
284
286
-
die-temp@6 {
285
+
channel@6 {
287
286
reg = <ADC5_DIE_TEMP>;
288
287
qcom,pre-scaling = <1 1>;
289
288
label = "die_temp";
···
301
300
};
302
301
303
302
pmc8180c_gpios: gpio@c000 {
304
-
compatible = "qcom,pmc8180c-gpio";
303
+
compatible = "qcom,pmc8180c-gpio", "qcom,spmi-gpio";
305
304
reg = <0xc000>;
306
305
gpio-controller;
306
+
gpio-ranges = <&pmc8180c_gpios 0 0 12>;
307
307
#gpio-cells = <2>;
308
308
interrupt-controller;
309
309
#interrupt-cells = <2>;
···
315
313
compatible = "qcom,pmc8180c", "qcom,spmi-pmic";
316
314
reg = <0x5 SPMI_USID>;
317
315
318
-
pmc8180c_lpg: lpg {
316
+
pmc8180c_lpg: pwm {
319
317
compatible = "qcom,pmc8180c-lpg";
320
318
321
319
#address-cells = <1>;
+199
-10
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+199
-10
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
···
50
50
};
51
51
};
52
52
53
+
pmic-glink {
54
+
compatible = "qcom,sc8180x-pmic-glink", "qcom,pmic-glink";
55
+
56
+
#address-cells = <1>;
57
+
#size-cells = <0>;
58
+
59
+
connector@0 {
60
+
compatible = "usb-c-connector";
61
+
reg = <0>;
62
+
power-role = "dual";
63
+
data-role = "dual";
64
+
65
+
ports {
66
+
#address-cells = <1>;
67
+
#size-cells = <0>;
68
+
69
+
port@0 {
70
+
reg = <0>;
71
+
72
+
pmic_glink_con0_hs: endpoint {
73
+
remote-endpoint = <&usb_prim_role_switch>;
74
+
};
75
+
};
76
+
77
+
port@1 {
78
+
reg = <1>;
79
+
80
+
pmic_glink_con0_ss: endpoint {
81
+
remote-endpoint = <&usb_prim_qmpphy_out>;
82
+
};
83
+
};
84
+
85
+
port@2 {
86
+
reg = <2>;
87
+
88
+
pmic_glink_con0_sbu: endpoint {
89
+
remote-endpoint = <&usbprim_sbu_mux>;
90
+
};
91
+
};
92
+
};
93
+
};
94
+
95
+
connector@1 {
96
+
compatible = "usb-c-connector";
97
+
reg = <1>;
98
+
power-role = "dual";
99
+
data-role = "dual";
100
+
101
+
ports {
102
+
#address-cells = <1>;
103
+
#size-cells = <0>;
104
+
port@0 {
105
+
reg = <0>;
106
+
107
+
pmic_glink_con1_hs: endpoint {
108
+
remote-endpoint = <&usb_sec_role_switch>;
109
+
};
110
+
};
111
+
112
+
port@1 {
113
+
reg = <1>;
114
+
115
+
pmic_glink_con1_ss: endpoint {
116
+
remote-endpoint = <&usb_sec_qmpphy_out>;
117
+
};
118
+
};
119
+
120
+
port@2 {
121
+
reg = <2>;
122
+
123
+
pmic_glink_con1_sbu: endpoint {
124
+
remote-endpoint = <&usbsec_sbu_mux>;
125
+
};
126
+
};
127
+
};
128
+
};
129
+
};
130
+
53
131
reserved-memory {
54
132
rmtfs_mem: rmtfs-region@85500000 {
55
133
compatible = "qcom,rmtfs-mem";
···
220
142
regulator-boot-on;
221
143
222
144
vin-supply = <&vph_pwr>;
145
+
};
146
+
147
+
usbprim-sbu-mux {
148
+
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
149
+
150
+
enable-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
151
+
select-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
152
+
153
+
pinctrl-names = "default";
154
+
pinctrl-0 = <&usbprim_sbu_default>;
155
+
156
+
mode-switch;
157
+
orientation-switch;
158
+
159
+
port {
160
+
usbprim_sbu_mux: endpoint {
161
+
remote-endpoint = <&pmic_glink_con0_sbu>;
162
+
};
163
+
};
164
+
};
165
+
166
+
usbsec-sbu-mux {
167
+
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
168
+
169
+
enable-gpios = <&tlmm 188 GPIO_ACTIVE_LOW>;
170
+
select-gpios = <&tlmm 187 GPIO_ACTIVE_HIGH>;
171
+
172
+
pinctrl-names = "default";
173
+
pinctrl-0 = <&usbsec_sbu_default>;
174
+
175
+
mode-switch;
176
+
orientation-switch;
177
+
178
+
port {
179
+
usbsec_sbu_mux: endpoint {
180
+
remote-endpoint = <&pmic_glink_con1_sbu>;
181
+
};
182
+
};
223
183
};
224
184
};
225
185
···
479
363
status = "okay";
480
364
};
481
365
366
+
&mdss_dp0 {
367
+
status = "okay";
368
+
};
369
+
370
+
&mdss_dp0_out {
371
+
data-lanes = <0 1>;
372
+
remote-endpoint = <&usb_prim_qmpphy_dp_in>;
373
+
};
374
+
375
+
&mdss_dp1 {
376
+
status = "okay";
377
+
};
378
+
379
+
&mdss_dp1_out {
380
+
data-lanes = <0 1>;
381
+
remote-endpoint = <&usb_sec_qmpphy_dp_in>;
382
+
};
383
+
482
384
&mdss_edp {
483
385
data-lanes = <0 1 2 3>;
484
386
···
511
377
512
378
backlight = <&backlight>;
513
379
514
-
ports {
515
-
port {
516
-
auo_b133han05_in: endpoint {
517
-
remote-endpoint = <&mdss_edp_out>;
518
-
};
380
+
port {
381
+
auo_b133han05_in: endpoint {
382
+
remote-endpoint = <&mdss_edp_out>;
519
383
};
520
384
};
521
385
};
···
628
496
vdda-phy-supply = <&vreg_l3c_1p2>;
629
497
vdda-pll-supply = <&vreg_l5e_0p88>;
630
498
499
+
orientation-switch;
500
+
631
501
status = "okay";
632
502
};
633
503
···
639
505
640
506
&usb_prim_dwc3 {
641
507
dr_mode = "host";
508
+
};
509
+
510
+
&usb_prim_qmpphy_dp_in {
511
+
remote-endpoint = <&mdss_dp0_out>;
512
+
};
513
+
514
+
&usb_prim_qmpphy_out {
515
+
remote-endpoint = <&pmic_glink_con0_ss>;
516
+
};
517
+
518
+
&usb_prim_role_switch {
519
+
remote-endpoint = <&pmic_glink_con0_hs>;
642
520
};
643
521
644
522
&usb_sec_hsphy {
···
665
519
vdda-phy-supply = <&vreg_l3c_1p2>;
666
520
vdda-pll-supply = <&vreg_l5e_0p88>;
667
521
522
+
orientation-switch;
523
+
668
524
status = "okay";
525
+
};
526
+
527
+
&usb_sec_qmpphy_dp_in {
528
+
remote-endpoint = <&mdss_dp1_out>;
529
+
};
530
+
531
+
&usb_sec_qmpphy_out {
532
+
remote-endpoint = <&pmic_glink_con1_ss>;
533
+
};
534
+
535
+
&usb_sec_role_switch {
536
+
remote-endpoint = <&pmic_glink_con1_hs>;
669
537
};
670
538
671
539
&usb_sec {
···
742
582
pins = "gpio121";
743
583
function = "gpio";
744
584
745
-
input-enable;
746
585
bias-disable;
747
586
};
748
587
···
751
592
function = "gpio";
752
593
753
594
bias-pull-up;
754
-
intput-enable;
755
595
};
756
596
757
597
kp-disable-pins {
···
793
635
};
794
636
};
795
637
638
+
usbprim_sbu_default: usbprim-sbu-state {
639
+
oe-n-pins {
640
+
pins = "gpio152";
641
+
function = "gpio";
642
+
bias-disable;
643
+
drive-strength = <16>;
644
+
output-high;
645
+
};
646
+
647
+
sel-pins {
648
+
pins = "gpio100";
649
+
function = "gpio";
650
+
bias-disable;
651
+
drive-strength = <16>;
652
+
};
653
+
};
654
+
655
+
usbsec_sbu_default: usbsec-sbu-state {
656
+
oe-n-pins {
657
+
pins = "gpio188";
658
+
function = "gpio";
659
+
bias-disable;
660
+
drive-strength = <16>;
661
+
output-high;
662
+
};
663
+
664
+
sel-pins {
665
+
pins = "gpio187";
666
+
function = "gpio";
667
+
bias-disable;
668
+
drive-strength = <16>;
669
+
};
670
+
};
671
+
796
672
tp_int_active_state: tp-int-active-state {
797
673
tp-int-pins {
798
674
pins = "gpio24";
799
675
function = "gpio";
800
676
801
677
bias-disable;
802
-
input-enable;
803
678
};
804
679
805
680
tp-close-n-pins {
···
840
649
function = "gpio";
841
650
842
651
bias-disable;
843
-
input-enable;
844
652
};
845
653
};
846
654
···
848
658
pins = "gpio122";
849
659
function = "gpio";
850
660
851
-
input-enable;
852
661
bias-disable;
853
662
};
854
663
+59
-7
arch/arm64/boot/dts/qcom/sc8180x.dtsi
+59
-7
arch/arm64/boot/dts/qcom/sc8180x.dtsi
···
64
64
L3_0: l3-cache {
65
65
compatible = "cache";
66
66
cache-level = <3>;
67
+
cache-unified;
67
68
};
68
69
};
69
70
};
···
299
298
domain-idle-states {
300
299
CLUSTER_SLEEP_0: cluster-sleep-0 {
301
300
compatible = "domain-idle-state";
302
-
arm,psci-suspend-param = <0x4100c244>;
301
+
arm,psci-suspend-param = <0x4100a344>;
303
302
entry-latency-us = <3263>;
304
303
exit-latency-us = <6562>;
305
304
min-residency-us = <9987>;
···
2253
2252
};
2254
2253
2255
2254
gmu: gmu@2c6a000 {
2256
-
compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2255
+
compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2257
2256
2258
2257
reg = <0 0x02c6a000 0 0x30000>,
2259
2258
<0 0x0b290000 0 0x10000>,
···
2465
2464
2466
2465
status = "disabled";
2467
2466
2467
+
ports {
2468
+
#address-cells = <1>;
2469
+
#size-cells = <0>;
2470
+
2471
+
port@0 {
2472
+
reg = <0>;
2473
+
2474
+
usb_prim_qmpphy_out: endpoint {};
2475
+
};
2476
+
2477
+
port@2 {
2478
+
reg = <2>;
2479
+
2480
+
usb_prim_qmpphy_dp_in: endpoint {};
2481
+
};
2482
+
};
2483
+
2468
2484
usb_prim_ssphy: usb3-phy@88e9200 {
2469
2485
reg = <0 0x088e9200 0 0x200>,
2470
2486
<0 0x088e9400 0 0x200>,
···
2531
2513
2532
2514
status = "disabled";
2533
2515
2516
+
ports {
2517
+
#address-cells = <1>;
2518
+
#size-cells = <0>;
2519
+
2520
+
port@0 {
2521
+
reg = <0>;
2522
+
2523
+
usb_sec_qmpphy_out: endpoint {};
2524
+
};
2525
+
2526
+
port@2 {
2527
+
reg = <2>;
2528
+
2529
+
usb_sec_qmpphy_dp_in: endpoint {};
2530
+
};
2531
+
};
2532
+
2534
2533
usb_sec_ssphy: usb3-phy@88e9200 {
2535
2534
reg = <0 0x088ee200 0 0x200>,
2536
2535
<0 0x088ee400 0 0x200>,
···
2576
2541
2577
2542
system-cache-controller@9200000 {
2578
2543
compatible = "qcom,sc8180x-llcc";
2579
-
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2580
-
reg-names = "llcc_base", "llcc_broadcast_base";
2544
+
reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
2545
+
<0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
2546
+
<0 0x09600000 0 0x50000>;
2547
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2548
+
"llcc3_base", "llcc_broadcast_base";
2581
2549
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2582
2550
};
2583
2551
···
2642
2604
snps,dis_enblslpm_quirk;
2643
2605
phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
2644
2606
phy-names = "usb2-phy", "usb3-phy";
2607
+
2608
+
port {
2609
+
usb_prim_role_switch: endpoint {
2610
+
};
2611
+
};
2645
2612
};
2646
2613
};
2647
2614
···
2699
2656
snps,dis_enblslpm_quirk;
2700
2657
phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
2701
2658
phy-names = "usb2-phy", "usb3-phy";
2659
+
2660
+
port {
2661
+
usb_sec_role_switch: endpoint {
2662
+
};
2663
+
};
2702
2664
};
2703
2665
};
2704
2666
···
3031
2983
3032
2984
port@1 {
3033
2985
reg = <1>;
2986
+
mdss_dp0_out: endpoint {
2987
+
};
3034
2988
};
3035
2989
};
3036
2990
···
3107
3057
3108
3058
port@1 {
3109
3059
reg = <1>;
3060
+
mdss_dp1_out: endpoint {
3061
+
};
3110
3062
};
3111
3063
};
3112
3064
···
3481
3429
#size-cells = <1>;
3482
3430
ranges = <0 0 0 0x20000000>;
3483
3431
3484
-
frame@17c21000{
3432
+
frame@17c21000 {
3485
3433
reg = <0x17c21000 0x1000>,
3486
3434
<0x17c22000 0x1000>;
3487
3435
frame-number = <0>;
···
3908
3856
};
3909
3857
};
3910
3858
3911
-
gpu-thermal-top {
3859
+
gpu-top-thermal {
3912
3860
polling-delay-passive = <250>;
3913
3861
polling-delay = <1000>;
3914
3862
···
4058
4006
};
4059
4007
};
4060
4008
4061
-
gpu-thermal-bottom {
4009
+
gpu-bottom-thermal {
4062
4010
polling-delay-passive = <250>;
4063
4011
polling-delay = <1000>;
4064
4012
+7
-9
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+7
-9
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
···
133
133
vreg_edp_bl: regulator-edp-bl {
134
134
compatible = "regulator-fixed";
135
135
136
-
regulator-name = "VBL9";
136
+
regulator-name = "VREG_EDP_BL";
137
137
regulator-min-microvolt = <3600000>;
138
138
regulator-max-microvolt = <3600000>;
139
139
···
149
149
vreg_nvme: regulator-nvme {
150
150
compatible = "regulator-fixed";
151
151
152
-
regulator-name = "VCC3_SSD";
152
+
regulator-name = "VREG_NVME_3P3";
153
153
regulator-min-microvolt = <3300000>;
154
154
regulator-max-microvolt = <3300000>;
155
155
···
163
163
vreg_misc_3p3: regulator-misc-3p3 {
164
164
compatible = "regulator-fixed";
165
165
166
-
regulator-name = "VCC3B";
166
+
regulator-name = "VREG_MISC_3P3";
167
167
regulator-min-microvolt = <3300000>;
168
168
regulator-max-microvolt = <3300000>;
169
169
170
-
gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
170
+
gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>;
171
171
enable-active-high;
172
172
173
173
pinctrl-names = "default";
···
180
180
vreg_wlan: regulator-wlan {
181
181
compatible = "regulator-fixed";
182
182
183
-
regulator-name = "VCC_WLAN_3R9";
183
+
regulator-name = "VPH_PWR_WLAN";
184
184
regulator-min-microvolt = <3900000>;
185
185
regulator-max-microvolt = <3900000>;
186
186
···
196
196
vreg_wwan: regulator-wwan {
197
197
compatible = "regulator-fixed";
198
198
199
-
regulator-name = "VCC3B_WAN";
199
+
regulator-name = "SDX_VPH_PWR";
200
200
regulator-min-microvolt = <3300000>;
201
201
regulator-max-microvolt = <3300000>;
202
202
···
234
234
235
235
mode-switch;
236
236
orientation-switch;
237
-
svid = /bits/ 16 <0xff01>;
238
237
239
238
port {
240
239
usb0_sbu_mux: endpoint {
···
253
254
254
255
mode-switch;
255
256
orientation-switch;
256
-
svid = /bits/ 16 <0xff01>;
257
257
258
258
port {
259
259
usb1_sbu_mux: endpoint {
···
755
757
};
756
758
757
759
misc_3p3_reg_en: misc-3p3-reg-en-state {
758
-
pins = "gpio1";
760
+
pins = "gpio2";
759
761
function = "normal";
760
762
};
761
763
};
+30
-16
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+30
-16
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
···
12
12
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13
13
#include <dt-bindings/input/gpio-keys.h>
14
14
#include <dt-bindings/input/input.h>
15
+
#include <dt-bindings/leds/common.h>
15
16
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16
17
17
18
#include "sc8280xp.dtsi"
···
76
75
linux,code = <SW_LID>;
77
76
wakeup-source;
78
77
wakeup-event-action = <EV_ACT_DEASSERTED>;
78
+
};
79
+
};
80
+
81
+
leds {
82
+
compatible = "gpio-leds";
83
+
84
+
led-camera-indicator {
85
+
label = "white:camera-indicator";
86
+
function = LED_FUNCTION_INDICATOR;
87
+
color = <LED_COLOR_ID_WHITE>;
88
+
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
89
+
linux,default-trigger = "none";
90
+
default-state = "off";
91
+
/* Reuse as a panic indicator until we get a "camera on" trigger */
92
+
panic-indicator;
79
93
};
80
94
};
81
95
···
350
334
351
335
mode-switch;
352
336
orientation-switch;
353
-
svid = /bits/ 16 <0xff01>;
354
337
355
338
port {
356
339
usb0_sbu_mux: endpoint {
···
369
354
370
355
mode-switch;
371
356
orientation-switch;
372
-
svid = /bits/ 16 <0xff01>;
373
357
374
358
port {
375
359
usb1_sbu_mux: endpoint {
···
850
836
&pmk8280_vadc {
851
837
status = "okay";
852
838
853
-
pmic-die-temp@3 {
839
+
channel@3 {
854
840
reg = <PMK8350_ADC7_DIE_TEMP>;
855
841
qcom,pre-scaling = <1 1>;
856
842
label = "pmk8350_die_temp";
857
843
};
858
844
859
-
xo-therm@44 {
845
+
channel@44 {
860
846
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
861
847
qcom,hw-settle-time = <200>;
862
848
qcom,ratiometric;
863
849
label = "pmk8350_xo_therm";
864
850
};
865
851
866
-
pmic-die-temp@103 {
852
+
channel@103 {
867
853
reg = <PM8350_ADC7_DIE_TEMP(1)>;
868
854
qcom,pre-scaling = <1 1>;
869
855
label = "pmc8280_1_die_temp";
870
856
};
871
857
872
-
sys-therm@144 {
858
+
channel@144 {
873
859
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
874
860
qcom,hw-settle-time = <200>;
875
861
qcom,ratiometric;
876
862
label = "sys_therm1";
877
863
};
878
864
879
-
sys-therm@145 {
865
+
channel@145 {
880
866
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
881
867
qcom,hw-settle-time = <200>;
882
868
qcom,ratiometric;
883
869
label = "sys_therm2";
884
870
};
885
871
886
-
sys-therm@146 {
872
+
channel@146 {
887
873
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
888
874
qcom,hw-settle-time = <200>;
889
875
qcom,ratiometric;
890
876
label = "sys_therm3";
891
877
};
892
878
893
-
sys-therm@147 {
879
+
channel@147 {
894
880
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
895
881
qcom,hw-settle-time = <200>;
896
882
qcom,ratiometric;
897
883
label = "sys_therm4";
898
884
};
899
885
900
-
pmic-die-temp@303 {
886
+
channel@303 {
901
887
reg = <PM8350_ADC7_DIE_TEMP(3)>;
902
888
qcom,pre-scaling = <1 1>;
903
889
label = "pmc8280_2_die_temp";
904
890
};
905
891
906
-
sys-therm@344 {
892
+
channel@344 {
907
893
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
908
894
qcom,hw-settle-time = <200>;
909
895
qcom,ratiometric;
910
896
label = "sys_therm5";
911
897
};
912
898
913
-
sys-therm@345 {
899
+
channel@345 {
914
900
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
915
901
qcom,hw-settle-time = <200>;
916
902
qcom,ratiometric;
917
903
label = "sys_therm6";
918
904
};
919
905
920
-
sys-therm@346 {
906
+
channel@346 {
921
907
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
922
908
qcom,hw-settle-time = <200>;
923
909
qcom,ratiometric;
924
910
label = "sys_therm7";
925
911
};
926
912
927
-
sys-therm@347 {
913
+
channel@347 {
928
914
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
929
915
qcom,hw-settle-time = <200>;
930
916
qcom,ratiometric;
931
917
label = "sys_therm8";
932
918
};
933
919
934
-
pmic-die-temp@403 {
920
+
channel@403 {
935
921
reg = <PMR735A_ADC7_DIE_TEMP>;
936
922
qcom,pre-scaling = <1 1>;
937
923
label = "pmr735a_die_temp";
···
1260
1246
};
1261
1247
1262
1248
&tlmm {
1263
-
gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
1249
+
gpio-reserved-ranges = <70 2>, <74 6>, <125 2>, <128 2>, <154 4>;
1264
1250
1265
1251
bt_default: bt-default-state {
1266
1252
hstp-bt-en-pins {
+1
-1
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
···
101
101
compatible = "qcom,pmk8350-rtc";
102
102
reg = <0x6100>, <0x6200>;
103
103
reg-names = "rtc", "alarm";
104
-
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
104
+
interrupts-extended = <&spmi_bus 0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
105
105
wakeup-source;
106
106
status = "disabled";
107
107
};
+2
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+2
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
···
298
298
firmware {
299
299
scm: scm {
300
300
compatible = "qcom,scm-sc8280xp", "qcom,scm";
301
+
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
301
302
};
302
303
};
303
304
···
4059
4058
interrupt-controller;
4060
4059
#interrupt-cells = <2>;
4061
4060
gpio-ranges = <&tlmm 0 0 230>;
4061
+
wakeup-parent = <&pdc>;
4062
4062
};
4063
4063
4064
4064
apps_smmu: iommu@15000000 {
+1
-1
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
+1
-1
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
+1
-1
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
+82
-78
arch/arm64/boot/dts/qcom/sdm630.dtsi
+82
-78
arch/arm64/boot/dts/qcom/sdm630.dtsi
···
359
359
method = "smc";
360
360
};
361
361
362
+
rpm: remoteproc {
363
+
compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
364
+
365
+
glink-edge {
366
+
compatible = "qcom,glink-rpm";
367
+
368
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
369
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
370
+
mboxes = <&apcs_glb 0>;
371
+
372
+
rpm_requests: rpm-requests {
373
+
compatible = "qcom,rpm-sdm660";
374
+
qcom,glink-channels = "rpm_requests";
375
+
376
+
rpmcc: clock-controller {
377
+
compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
378
+
#clock-cells = <1>;
379
+
};
380
+
381
+
rpmpd: power-controller {
382
+
compatible = "qcom,sdm660-rpmpd";
383
+
#power-domain-cells = <1>;
384
+
operating-points-v2 = <&rpmpd_opp_table>;
385
+
386
+
rpmpd_opp_table: opp-table {
387
+
compatible = "operating-points-v2";
388
+
389
+
rpmpd_opp_ret: opp1 {
390
+
opp-level = <RPM_SMD_LEVEL_RETENTION>;
391
+
};
392
+
393
+
rpmpd_opp_ret_plus: opp2 {
394
+
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
395
+
};
396
+
397
+
rpmpd_opp_min_svs: opp3 {
398
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
399
+
};
400
+
401
+
rpmpd_opp_low_svs: opp4 {
402
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
403
+
};
404
+
405
+
rpmpd_opp_svs: opp5 {
406
+
opp-level = <RPM_SMD_LEVEL_SVS>;
407
+
};
408
+
409
+
rpmpd_opp_svs_plus: opp6 {
410
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
411
+
};
412
+
413
+
rpmpd_opp_nom: opp7 {
414
+
opp-level = <RPM_SMD_LEVEL_NOM>;
415
+
};
416
+
417
+
rpmpd_opp_nom_plus: opp8 {
418
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
419
+
};
420
+
421
+
rpmpd_opp_turbo: opp9 {
422
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
423
+
};
424
+
};
425
+
};
426
+
};
427
+
};
428
+
};
429
+
362
430
reserved-memory {
363
431
#address-cells = <2>;
364
432
#size-cells = <2>;
···
505
437
compatible = "shared-dma-pool";
506
438
reg = <0x0 0xfed00000 0x0 0xa00000>;
507
439
no-map;
508
-
};
509
-
};
510
-
511
-
rpm-glink {
512
-
compatible = "qcom,glink-rpm";
513
-
514
-
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
515
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
516
-
mboxes = <&apcs_glb 0>;
517
-
518
-
rpm_requests: rpm-requests {
519
-
compatible = "qcom,rpm-sdm660";
520
-
qcom,glink-channels = "rpm_requests";
521
-
522
-
rpmcc: clock-controller {
523
-
compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
524
-
#clock-cells = <1>;
525
-
};
526
-
527
-
rpmpd: power-controller {
528
-
compatible = "qcom,sdm660-rpmpd";
529
-
#power-domain-cells = <1>;
530
-
operating-points-v2 = <&rpmpd_opp_table>;
531
-
532
-
rpmpd_opp_table: opp-table {
533
-
compatible = "operating-points-v2";
534
-
535
-
rpmpd_opp_ret: opp1 {
536
-
opp-level = <RPM_SMD_LEVEL_RETENTION>;
537
-
};
538
-
539
-
rpmpd_opp_ret_plus: opp2 {
540
-
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
541
-
};
542
-
543
-
rpmpd_opp_min_svs: opp3 {
544
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
545
-
};
546
-
547
-
rpmpd_opp_low_svs: opp4 {
548
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
549
-
};
550
-
551
-
rpmpd_opp_svs: opp5 {
552
-
opp-level = <RPM_SMD_LEVEL_SVS>;
553
-
};
554
-
555
-
rpmpd_opp_svs_plus: opp6 {
556
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
557
-
};
558
-
559
-
rpmpd_opp_nom: opp7 {
560
-
opp-level = <RPM_SMD_LEVEL_NOM>;
561
-
};
562
-
563
-
rpmpd_opp_nom_plus: opp8 {
564
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
565
-
};
566
-
567
-
rpmpd_opp_turbo: opp9 {
568
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
569
-
};
570
-
};
571
-
};
572
440
};
573
441
};
574
442
···
1034
1030
reg = <0x05000000 0x40000>;
1035
1031
reg-names = "kgsl_3d0_reg_memory";
1036
1032
1037
-
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1033
+
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1038
1034
1039
1035
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1040
1036
<&gpucc GPUCC_RBBMTIMER_CLK>,
···
1200
1196
1201
1197
spmi_bus: spmi@800f000 {
1202
1198
compatible = "qcom,spmi-pmic-arb";
1203
-
reg = <0x0800f000 0x1000>,
1204
-
<0x08400000 0x1000000>,
1205
-
<0x09400000 0x1000000>,
1206
-
<0x0a400000 0x220000>,
1207
-
<0x0800a000 0x3000>;
1199
+
reg = <0x0800f000 0x1000>,
1200
+
<0x08400000 0x1000000>,
1201
+
<0x09400000 0x1000000>,
1202
+
<0x0a400000 0x220000>,
1203
+
<0x0800a000 0x3000>;
1208
1204
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1209
1205
interrupt-names = "periph_irq";
1210
1206
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
···
2290
2286
2291
2287
frame@17921000 {
2292
2288
frame-number = <0>;
2293
-
interrupts = <0 8 0x4>,
2294
-
<0 7 0x4>;
2289
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2290
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2295
2291
reg = <0x17921000 0x1000>,
2296
2292
<0x17922000 0x1000>;
2297
2293
};
2298
2294
2299
2295
frame@17923000 {
2300
2296
frame-number = <1>;
2301
-
interrupts = <0 9 0x4>;
2297
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2302
2298
reg = <0x17923000 0x1000>;
2303
2299
status = "disabled";
2304
2300
};
2305
2301
2306
2302
frame@17924000 {
2307
2303
frame-number = <2>;
2308
-
interrupts = <0 10 0x4>;
2304
+
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2309
2305
reg = <0x17924000 0x1000>;
2310
2306
status = "disabled";
2311
2307
};
2312
2308
2313
2309
frame@17925000 {
2314
2310
frame-number = <3>;
2315
-
interrupts = <0 11 0x4>;
2311
+
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2316
2312
reg = <0x17925000 0x1000>;
2317
2313
status = "disabled";
2318
2314
};
2319
2315
2320
2316
frame@17926000 {
2321
2317
frame-number = <4>;
2322
-
interrupts = <0 12 0x4>;
2318
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2323
2319
reg = <0x17926000 0x1000>;
2324
2320
status = "disabled";
2325
2321
};
2326
2322
2327
2323
frame@17927000 {
2328
2324
frame-number = <5>;
2329
-
interrupts = <0 13 0x4>;
2325
+
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2330
2326
reg = <0x17927000 0x1000>;
2331
2327
status = "disabled";
2332
2328
};
2333
2329
2334
2330
frame@17928000 {
2335
2331
frame-number = <6>;
2336
-
interrupts = <0 14 0x4>;
2332
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2337
2333
reg = <0x17928000 0x1000>;
2338
2334
status = "disabled";
2339
2335
};
+1
-1
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
+1
-1
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
+186
arch/arm64/boot/dts/qcom/sdm670.dtsi
+186
arch/arm64/boot/dts/qcom/sdm670.dtsi
···
10
10
#include <dt-bindings/clock/qcom,rpmh.h>
11
11
#include <dt-bindings/dma/qcom-gpi.h>
12
12
#include <dt-bindings/gpio/gpio.h>
13
+
#include <dt-bindings/interconnect/qcom,osm-l3.h>
13
14
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
14
15
#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16
#include <dt-bindings/phy/phy-qcom-qusb2.h>
···
36
35
compatible = "qcom,kryo360";
37
36
reg = <0x0 0x0>;
38
37
enable-method = "psci";
38
+
capacity-dmips-mhz = <610>;
39
+
dynamic-power-coefficient = <203>;
40
+
qcom,freq-domain = <&cpufreq_hw 0>;
41
+
operating-points-v2 = <&cpu0_opp_table>;
42
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
43
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
39
44
power-domains = <&CPU_PD0>;
40
45
power-domain-names = "psci";
41
46
next-level-cache = <&L2_0>;
···
63
56
compatible = "qcom,kryo360";
64
57
reg = <0x0 0x100>;
65
58
enable-method = "psci";
59
+
capacity-dmips-mhz = <610>;
60
+
dynamic-power-coefficient = <203>;
61
+
qcom,freq-domain = <&cpufreq_hw 0>;
62
+
operating-points-v2 = <&cpu0_opp_table>;
63
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
64
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
66
65
power-domains = <&CPU_PD1>;
67
66
power-domain-names = "psci";
68
67
next-level-cache = <&L2_100>;
···
85
72
compatible = "qcom,kryo360";
86
73
reg = <0x0 0x200>;
87
74
enable-method = "psci";
75
+
capacity-dmips-mhz = <610>;
76
+
dynamic-power-coefficient = <203>;
77
+
qcom,freq-domain = <&cpufreq_hw 0>;
78
+
operating-points-v2 = <&cpu0_opp_table>;
79
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
80
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
88
81
power-domains = <&CPU_PD2>;
89
82
power-domain-names = "psci";
90
83
next-level-cache = <&L2_200>;
···
107
88
compatible = "qcom,kryo360";
108
89
reg = <0x0 0x300>;
109
90
enable-method = "psci";
91
+
capacity-dmips-mhz = <610>;
92
+
dynamic-power-coefficient = <203>;
93
+
qcom,freq-domain = <&cpufreq_hw 0>;
94
+
operating-points-v2 = <&cpu0_opp_table>;
95
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
96
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
110
97
power-domains = <&CPU_PD3>;
111
98
power-domain-names = "psci";
112
99
next-level-cache = <&L2_300>;
···
129
104
compatible = "qcom,kryo360";
130
105
reg = <0x0 0x400>;
131
106
enable-method = "psci";
107
+
capacity-dmips-mhz = <610>;
108
+
dynamic-power-coefficient = <203>;
109
+
qcom,freq-domain = <&cpufreq_hw 0>;
110
+
operating-points-v2 = <&cpu0_opp_table>;
111
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
112
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
132
113
power-domains = <&CPU_PD4>;
133
114
power-domain-names = "psci";
134
115
next-level-cache = <&L2_400>;
···
151
120
compatible = "qcom,kryo360";
152
121
reg = <0x0 0x500>;
153
122
enable-method = "psci";
123
+
capacity-dmips-mhz = <610>;
124
+
dynamic-power-coefficient = <203>;
125
+
qcom,freq-domain = <&cpufreq_hw 0>;
126
+
operating-points-v2 = <&cpu0_opp_table>;
127
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
128
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
154
129
power-domains = <&CPU_PD5>;
155
130
power-domain-names = "psci";
156
131
next-level-cache = <&L2_500>;
···
173
136
compatible = "qcom,kryo360";
174
137
reg = <0x0 0x600>;
175
138
enable-method = "psci";
139
+
capacity-dmips-mhz = <1024>;
140
+
dynamic-power-coefficient = <393>;
141
+
qcom,freq-domain = <&cpufreq_hw 1>;
142
+
operating-points-v2 = <&cpu6_opp_table>;
143
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
144
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
176
145
power-domains = <&CPU_PD6>;
177
146
power-domain-names = "psci";
178
147
next-level-cache = <&L2_600>;
···
195
152
compatible = "qcom,kryo360";
196
153
reg = <0x0 0x700>;
197
154
enable-method = "psci";
155
+
capacity-dmips-mhz = <1024>;
156
+
dynamic-power-coefficient = <393>;
157
+
qcom,freq-domain = <&cpufreq_hw 1>;
158
+
operating-points-v2 = <&cpu6_opp_table>;
159
+
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
160
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
198
161
power-domains = <&CPU_PD7>;
199
162
power-domain-names = "psci";
200
163
next-level-cache = <&L2_700>;
···
293
244
device_type = "memory";
294
245
/* We expect the bootloader to fill in the size */
295
246
reg = <0x0 0x80000000 0x0 0x0>;
247
+
};
248
+
249
+
cpu0_opp_table: opp-table-cpu0 {
250
+
compatible = "operating-points-v2";
251
+
opp-shared;
252
+
253
+
cpu0_opp1: opp-300000000 {
254
+
opp-hz = /bits/ 64 <300000000>;
255
+
opp-peak-kBps = <400000 4800000>;
256
+
};
257
+
258
+
cpu0_opp2: opp-576000000 {
259
+
opp-hz = /bits/ 64 <576000000>;
260
+
opp-peak-kBps = <400000 4800000>;
261
+
};
262
+
263
+
cpu0_opp3: opp-748800000 {
264
+
opp-hz = /bits/ 64 <748800000>;
265
+
opp-peak-kBps = <1200000 4800000>;
266
+
};
267
+
268
+
cpu0_opp4: opp-998400000 {
269
+
opp-hz = /bits/ 64 <998400000>;
270
+
opp-peak-kBps = <1804000 8908800>;
271
+
};
272
+
273
+
cpu0_opp5: opp-1209600000 {
274
+
opp-hz = /bits/ 64 <1209600000>;
275
+
opp-peak-kBps = <2188000 8908800>;
276
+
};
277
+
278
+
cpu0_opp6: opp-1324800000 {
279
+
opp-hz = /bits/ 64 <1324800000>;
280
+
opp-peak-kBps = <2188000 13516800>;
281
+
};
282
+
283
+
cpu0_opp7: opp-1516800000 {
284
+
opp-hz = /bits/ 64 <1516800000>;
285
+
opp-peak-kBps = <3072000 15052800>;
286
+
};
287
+
288
+
cpu0_opp8: opp-1612800000 {
289
+
opp-hz = /bits/ 64 <1612800000>;
290
+
opp-peak-kBps = <3072000 22118400>;
291
+
};
292
+
293
+
cpu0_opp9: opp-1708800000 {
294
+
opp-hz = /bits/ 64 <1708800000>;
295
+
opp-peak-kBps = <4068000 23040000>;
296
+
};
297
+
};
298
+
299
+
cpu6_opp_table: opp-table-cpu6 {
300
+
compatible = "operating-points-v2";
301
+
opp-shared;
302
+
303
+
cpu6_opp1: opp-300000000 {
304
+
opp-hz = /bits/ 64 <300000000>;
305
+
opp-peak-kBps = <400000 4800000>;
306
+
};
307
+
308
+
cpu6_opp2: opp-652800000 {
309
+
opp-hz = /bits/ 64 <652800000>;
310
+
opp-peak-kBps = <400000 4800000>;
311
+
};
312
+
313
+
cpu6_opp3: opp-825600000 {
314
+
opp-hz = /bits/ 64 <825600000>;
315
+
opp-peak-kBps = <1200000 4800000>;
316
+
};
317
+
318
+
cpu6_opp4: opp-979200000 {
319
+
opp-hz = /bits/ 64 <979200000>;
320
+
opp-peak-kBps = <1200000 4800000>;
321
+
};
322
+
323
+
cpu6_opp5: opp-1132800000 {
324
+
opp-hz = /bits/ 64 <1132800000>;
325
+
opp-peak-kBps = <2188000 8908800>;
326
+
};
327
+
328
+
cpu6_opp6: opp-1363200000 {
329
+
opp-hz = /bits/ 64 <1363200000>;
330
+
opp-peak-kBps = <4068000 12902400>;
331
+
};
332
+
333
+
cpu6_opp7: opp-1536000000 {
334
+
opp-hz = /bits/ 64 <1536000000>;
335
+
opp-peak-kBps = <4068000 12902400>;
336
+
};
337
+
338
+
cpu6_opp8: opp-1747200000 {
339
+
opp-hz = /bits/ 64 <1747200000>;
340
+
opp-peak-kBps = <4068000 15052800>;
341
+
};
342
+
343
+
cpu6_opp9: opp-1843200000 {
344
+
opp-hz = /bits/ 64 <1843200000>;
345
+
opp-peak-kBps = <4068000 15052800>;
346
+
};
347
+
348
+
cpu6_opp10: opp-1996800000 {
349
+
opp-hz = /bits/ 64 <1996800000>;
350
+
opp-peak-kBps = <6220000 19046400>;
351
+
};
296
352
};
297
353
298
354
psci {
···
1123
969
interrupt-controller;
1124
970
#interrupt-cells = <2>;
1125
971
gpio-ranges = <&tlmm 0 0 151>;
972
+
wakeup-parent = <&pdc>;
1126
973
1127
974
qup_i2c0_default: qup-i2c0-default-state {
1128
975
pins = "gpio0", "gpio1";
···
1324
1169
};
1325
1170
};
1326
1171
1172
+
pdc: interrupt-controller@b220000 {
1173
+
compatible = "qcom,sdm670-pdc", "qcom,pdc";
1174
+
reg = <0 0x0b220000 0 0x30000>;
1175
+
qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1176
+
<54 534 24>, <79 559 30>, <115 630 7>;
1177
+
#interrupt-cells = <2>;
1178
+
interrupt-parent = <&intc>;
1179
+
interrupt-controller;
1180
+
};
1181
+
1327
1182
spmi_bus: spmi@c440000 {
1328
1183
compatible = "qcom,spmi-pmic-arb";
1329
1184
reg = <0 0x0c440000 0 0x1100>,
···
1518
1353
interrupt-controller;
1519
1354
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1520
1355
#interrupt-cells = <3>;
1356
+
};
1357
+
1358
+
osm_l3: interconnect@17d41000 {
1359
+
compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
1360
+
reg = <0 0x17d41000 0 0x1400>;
1361
+
1362
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1363
+
clock-names = "xo", "alternate";
1364
+
1365
+
#interconnect-cells = <1>;
1366
+
};
1367
+
1368
+
cpufreq_hw: cpufreq@17d43000 {
1369
+
compatible = "qcom,cpufreq-hw";
1370
+
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
1371
+
reg-names = "freq-domain0", "freq-domain1";
1372
+
1373
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1374
+
clock-names = "xo", "alternate";
1375
+
1376
+
#freq-domain-cells = <1>;
1521
1377
};
1522
1378
};
1523
1379
};
+5
-5
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
+5
-5
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
···
1071
1071
};
1072
1072
1073
1073
&pm8998_adc {
1074
-
adc-chan@4d {
1074
+
channel@4d {
1075
1075
reg = <ADC5_AMUX_THM1_100K_PU>;
1076
1076
label = "sdm_temp";
1077
1077
};
1078
1078
1079
-
adc-chan@4e {
1079
+
channel@4e {
1080
1080
reg = <ADC5_AMUX_THM2_100K_PU>;
1081
1081
label = "quiet_temp";
1082
1082
};
1083
1083
1084
-
adc-chan@4f {
1084
+
channel@4f {
1085
1085
reg = <ADC5_AMUX_THM3_100K_PU>;
1086
1086
label = "lte_temp_1";
1087
1087
};
1088
1088
1089
-
adc-chan@50 {
1089
+
channel@50 {
1090
1090
reg = <ADC5_AMUX_THM4_100K_PU>;
1091
1091
label = "lte_temp_2";
1092
1092
};
1093
1093
1094
-
adc-chan@51 {
1094
+
channel@51 {
1095
1095
reg = <ADC5_AMUX_THM5_100K_PU>;
1096
1096
label = "charger_temp";
1097
1097
};
+16
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+16
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
···
101
101
};
102
102
};
103
103
104
+
reserved-memory {
105
+
/* Cont splash region set up by the bootloader */
106
+
cont_splash_mem: framebuffer@9d400000 {
107
+
reg = <0x0 0x9d400000 0x0 0x2400000>;
108
+
no-map;
109
+
};
110
+
};
111
+
104
112
lt9611_1v8: lt9611-vdd18-regulator {
105
113
compatible = "regulator-fixed";
106
114
regulator-name = "LT9611_1V8";
···
418
410
};
419
411
};
420
412
413
+
&camss {
414
+
status = "okay";
415
+
416
+
vdda-phy-supply = <&vreg_l1a_0p875>;
417
+
vdda-pll-supply = <&vreg_l26a_1p2>;
418
+
};
419
+
421
420
&cdsp_pas {
422
421
status = "okay";
423
422
firmware-name = "qcom/sdm845/cdsp.mbn";
···
521
506
};
522
507
523
508
&mdss {
509
+
memory-region = <&cont_splash_mem>;
524
510
status = "okay";
525
511
};
526
512
+7
-6
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+7
-6
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
···
15
15
/ {
16
16
model = "Qualcomm Technologies, Inc. SDM845 MTP";
17
17
compatible = "qcom,sdm845-mtp", "qcom,sdm845";
18
+
chassis-type = "handset";
18
19
19
20
aliases {
20
21
serial0 = &uart9;
···
534
533
};
535
534
536
535
&pm8998_adc {
537
-
adc-chan@4c {
536
+
channel@4c {
538
537
reg = <ADC5_XO_THERM_100K_PU>;
539
538
label = "xo_therm";
540
539
qcom,ratiometric;
541
540
qcom,hw-settle-time = <200>;
542
541
};
543
542
544
-
adc-chan@4d {
543
+
channel@4d {
545
544
reg = <ADC5_AMUX_THM1_100K_PU>;
546
545
label = "msm_therm";
547
546
qcom,ratiometric;
548
547
qcom,hw-settle-time = <200>;
549
548
};
550
549
551
-
adc-chan@4f {
550
+
channel@4f {
552
551
reg = <ADC5_AMUX_THM3_100K_PU>;
553
552
label = "pa_therm1";
554
553
qcom,ratiometric;
555
554
qcom,hw-settle-time = <200>;
556
555
};
557
556
558
-
adc-chan@51 {
557
+
channel@51 {
559
558
reg = <ADC5_AMUX_THM5_100K_PU>;
560
559
label = "quiet_therm";
561
560
qcom,ratiometric;
562
561
qcom,hw-settle-time = <200>;
563
562
};
564
563
565
-
adc-chan@83 {
564
+
channel@83 {
566
565
reg = <ADC5_VPH_PWR>;
567
566
label = "vph_pwr";
568
567
qcom,ratiometric;
569
568
qcom,hw-settle-time = <200>;
570
569
};
571
570
572
-
adc-chan@85 {
571
+
channel@85 {
573
572
reg = <ADC5_VCOIN>;
574
573
label = "vcoin";
575
574
qcom,ratiometric;
+3
-3
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts
+3
-3
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts
···
39
39
max98927_codec: max98927@3a {
40
40
compatible = "maxim,max98927";
41
41
reg = <0x3a>;
42
-
#sound-dai-cells = <1>;
42
+
#sound-dai-cells = <0>;
43
43
44
44
pinctrl-0 = <&speaker_default>;
45
45
pinctrl-names = "default";
···
57
57
58
58
&sound {
59
59
model = "OnePlus 6";
60
-
audio-routing = "RX_BIAS", "MCLK",
60
+
audio-routing = "RX_BIAS", "MCLK",
61
61
"AMIC2", "MIC BIAS2",
62
62
"AMIC3", "MIC BIAS4",
63
63
"AMIC4", "MIC BIAS1",
···
66
66
67
67
&speaker_playback_dai {
68
68
codec {
69
-
sound-dai = <&max98927_codec 0>;
69
+
sound-dai = <&max98927_codec>;
70
70
};
71
71
};
72
72
+1
-1
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
+1
-1
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
+9
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
+9
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
+6
-1
arch/arm64/boot/dts/qcom/sdm845.dtsi
+6
-1
arch/arm64/boot/dts/qcom/sdm845.dtsi
···
1207
1207
#clock-cells = <1>;
1208
1208
#reset-cells = <1>;
1209
1209
#power-domain-cells = <1>;
1210
+
power-domains = <&rpmhpd SDM845_CX>;
1210
1211
};
1211
1212
1212
1213
qfprom@784000 {
···
2614
2613
<0 0>,
2615
2614
<0 0>,
2616
2615
<0 0>,
2617
-
<0 300000000>;
2616
+
<75000000 300000000>;
2617
+
2618
+
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2619
+
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2620
+
interconnect-names = "ufs-ddr", "cpu-ufs";
2618
2621
2619
2622
status = "disabled";
2620
2623
};
+55
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
+55
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
···
33
33
chassis-type = "convertible";
34
34
35
35
aliases {
36
-
hsuart0 = &uart6;
36
+
serial0 = &uart9;
37
+
serial1 = &uart6;
37
38
};
38
39
39
40
gpio-keys {
···
81
80
};
82
81
};
83
82
83
+
sw_edp_1p2: edp-1p2-regulator {
84
+
compatible = "regulator-fixed";
85
+
regulator-name = "sw_edp_1p2";
86
+
87
+
regulator-min-microvolt = <1200000>;
88
+
regulator-max-microvolt = <1200000>;
89
+
90
+
pinctrl-0 = <&sw_edp_1p2_en>;
91
+
pinctrl-names = "default";
92
+
93
+
gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>;
94
+
enable-active-high;
95
+
96
+
vin-supply = <&vreg_l2a_1p2>;
97
+
};
98
+
84
99
sn65dsi86_refclk: sn65dsi86-refclk {
85
100
compatible = "fixed-clock";
86
101
#clock-cells = <0>;
87
102
88
103
clock-frequency = <19200000>;
104
+
};
105
+
106
+
vph_pwr: regulator-vph-pwr {
107
+
compatible = "regulator-fixed";
108
+
regulator-name = "vph_pwr";
109
+
regulator-min-microvolt = <3700000>;
110
+
regulator-max-microvolt = <3700000>;
111
+
};
112
+
113
+
vlcm_3v3: regulator-vlcm-3v3 {
114
+
compatible = "regulator-fixed";
115
+
regulator-name = "vlcm_3v3";
116
+
117
+
vin-supply = <&vph_pwr>;
118
+
regulator-min-microvolt = <3300000>;
119
+
regulator-max-microvolt = <3300000>;
120
+
121
+
gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
122
+
enable-active-high;
89
123
};
90
124
91
125
backlight: backlight {
···
423
387
424
388
enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
425
389
390
+
vcca-supply = <&sw_edp_1p2>;
391
+
vcc-supply = <&sw_edp_1p2>;
426
392
vpll-supply = <&vreg_l14a_1p88>;
427
393
vccio-supply = <&vreg_l14a_1p88>;
428
394
···
457
419
panel: panel {
458
420
compatible = "boe,nv133fhm-n61";
459
421
backlight = <&backlight>;
422
+
power-supply = <&vlcm_3v3>;
460
423
461
424
port {
462
425
panel_in_edp: endpoint {
···
517
478
&mss_pil {
518
479
status = "okay";
519
480
firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn";
481
+
};
482
+
483
+
&pm8998_gpios {
484
+
/* This pin is pulled down by a fixed resistor */
485
+
sw_edp_1p2_en: pm8998-gpio9-state {
486
+
pins = "gpio9";
487
+
function = "normal";
488
+
bias-disable;
489
+
qcom,drive-strength = <0>;
490
+
};
520
491
};
521
492
522
493
&qup_i2c10_default {
···
707
658
};
708
659
};
709
660
661
+
&uart9 {
662
+
status = "okay";
663
+
};
664
+
710
665
&ufs_mem_hc {
711
666
status = "okay";
712
667
···
832
779
833
780
&crypto {
834
781
/* FIXME: qce_start triggers an SError */
835
-
status = "disable";
782
+
status = "disabled";
836
783
};
+1
-1
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
+1
-1
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
+230
arch/arm64/boot/dts/qcom/sdx75-idp.dts
+230
arch/arm64/boot/dts/qcom/sdx75-idp.dts
···
5
5
6
6
/dts-v1/;
7
7
8
+
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
8
9
#include "sdx75.dtsi"
10
+
#include "pm7550ba.dtsi"
11
+
#include "pmk8550.dtsi"
12
+
#include "pmx75.dtsi"
9
13
10
14
/ {
11
15
model = "Qualcomm Technologies, Inc. SDX75 IDP";
···
17
13
18
14
aliases {
19
15
serial0 = &uart1;
16
+
};
17
+
18
+
vph_pwr: vph-pwr-regulator {
19
+
compatible = "regulator-fixed";
20
+
regulator-name = "vph_pwr";
21
+
regulator-min-microvolt = <3700000>;
22
+
regulator-max-microvolt = <3700000>;
23
+
};
24
+
25
+
vph_ext: vph-ext-regulator {
26
+
compatible = "regulator-fixed";
27
+
regulator-name = "vph_ext";
28
+
regulator-min-microvolt = <3700000>;
29
+
regulator-max-microvolt = <3700000>;
30
+
};
31
+
32
+
vreg_bob_3p3: pmx75-bob {
33
+
compatible = "regulator-fixed";
34
+
regulator-name = "vreg_bob_3p3";
35
+
regulator-min-microvolt = <3300000>;
36
+
regulator-max-microvolt = <3300000>;
37
+
38
+
vin-supply = <&vph_ext>;
39
+
};
40
+
};
41
+
42
+
&apps_rsc {
43
+
pmx75-rpmh-regulators {
44
+
compatible = "qcom,pmx75-rpmh-regulators";
45
+
qcom,pmic-id = "b";
46
+
47
+
vdd-s1-supply = <&vph_pwr>;
48
+
vdd-s2-supply = <&vph_pwr>;
49
+
vdd-s3-supply = <&vph_pwr>;
50
+
vdd-s4-supply = <&vph_pwr>;
51
+
vdd-s5-supply = <&vph_pwr>;
52
+
vdd-s6-supply = <&vph_pwr>;
53
+
vdd-s7-supply = <&vph_pwr>;
54
+
vdd-s8-supply = <&vph_pwr>;
55
+
vdd-s9-supply = <&vph_pwr>;
56
+
vdd-s10-supply = <&vph_pwr>;
57
+
vdd-l1-supply = <&vreg_s2b_1p224>;
58
+
vdd-l2-l18-supply = <&vreg_s2b_1p224>;
59
+
vdd-l3-supply = <&vreg_s7b_0p936>;
60
+
vdd-l4-l16-supply = <&vreg_s7b_0p936>;
61
+
vdd-l5-l6-supply = <&vreg_s4b_1p824>;
62
+
vdd-l7-supply = <&vreg_s7b_0p936>;
63
+
vdd-l8-l9-supply = <&vreg_s8b_0p824>;
64
+
vdd-l10-supply = <&vreg_bob_3p3>;
65
+
vdd-l11-l13-supply = <&vreg_bob_3p3>;
66
+
vdd-l12-supply = <&vreg_s2b_1p224>;
67
+
vdd-l14-supply = <&vreg_s3b_0p752>;
68
+
vdd-l15-supply = <&vreg_s2b_1p224>;
69
+
vdd-l17-supply = <&vreg_s8b_0p824>;
70
+
vdd-l19-supply = <&vreg_s7b_0p936>;
71
+
vdd-l20-l21-supply = <&vreg_s7b_0p936>;
72
+
73
+
vreg_s2b_1p224: smps2 {
74
+
regulator-name = "vreg_s2b_1p224";
75
+
regulator-min-microvolt = <1224000>;
76
+
regulator-max-microvolt = <1350000>;
77
+
};
78
+
79
+
vreg_s3b_0p752: smps3 {
80
+
regulator-name = "vreg_s3b_0p752";
81
+
regulator-min-microvolt = <684000>;
82
+
regulator-max-microvolt = <904000>;
83
+
};
84
+
85
+
vreg_s4b_1p824: smps4 {
86
+
regulator-name = "vreg_s4b_1p824";
87
+
regulator-min-microvolt = <1824000>;
88
+
regulator-max-microvolt = <1904000>;
89
+
};
90
+
91
+
vreg_s7b_0p936: smps7 {
92
+
regulator-name = "vreg_s7b_0p936";
93
+
regulator-min-microvolt = <352000>;
94
+
regulator-max-microvolt = <1060000>;
95
+
};
96
+
97
+
vreg_s8b_0p824: smps8 {
98
+
regulator-name = "vreg_s8b_0p824";
99
+
regulator-min-microvolt = <500000>;
100
+
regulator-max-microvolt = <1100000>;
101
+
};
102
+
103
+
vreg_l1b_1p2: ldo1 {
104
+
regulator-name = "vreg_l1b_1p2";
105
+
regulator-min-microvolt = <1200000>;
106
+
regulator-max-microvolt = <1200000>;
107
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
108
+
};
109
+
110
+
vreg_l2b_1p128: ldo2 {
111
+
regulator-name = "vreg_l2b_1p128";
112
+
regulator-min-microvolt = <1000000>;
113
+
regulator-max-microvolt = <1160000>;
114
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
115
+
};
116
+
117
+
vreg_l3b_0p896: ldo3 {
118
+
regulator-name = "vreg_l3b_0p896";
119
+
regulator-min-microvolt = <300000>;
120
+
regulator-max-microvolt = <1040000>;
121
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
122
+
};
123
+
124
+
vreg_l4b_0p88: ldo4 {
125
+
regulator-name = "vreg_l4b_0p88";
126
+
regulator-min-microvolt = <864000>;
127
+
regulator-max-microvolt = <912000>;
128
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
129
+
};
130
+
131
+
vreg_l5b_1p776: ldo5 {
132
+
regulator-name = "vreg_l5b_1p776";
133
+
regulator-min-microvolt = <1770000>;
134
+
regulator-max-microvolt = <1800000>;
135
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
136
+
};
137
+
138
+
vreg_l6b_1p8: ldo6 {
139
+
regulator-name = "vreg_l6b_1p8";
140
+
regulator-min-microvolt = <1800000>;
141
+
regulator-max-microvolt = <1800000>;
142
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
143
+
};
144
+
145
+
vreg_l7b_0p904: ldo7 {
146
+
regulator-name = "vreg_l7b_0p904";
147
+
regulator-min-microvolt = <300000>;
148
+
regulator-max-microvolt = <960000>;
149
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
150
+
};
151
+
152
+
vreg_l8b_0p8: ldo8 {
153
+
regulator-name = "vreg_l8b_0p8";
154
+
regulator-min-microvolt = <800000>;
155
+
regulator-max-microvolt = <800000>;
156
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
157
+
};
158
+
159
+
vreg_l9b_0p752: ldo9 {
160
+
regulator-name = "vreg_l9b_0p752";
161
+
regulator-min-microvolt = <752000>;
162
+
regulator-max-microvolt = <800000>;
163
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
164
+
};
165
+
166
+
vreg_l10b_3p08: ldo10 {
167
+
regulator-name = "vreg_l10b_3p08";
168
+
regulator-min-microvolt = <3008000>;
169
+
regulator-max-microvolt = <3088000>;
170
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
171
+
};
172
+
173
+
vreg_l11b_1p8: ldo11 {
174
+
regulator-name = "vreg_l11b_1p8";
175
+
regulator-min-microvolt = <1704000>;
176
+
regulator-max-microvolt = <2928000>;
177
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
178
+
};
179
+
180
+
vreg_l12b_1p2: ldo12 {
181
+
regulator-name = "vreg_l12b_1p2";
182
+
regulator-min-microvolt = <1200000>;
183
+
regulator-max-microvolt = <1200000>;
184
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
185
+
};
186
+
187
+
vreg_l13b_1p8: ldo13 {
188
+
regulator-name = "vreg_l13b_1p8";
189
+
regulator-min-microvolt = <1704000>;
190
+
regulator-max-microvolt = <2928000>;
191
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
192
+
};
193
+
194
+
vreg_l14b_0p624: ldo14 {
195
+
regulator-name = "vreg_l14b_0p624";
196
+
regulator-min-microvolt = <300000>;
197
+
regulator-max-microvolt = <800000>;
198
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
199
+
};
200
+
201
+
vreg_l15b_1p2: ldo15 {
202
+
regulator-name = "vreg_l15b_1p2";
203
+
regulator-min-microvolt = <1200000>;
204
+
regulator-max-microvolt = <1200000>;
205
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
206
+
};
207
+
208
+
vreg_l16b_0p912: ldo16 {
209
+
regulator-name = "vreg_l16b_0p912";
210
+
regulator-min-microvolt = <880000>;
211
+
regulator-max-microvolt = <920000>;
212
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
213
+
};
214
+
215
+
vreg_l17b_0p752: ldo17 {
216
+
regulator-name = "vreg_l17b_0p752";
217
+
regulator-min-microvolt = <684000>;
218
+
regulator-max-microvolt = <957600>;
219
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
220
+
};
221
+
222
+
vreg_l19b_0p952: ldo19 {
223
+
regulator-name = "vreg_l19b_0p952";
224
+
regulator-min-microvolt = <900000>;
225
+
regulator-max-microvolt = <960000>;
226
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
227
+
};
228
+
229
+
vreg_l20b_0p912: ldo20 {
230
+
regulator-name = "vreg_l20b_0p912";
231
+
regulator-min-microvolt = <912000>;
232
+
regulator-max-microvolt = <952000>;
233
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
234
+
};
235
+
236
+
vreg_l21b_0p856: ldo21 {
237
+
regulator-name = "vreg_l21b_0p856";
238
+
regulator-min-microvolt = <300000>;
239
+
regulator-max-microvolt = <1000000>;
240
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
241
+
};
20
242
};
21
243
};
22
244
+77
-2
arch/arm64/boot/dts/qcom/sdx75.dtsi
+77
-2
arch/arm64/boot/dts/qcom/sdx75.dtsi
···
9
9
#include <dt-bindings/clock/qcom,rpmh.h>
10
10
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
11
11
#include <dt-bindings/interrupt-controller/arm-gic.h>
12
+
#include <dt-bindings/power/qcom,rpmhpd.h>
13
+
#include <dt-bindings/power/qcom-rpmpd.h>
12
14
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
13
15
14
16
/ {
···
471
469
interrupt-controller;
472
470
};
473
471
472
+
spmi_bus: spmi@c400000 {
473
+
compatible = "qcom,spmi-pmic-arb";
474
+
reg = <0x0 0x0c400000 0x0 0x3000>,
475
+
<0x0 0x0c500000 0x0 0x400000>,
476
+
<0x0 0x0c440000 0x0 0x80000>,
477
+
<0x0 0x0c4c0000 0x0 0x10000>,
478
+
<0x0 0x0c42d000 0x0 0x4000>;
479
+
reg-names = "core",
480
+
"chnls",
481
+
"obsrvr",
482
+
"intr",
483
+
"cnfg";
484
+
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
485
+
interrupt-names = "periph_irq";
486
+
qcom,ee = <0>;
487
+
qcom,channel = <0>;
488
+
qcom,bus-id = <0>;
489
+
#address-cells = <2>;
490
+
#size-cells = <0>;
491
+
interrupt-controller;
492
+
#interrupt-cells = <4>;
493
+
};
494
+
474
495
tlmm: pinctrl@f000000 {
475
496
compatible = "qcom,sdx75-tlmm";
476
497
reg = <0x0 0x0f000000 0x0 0x400000>;
···
509
484
tx-pins {
510
485
pins = "gpio12";
511
486
function = "qup_se1_l2_mira";
512
-
drive-strength= <2>;
487
+
drive-strength = <2>;
513
488
bias-disable;
514
489
};
515
490
516
491
rx-pins {
517
492
pins = "gpio13";
518
493
function = "qup_se1_l3_mira";
519
-
drive-strength= <2>;
494
+
drive-strength = <2>;
520
495
bias-disable;
521
496
};
522
497
};
···
667
642
clocks = <&xo_board>;
668
643
clock-names = "xo";
669
644
#clock-cells = <1>;
645
+
};
646
+
647
+
rpmhpd: power-controller {
648
+
compatible = "qcom,sdx75-rpmhpd";
649
+
#power-domain-cells = <1>;
650
+
operating-points-v2 = <&rpmhpd_opp_table>;
651
+
652
+
rpmhpd_opp_table: opp-table {
653
+
compatible = "operating-points-v2";
654
+
655
+
rpmhpd_opp_ret: opp-16 {
656
+
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
657
+
};
658
+
659
+
rpmhpd_opp_min_svs: opp-48 {
660
+
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
661
+
};
662
+
663
+
rpmhpd_opp_low_svs: opp-64 {
664
+
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
665
+
};
666
+
667
+
rpmhpd_opp_svs: opp-128 {
668
+
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
669
+
};
670
+
671
+
rpmhpd_opp_svs_l1: opp-192 {
672
+
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
673
+
};
674
+
675
+
rpmhpd_opp_nom: opp-256 {
676
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
677
+
};
678
+
679
+
rpmhpd_opp_nom_l1: opp-320 {
680
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
681
+
};
682
+
683
+
rpmhpd_opp_nom_l2: opp-336 {
684
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
685
+
};
686
+
687
+
rpmhpd_opp_turbo: opp-384 {
688
+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
689
+
};
690
+
691
+
rpmhpd_opp_turbo_l1: opp-416 {
692
+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
693
+
};
694
+
};
670
695
};
671
696
};
672
697
+18
arch/arm64/boot/dts/qcom/sm4450-qrd.dts
+18
arch/arm64/boot/dts/qcom/sm4450-qrd.dts
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "sm4450.dtsi"
9
+
/ {
10
+
model = "Qualcomm Technologies, Inc. SM4450 QRD";
11
+
compatible = "qcom,sm4450-qrd", "qcom,sm4450";
12
+
13
+
aliases { };
14
+
15
+
chosen {
16
+
bootargs = "console=hvc0";
17
+
};
18
+
};
+431
arch/arm64/boot/dts/qcom/sm4450.dtsi
+431
arch/arm64/boot/dts/qcom/sm4450.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <dt-bindings/gpio/gpio.h>
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
9
+
/ {
10
+
interrupt-parent = <&intc>;
11
+
12
+
#address-cells = <2>;
13
+
#size-cells = <2>;
14
+
15
+
chosen { };
16
+
17
+
clocks{
18
+
xo_board: xo-board {
19
+
compatible = "fixed-clock";
20
+
clock-frequency = <76800000>;
21
+
#clock-cells = <0>;
22
+
};
23
+
24
+
sleep_clk: sleep-clk {
25
+
compatible = "fixed-clock";
26
+
clock-frequency = <32000>;
27
+
#clock-cells = <0>;
28
+
};
29
+
};
30
+
31
+
cpus {
32
+
#address-cells = <2>;
33
+
#size-cells = <0>;
34
+
35
+
CPU0: cpu@0 {
36
+
device_type = "cpu";
37
+
compatible = "arm,cortex-a55";
38
+
reg = <0x0 0x0>;
39
+
enable-method = "psci";
40
+
next-level-cache = <&L2_0>;
41
+
power-domains = <&CPU_PD0>;
42
+
power-domain-names = "psci";
43
+
#cooling-cells = <2>;
44
+
45
+
L2_0: l2-cache {
46
+
compatible = "cache";
47
+
cache-level = <2>;
48
+
cache-unified;
49
+
next-level-cache = <&L3_0>;
50
+
51
+
L3_0: l3-cache {
52
+
compatible = "cache";
53
+
cache-level = <3>;
54
+
cache-unified;
55
+
};
56
+
};
57
+
};
58
+
59
+
CPU1: cpu@100 {
60
+
device_type = "cpu";
61
+
compatible = "arm,cortex-a55";
62
+
reg = <0x0 0x100>;
63
+
enable-method = "psci";
64
+
next-level-cache = <&L2_100>;
65
+
power-domains = <&CPU_PD0>;
66
+
power-domain-names = "psci";
67
+
#cooling-cells = <2>;
68
+
69
+
L2_100: l2-cache {
70
+
compatible = "cache";
71
+
cache-level = <2>;
72
+
cache-unified;
73
+
next-level-cache = <&L3_0>;
74
+
};
75
+
};
76
+
77
+
CPU2: cpu@200 {
78
+
device_type = "cpu";
79
+
compatible = "arm,cortex-a55";
80
+
reg = <0x0 0x200>;
81
+
enable-method = "psci";
82
+
next-level-cache = <&L2_200>;
83
+
power-domains = <&CPU_PD0>;
84
+
power-domain-names = "psci";
85
+
#cooling-cells = <2>;
86
+
87
+
L2_200: l2-cache {
88
+
compatible = "cache";
89
+
cache-level = <2>;
90
+
cache-unified;
91
+
next-level-cache = <&L3_0>;
92
+
};
93
+
};
94
+
95
+
CPU3: cpu@300 {
96
+
device_type = "cpu";
97
+
compatible = "arm,cortex-a55";
98
+
reg = <0x0 0x300>;
99
+
enable-method = "psci";
100
+
next-level-cache = <&L2_300>;
101
+
power-domains = <&CPU_PD0>;
102
+
power-domain-names = "psci";
103
+
#cooling-cells = <2>;
104
+
105
+
L2_300: l2-cache {
106
+
compatible = "cache";
107
+
cache-level = <2>;
108
+
cache-unified;
109
+
next-level-cache = <&L3_0>;
110
+
};
111
+
};
112
+
113
+
CPU4: cpu@400 {
114
+
device_type = "cpu";
115
+
compatible = "arm,cortex-a55";
116
+
reg = <0x0 0x400>;
117
+
enable-method = "psci";
118
+
next-level-cache = <&L2_400>;
119
+
power-domains = <&CPU_PD0>;
120
+
power-domain-names = "psci";
121
+
#cooling-cells = <2>;
122
+
123
+
L2_400: l2-cache {
124
+
compatible = "cache";
125
+
cache-level = <2>;
126
+
cache-unified;
127
+
next-level-cache = <&L3_0>;
128
+
};
129
+
};
130
+
131
+
CPU5: cpu@500 {
132
+
device_type = "cpu";
133
+
compatible = "arm,cortex-a55";
134
+
reg = <0x0 0x500>;
135
+
enable-method = "psci";
136
+
next-level-cache = <&L2_500>;
137
+
power-domains = <&CPU_PD0>;
138
+
power-domain-names = "psci";
139
+
#cooling-cells = <2>;
140
+
141
+
L2_500: l2-cache {
142
+
compatible = "cache";
143
+
cache-level = <2>;
144
+
cache-unified;
145
+
next-level-cache = <&L3_0>;
146
+
};
147
+
};
148
+
149
+
CPU6: cpu@600 {
150
+
device_type = "cpu";
151
+
compatible = "arm,cortex-a78";
152
+
reg = <0x0 0x600>;
153
+
enable-method = "psci";
154
+
next-level-cache = <&L2_600>;
155
+
power-domains = <&CPU_PD0>;
156
+
power-domain-names = "psci";
157
+
#cooling-cells = <2>;
158
+
159
+
L2_600: l2-cache {
160
+
compatible = "cache";
161
+
cache-level = <2>;
162
+
cache-unified;
163
+
next-level-cache = <&L3_0>;
164
+
};
165
+
};
166
+
167
+
CPU7: cpu@700 {
168
+
device_type = "cpu";
169
+
compatible = "arm,cortex-a78";
170
+
reg = <0x0 0x700>;
171
+
enable-method = "psci";
172
+
next-level-cache = <&L2_700>;
173
+
power-domains = <&CPU_PD0>;
174
+
power-domain-names = "psci";
175
+
#cooling-cells = <2>;
176
+
177
+
L2_700: l2-cache {
178
+
compatible = "cache";
179
+
cache-level = <2>;
180
+
cache-unified;
181
+
next-level-cache = <&L3_0>;
182
+
};
183
+
};
184
+
185
+
cpu-map {
186
+
cluster0 {
187
+
core0 {
188
+
cpu = <&CPU0>;
189
+
};
190
+
191
+
core1 {
192
+
cpu = <&CPU1>;
193
+
};
194
+
195
+
core2 {
196
+
cpu = <&CPU2>;
197
+
};
198
+
199
+
core3 {
200
+
cpu = <&CPU3>;
201
+
};
202
+
203
+
core4 {
204
+
cpu = <&CPU4>;
205
+
};
206
+
207
+
core5 {
208
+
cpu = <&CPU5>;
209
+
};
210
+
211
+
core6 {
212
+
cpu = <&CPU6>;
213
+
};
214
+
215
+
core7 {
216
+
cpu = <&CPU7>;
217
+
};
218
+
};
219
+
};
220
+
221
+
idle-states {
222
+
entry-method = "psci";
223
+
224
+
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
225
+
compatible = "arm,idle-state";
226
+
arm,psci-suspend-param = <0x40000004>;
227
+
entry-latency-us = <800>;
228
+
exit-latency-us = <750>;
229
+
min-residency-us = <4090>;
230
+
local-timer-stop;
231
+
};
232
+
233
+
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
234
+
compatible = "arm,idle-state";
235
+
arm,psci-suspend-param = <0x40000004>;
236
+
entry-latency-us = <600>;
237
+
exit-latency-us = <1550>;
238
+
min-residency-us = <4791>;
239
+
local-timer-stop;
240
+
};
241
+
};
242
+
243
+
domain-idle-states {
244
+
CLUSTER_SLEEP_0: cluster-sleep-0 {
245
+
compatible = "domain-idle-state";
246
+
arm,psci-suspend-param = <0x41000044>;
247
+
entry-latency-us = <1050>;
248
+
exit-latency-us = <2500>;
249
+
min-residency-us = <5309>;
250
+
};
251
+
252
+
CLUSTER_SLEEP_1: cluster-sleep-1 {
253
+
compatible = "domain-idle-state";
254
+
arm,psci-suspend-param = <0x41003344>;
255
+
entry-latency-us = <1561>;
256
+
exit-latency-us = <2801>;
257
+
min-residency-us = <8550>;
258
+
};
259
+
};
260
+
};
261
+
262
+
memory@a0000000 {
263
+
device_type = "memory";
264
+
/* We expect the bootloader to fill in the size */
265
+
reg = <0x0 0xa0000000 0x0 0x0>;
266
+
};
267
+
268
+
pmu {
269
+
compatible = "arm,armv8-pmuv3";
270
+
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
271
+
};
272
+
273
+
psci {
274
+
compatible = "arm,psci-1.0";
275
+
method = "smc";
276
+
277
+
CPU_PD0: power-domain-cpu0 {
278
+
#power-domain-cells = <0>;
279
+
power-domains = <&CLUSTER_PD>;
280
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
281
+
};
282
+
283
+
CPU_PD1: power-domain-cpu1 {
284
+
#power-domain-cells = <0>;
285
+
power-domains = <&CLUSTER_PD>;
286
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
287
+
};
288
+
289
+
CPU_PD2: power-domain-cpu2 {
290
+
#power-domain-cells = <0>;
291
+
power-domains = <&CLUSTER_PD>;
292
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
293
+
};
294
+
295
+
CPU_PD3: power-domain-cpu3 {
296
+
#power-domain-cells = <0>;
297
+
power-domains = <&CLUSTER_PD>;
298
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
299
+
};
300
+
301
+
CPU_PD4: power-domain-cpu4 {
302
+
#power-domain-cells = <0>;
303
+
power-domains = <&CLUSTER_PD>;
304
+
domain-idle-states = <&BIG_CPU_SLEEP_0>;
305
+
};
306
+
307
+
CPU_PD5: power-domain-cpu5 {
308
+
#power-domain-cells = <0>;
309
+
power-domains = <&CLUSTER_PD>;
310
+
domain-idle-states = <&BIG_CPU_SLEEP_0>;
311
+
};
312
+
313
+
CPU_PD6: power-domain-cpu6 {
314
+
#power-domain-cells = <0>;
315
+
power-domains = <&CLUSTER_PD>;
316
+
domain-idle-states = <&BIG_CPU_SLEEP_0>;
317
+
};
318
+
319
+
CPU_PD7: power-domain-cpu7 {
320
+
#power-domain-cells = <0>;
321
+
power-domains = <&CLUSTER_PD>;
322
+
domain-idle-states = <&BIG_CPU_SLEEP_0>;
323
+
};
324
+
325
+
CLUSTER_PD: power-domain-cpu-cluster0 {
326
+
#power-domain-cells = <0>;
327
+
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
328
+
};
329
+
};
330
+
331
+
soc: soc@0 {
332
+
#address-cells = <2>;
333
+
#size-cells = <2>;
334
+
ranges = <0 0 0 0 0x10 0>;
335
+
dma-ranges = <0 0 0 0 0x10 0>;
336
+
compatible = "simple-bus";
337
+
338
+
tcsr_mutex: hwlock@1f40000 {
339
+
compatible = "qcom,tcsr-mutex";
340
+
reg = <0x0 0x01f40000 0x0 0x40000>;
341
+
#hwlock-cells = <1>;
342
+
};
343
+
344
+
pdc: interrupt-controller@b220000 {
345
+
compatible = "qcom,sm4450-pdc", "qcom,pdc";
346
+
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
347
+
qcom,pdc-ranges = <0 480 94>, <94 494 31>,
348
+
<125 63 1>;
349
+
#interrupt-cells = <2>;
350
+
interrupt-parent = <&intc>;
351
+
interrupt-controller;
352
+
};
353
+
354
+
intc: interrupt-controller@17200000 {
355
+
compatible = "arm,gic-v3";
356
+
reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
357
+
<0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
358
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
359
+
#interrupt-cells = <3>;
360
+
interrupt-controller;
361
+
#redistributor-regions = <1>;
362
+
redistributor-stride = <0x0 0x20000>;
363
+
};
364
+
365
+
timer@17420000 {
366
+
compatible = "arm,armv7-timer-mem";
367
+
reg = <0x0 0x17420000 0x0 0x1000>;
368
+
ranges = <0 0 0 0x20000000>;
369
+
#address-cells = <1>;
370
+
#size-cells = <1>;
371
+
372
+
frame@17421000 {
373
+
reg = <0x17421000 0x1000>,
374
+
<0x17422000 0x1000>;
375
+
frame-number = <0>;
376
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
377
+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
378
+
};
379
+
380
+
frame@17423000 {
381
+
reg = <0x17423000 0x1000>;
382
+
frame-number = <1>;
383
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
384
+
status = "disabled";
385
+
};
386
+
387
+
frame@17425000 {
388
+
reg = <0x17425000 0x1000>;
389
+
frame-number = <2>;
390
+
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
391
+
status = "disabled";
392
+
};
393
+
394
+
frame@17427000 {
395
+
reg = <0x17427000 0x1000>;
396
+
frame-number = <3>;
397
+
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
398
+
status = "disabled";
399
+
};
400
+
401
+
frame@17429000 {
402
+
reg = <0x17429000 0x1000>;
403
+
frame-number = <4>;
404
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
405
+
status = "disabled";
406
+
};
407
+
408
+
frame@1742b000 {
409
+
reg = <0x1742b000 0x1000>;
410
+
frame-number = <5>;
411
+
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
412
+
status = "disabled";
413
+
};
414
+
415
+
frame@1742d000 {
416
+
reg = <0x1742d000 0x1000>;
417
+
frame-number = <6>;
418
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
419
+
status = "disabled";
420
+
};
421
+
};
422
+
};
423
+
424
+
timer {
425
+
compatible = "arm,armv8-timer";
426
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
427
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
428
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
429
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
430
+
};
431
+
};
+1
-1
arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts
+1
-1
arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts
+170
-63
arch/arm64/boot/dts/qcom/sm6115.dtsi
+170
-63
arch/arm64/boot/dts/qcom/sm6115.dtsi
···
341
341
};
342
342
};
343
343
344
+
rpm: remoteproc {
345
+
compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
346
+
347
+
glink-edge {
348
+
compatible = "qcom,glink-rpm";
349
+
350
+
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
351
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
352
+
mboxes = <&apcs_glb 0>;
353
+
354
+
rpm_requests: rpm-requests {
355
+
compatible = "qcom,rpm-sm6115";
356
+
qcom,glink-channels = "rpm_requests";
357
+
358
+
rpmcc: clock-controller {
359
+
compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
360
+
clocks = <&xo_board>;
361
+
clock-names = "xo";
362
+
#clock-cells = <1>;
363
+
};
364
+
365
+
rpmpd: power-controller {
366
+
compatible = "qcom,sm6115-rpmpd";
367
+
#power-domain-cells = <1>;
368
+
operating-points-v2 = <&rpmpd_opp_table>;
369
+
370
+
rpmpd_opp_table: opp-table {
371
+
compatible = "operating-points-v2";
372
+
373
+
rpmpd_opp_min_svs: opp1 {
374
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
375
+
};
376
+
377
+
rpmpd_opp_low_svs: opp2 {
378
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
379
+
};
380
+
381
+
rpmpd_opp_svs: opp3 {
382
+
opp-level = <RPM_SMD_LEVEL_SVS>;
383
+
};
384
+
385
+
rpmpd_opp_svs_plus: opp4 {
386
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
387
+
};
388
+
389
+
rpmpd_opp_nom: opp5 {
390
+
opp-level = <RPM_SMD_LEVEL_NOM>;
391
+
};
392
+
393
+
rpmpd_opp_nom_plus: opp6 {
394
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
395
+
};
396
+
397
+
rpmpd_opp_turbo: opp7 {
398
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
399
+
};
400
+
401
+
rpmpd_opp_turbo_plus: opp8 {
402
+
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
403
+
};
404
+
};
405
+
};
406
+
};
407
+
};
408
+
};
409
+
344
410
reserved_memory: reserved-memory {
345
411
#address-cells = <2>;
346
412
#size-cells = <2>;
···
503
437
504
438
qcom,client-id = <1>;
505
439
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
506
-
};
507
-
};
508
-
509
-
rpm-glink {
510
-
compatible = "qcom,glink-rpm";
511
-
512
-
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
513
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
514
-
mboxes = <&apcs_glb 0>;
515
-
516
-
rpm_requests: rpm-requests {
517
-
compatible = "qcom,rpm-sm6115";
518
-
qcom,glink-channels = "rpm_requests";
519
-
520
-
rpmcc: clock-controller {
521
-
compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
522
-
clocks = <&xo_board>;
523
-
clock-names = "xo";
524
-
#clock-cells = <1>;
525
-
};
526
-
527
-
rpmpd: power-controller {
528
-
compatible = "qcom,sm6115-rpmpd";
529
-
#power-domain-cells = <1>;
530
-
operating-points-v2 = <&rpmpd_opp_table>;
531
-
532
-
rpmpd_opp_table: opp-table {
533
-
compatible = "operating-points-v2";
534
-
535
-
rpmpd_opp_min_svs: opp1 {
536
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
537
-
};
538
-
539
-
rpmpd_opp_low_svs: opp2 {
540
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
541
-
};
542
-
543
-
rpmpd_opp_svs: opp3 {
544
-
opp-level = <RPM_SMD_LEVEL_SVS>;
545
-
};
546
-
547
-
rpmpd_opp_svs_plus: opp4 {
548
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
549
-
};
550
-
551
-
rpmpd_opp_nom: opp5 {
552
-
opp-level = <RPM_SMD_LEVEL_NOM>;
553
-
};
554
-
555
-
rpmpd_opp_nom_plus: opp6 {
556
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
557
-
};
558
-
559
-
rpmpd_opp_turbo: opp7 {
560
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
561
-
};
562
-
563
-
rpmpd_opp_turbo_plus: opp8 {
564
-
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
565
-
};
566
-
};
567
-
};
568
440
};
569
441
};
570
442
···
869
865
reg = <0x25b 0x1>;
870
866
bits = <1 4>;
871
867
};
868
+
869
+
gpu_speed_bin: gpu-speed-bin@6006 {
870
+
reg = <0x6006 0x2>;
871
+
bits = <5 8>;
872
+
};
872
873
};
873
874
874
875
rng: rng@1b53000 {
···
1061
1052
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1062
1053
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1063
1054
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1064
-
dma-channels = <10>;
1055
+
dma-channels = <10>;
1065
1056
dma-channel-mask = <0xf>;
1066
1057
iommus = <&apps_smmu 0xf6 0x0>;
1067
1058
#dma-cells = <3>;
···
1323
1314
snps,hird-threshold = /bits/ 8 <0x10>;
1324
1315
snps,usb3_lpm_capable;
1325
1316
};
1317
+
};
1318
+
1319
+
gpu: gpu@5900000 {
1320
+
compatible = "qcom,adreno-610.0", "qcom,adreno";
1321
+
reg = <0x0 0x05900000 0x0 0x40000>;
1322
+
reg-names = "kgsl_3d0_reg_memory";
1323
+
1324
+
/* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1325
+
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
1326
+
<&gpucc GPU_CC_AHB_CLK>,
1327
+
<&gcc GCC_BIMC_GPU_AXI_CLK>,
1328
+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1329
+
<&gpucc GPU_CC_CX_GMU_CLK>,
1330
+
<&gpucc GPU_CC_CXO_CLK>;
1331
+
clock-names = "core",
1332
+
"iface",
1333
+
"mem_iface",
1334
+
"alt_mem_iface",
1335
+
"gmu",
1336
+
"xo";
1337
+
1338
+
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1339
+
1340
+
iommus = <&adreno_smmu 0 1>;
1341
+
operating-points-v2 = <&gpu_opp_table>;
1342
+
power-domains = <&rpmpd SM6115_VDDCX>;
1343
+
qcom,gmu = <&gmu_wrapper>;
1344
+
1345
+
nvmem-cells = <&gpu_speed_bin>;
1346
+
nvmem-cell-names = "speed_bin";
1347
+
1348
+
status = "disabled";
1349
+
1350
+
zap-shader {
1351
+
memory-region = <&pil_gpu_mem>;
1352
+
};
1353
+
1354
+
gpu_opp_table: opp-table {
1355
+
compatible = "operating-points-v2";
1356
+
1357
+
opp-320000000 {
1358
+
opp-hz = /bits/ 64 <320000000>;
1359
+
required-opps = <&rpmpd_opp_low_svs>;
1360
+
opp-supported-hw = <0x1f>;
1361
+
};
1362
+
1363
+
opp-465000000 {
1364
+
opp-hz = /bits/ 64 <465000000>;
1365
+
required-opps = <&rpmpd_opp_svs>;
1366
+
opp-supported-hw = <0x1f>;
1367
+
};
1368
+
1369
+
opp-600000000 {
1370
+
opp-hz = /bits/ 64 <600000000>;
1371
+
required-opps = <&rpmpd_opp_svs_plus>;
1372
+
opp-supported-hw = <0x1f>;
1373
+
};
1374
+
1375
+
opp-745000000 {
1376
+
opp-hz = /bits/ 64 <745000000>;
1377
+
required-opps = <&rpmpd_opp_nom>;
1378
+
opp-supported-hw = <0xf>;
1379
+
};
1380
+
1381
+
opp-820000000 {
1382
+
opp-hz = /bits/ 64 <820000000>;
1383
+
required-opps = <&rpmpd_opp_nom_plus>;
1384
+
opp-supported-hw = <0x7>;
1385
+
};
1386
+
1387
+
opp-900000000 {
1388
+
opp-hz = /bits/ 64 <900000000>;
1389
+
required-opps = <&rpmpd_opp_turbo>;
1390
+
opp-supported-hw = <0x7>;
1391
+
};
1392
+
1393
+
/* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
1394
+
opp-950000000 {
1395
+
opp-hz = /bits/ 64 <950000000>;
1396
+
required-opps = <&rpmpd_opp_turbo_plus>;
1397
+
opp-supported-hw = <0x4>;
1398
+
};
1399
+
1400
+
opp-980000000 {
1401
+
opp-hz = /bits/ 64 <980000000>;
1402
+
required-opps = <&rpmpd_opp_turbo_plus>;
1403
+
opp-supported-hw = <0x3>;
1404
+
};
1405
+
};
1406
+
};
1407
+
1408
+
gmu_wrapper: gmu@596a000 {
1409
+
compatible = "qcom,adreno-gmu-wrapper";
1410
+
reg = <0x0 0x0596a000 0x0 0x30000>;
1411
+
reg-names = "gmu";
1412
+
power-domains = <&gpucc GPU_CX_GDSC>,
1413
+
<&gpucc GPU_GX_GDSC>;
1414
+
power-domain-names = "cx", "gx";
1326
1415
};
1327
1416
1328
1417
gpucc: clock-controller@5990000 {
+60
-5
arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
+60
-5
arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
···
65
65
};
66
66
};
67
67
68
-
&dispcc {
69
-
/* HACK: disable until a panel driver is ready to retain simplefb */
70
-
status = "disabled";
68
+
&gpu {
69
+
status = "okay";
70
+
71
+
zap-shader {
72
+
firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn";
73
+
};
74
+
};
75
+
76
+
&mdss {
77
+
status = "okay";
78
+
};
79
+
80
+
&mdss_dsi0 {
81
+
vdda-supply = <&pm6125_l18>;
82
+
status = "okay";
83
+
84
+
panel: panel@0 {
85
+
compatible = "lenovo,j606f-boe-nt36523w", "novatek,nt36523w";
86
+
reg = <0>;
87
+
88
+
reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
89
+
vddio-supply = <&pm6125_l9>;
90
+
91
+
pinctrl-names = "default";
92
+
pinctrl-0 = <&te_active &mdss_dsi_active>;
93
+
94
+
rotation = <180>; /* Yep, it's mounted upside down! */
95
+
96
+
port {
97
+
panel_in: endpoint {
98
+
remote-endpoint = <&mdss_dsi0_out>;
99
+
};
100
+
};
101
+
};
102
+
};
103
+
104
+
&mdss_dsi0_out {
105
+
data-lanes = <0 1 2 3>;
106
+
remote-endpoint = <&panel_in>;
107
+
};
108
+
109
+
&mdss_dsi0_phy {
110
+
status = "okay";
71
111
};
72
112
73
113
&pm6125_gpios {
···
252
212
};
253
213
254
214
pm6125_l18: l18 {
255
-
regulator-min-microvolt = <1104000>;
256
-
regulator-max-microvolt = <1312000>;
215
+
/* 1.104V-1.312V fixed @ 1.232V for DSIPHY */
216
+
regulator-min-microvolt = <1232000>;
217
+
regulator-max-microvolt = <1232000>;
257
218
};
258
219
259
220
pm6125_l19: l19 {
···
322
281
drive-strength = <2>;
323
282
bias-pull-up;
324
283
output-high;
284
+
};
285
+
286
+
te_active: te-active-state {
287
+
pins = "gpio81";
288
+
function = "mdp_vsync";
289
+
drive-strength = <2>;
290
+
bias-pull-down;
291
+
};
292
+
293
+
mdss_dsi_active: dsi-active-state {
294
+
pins = "gpio82";
295
+
function = "gpio";
296
+
drive-strength = <8>;
297
+
bias-disable;
325
298
};
326
299
};
327
300
+12
-7
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
+12
-7
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
···
42
42
43
43
extcon_usb: extcon-usb {
44
44
compatible = "linux,extcon-usb-gpio";
45
-
id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
45
+
id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
46
46
};
47
47
48
48
gpio-keys {
···
79
79
reg = <0x0 0xffc40000 0x0 0xc0000>;
80
80
record-size = <0x1000>;
81
81
console-size = <0x40000>;
82
-
msg-size = <0x20000 0x20000>;
82
+
pmsg-size = <0x20000>;
83
83
};
84
84
85
85
cmdline_mem: memory@ffd00000 {
···
183
183
pinctrl-names = "default";
184
184
pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
185
185
186
-
rf-pa0-therm@4d {
186
+
channel@4d {
187
187
reg = <ADC5_AMUX_THM1_100K_PU>;
188
188
qcom,ratiometric;
189
189
qcom,hw-settle-time = <200>;
190
190
qcom,pre-scaling = <1 1>;
191
+
label = "rf_pa0_therm";
191
192
};
192
193
193
-
quiet-therm@4e {
194
+
channel@4e {
194
195
reg = <ADC5_AMUX_THM2_100K_PU>;
195
196
qcom,ratiometric;
196
197
qcom,hw-settle-time = <200>;
197
198
qcom,pre-scaling = <1 1>;
199
+
label = "quiet_therm";
198
200
};
199
201
200
-
camera-flash-therm@52 {
202
+
channel@52 {
201
203
reg = <ADC5_GPIO1_100K_PU>;
202
204
qcom,ratiometric;
203
205
qcom,hw-settle-time = <200>;
204
206
qcom,pre-scaling = <1 1>;
207
+
label = "camera_flash_therm";
205
208
};
206
209
207
-
emmc-ufs-therm@54 {
210
+
channel@54 {
208
211
reg = <ADC5_GPIO3_100K_PU>;
209
212
qcom,ratiometric;
210
213
qcom,hw-settle-time = <200>;
211
214
qcom,pre-scaling = <1 1>;
215
+
label = "emmc_ufs_therm";
212
216
};
213
217
214
-
rf-pa1-therm@55 {
218
+
channel@55 {
215
219
reg = <ADC5_GPIO4_100K_PU>;
216
220
qcom,ratiometric;
217
221
qcom,hw-settle-time = <200>;
218
222
qcom,pre-scaling = <1 1>;
223
+
label = "rf_pa1_therm";
219
224
};
220
225
};
221
226
+2
-2
arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts
+2
-2
arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts
···
52
52
reg = <0x0 0xffc40000 0x0 0xc0000>;
53
53
record-size = <0x1000>;
54
54
console-size = <0x40000>;
55
-
msg-size = <0x20000 0x20000>;
55
+
pmsg-size = <0x20000>;
56
56
};
57
57
58
58
cmdline_mem: memory@ffd00000 {
···
63
63
64
64
extcon_usb: usb-id {
65
65
compatible = "linux,extcon-usb-gpio";
66
-
id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
66
+
id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
67
67
};
68
68
69
69
gpio-keys {
+72
-68
arch/arm64/boot/dts/qcom/sm6125.dtsi
+72
-68
arch/arm64/boot/dts/qcom/sm6125.dtsi
···
181
181
method = "smc";
182
182
};
183
183
184
+
rpm: remoteproc {
185
+
compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
186
+
187
+
glink-edge {
188
+
compatible = "qcom,glink-rpm";
189
+
190
+
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
191
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
192
+
mboxes = <&apcs_glb 0>;
193
+
194
+
rpm_requests: rpm-requests {
195
+
compatible = "qcom,rpm-sm6125";
196
+
qcom,glink-channels = "rpm_requests";
197
+
198
+
rpmcc: clock-controller {
199
+
compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
200
+
#clock-cells = <1>;
201
+
};
202
+
203
+
rpmpd: power-controller {
204
+
compatible = "qcom,sm6125-rpmpd";
205
+
#power-domain-cells = <1>;
206
+
operating-points-v2 = <&rpmpd_opp_table>;
207
+
208
+
rpmpd_opp_table: opp-table {
209
+
compatible = "operating-points-v2";
210
+
211
+
rpmpd_opp_ret: opp1 {
212
+
opp-level = <RPM_SMD_LEVEL_RETENTION>;
213
+
};
214
+
215
+
rpmpd_opp_ret_plus: opp2 {
216
+
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
217
+
};
218
+
219
+
rpmpd_opp_min_svs: opp3 {
220
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
221
+
};
222
+
223
+
rpmpd_opp_low_svs: opp4 {
224
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
225
+
};
226
+
227
+
rpmpd_opp_svs: opp5 {
228
+
opp-level = <RPM_SMD_LEVEL_SVS>;
229
+
};
230
+
231
+
rpmpd_opp_svs_plus: opp6 {
232
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
233
+
};
234
+
235
+
rpmpd_opp_nom: opp7 {
236
+
opp-level = <RPM_SMD_LEVEL_NOM>;
237
+
};
238
+
239
+
rpmpd_opp_nom_plus: opp8 {
240
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
241
+
};
242
+
243
+
rpmpd_opp_turbo: opp9 {
244
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
245
+
};
246
+
247
+
rpmpd_opp_turbo_no_cpr: opp10 {
248
+
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
249
+
};
250
+
};
251
+
};
252
+
};
253
+
};
254
+
};
255
+
184
256
reserved_memory: reserved-memory {
185
257
#address-cells = <2>;
186
258
#size-cells = <2>;
···
361
289
qseecom_ta_mem: memory@13fc00000 {
362
290
reg = <0x1 0x3fc00000 0x0 0x400000>;
363
291
no-map;
364
-
};
365
-
};
366
-
367
-
rpm-glink {
368
-
compatible = "qcom,glink-rpm";
369
-
370
-
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
371
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
372
-
mboxes = <&apcs_glb 0>;
373
-
374
-
rpm_requests: rpm-requests {
375
-
compatible = "qcom,rpm-sm6125";
376
-
qcom,glink-channels = "rpm_requests";
377
-
378
-
rpmcc: clock-controller {
379
-
compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
380
-
#clock-cells = <1>;
381
-
};
382
-
383
-
rpmpd: power-controller {
384
-
compatible = "qcom,sm6125-rpmpd";
385
-
#power-domain-cells = <1>;
386
-
operating-points-v2 = <&rpmpd_opp_table>;
387
-
388
-
rpmpd_opp_table: opp-table {
389
-
compatible = "operating-points-v2";
390
-
391
-
rpmpd_opp_ret: opp1 {
392
-
opp-level = <RPM_SMD_LEVEL_RETENTION>;
393
-
};
394
-
395
-
rpmpd_opp_ret_plus: opp2 {
396
-
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
397
-
};
398
-
399
-
rpmpd_opp_min_svs: opp3 {
400
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
401
-
};
402
-
403
-
rpmpd_opp_low_svs: opp4 {
404
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
405
-
};
406
-
407
-
rpmpd_opp_svs: opp5 {
408
-
opp-level = <RPM_SMD_LEVEL_SVS>;
409
-
};
410
-
411
-
rpmpd_opp_svs_plus: opp6 {
412
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
413
-
};
414
-
415
-
rpmpd_opp_nom: opp7 {
416
-
opp-level = <RPM_SMD_LEVEL_NOM>;
417
-
};
418
-
419
-
rpmpd_opp_nom_plus: opp8 {
420
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
421
-
};
422
-
423
-
rpmpd_opp_turbo: opp9 {
424
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
425
-
};
426
-
427
-
rpmpd_opp_turbo_no_cpr: opp10 {
428
-
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
429
-
};
430
-
};
431
-
};
432
292
};
433
293
};
434
294
+488
-6
arch/arm64/boot/dts/qcom/sm6350.dtsi
+488
-6
arch/arm64/boot/dts/qcom/sm6350.dtsi
···
4
4
* Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
5
5
*/
6
6
7
+
#include <dt-bindings/clock/qcom,dispcc-sm6350.h>
7
8
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
9
+
#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
8
10
#include <dt-bindings/clock/qcom,rpmh.h>
9
11
#include <dt-bindings/clock/qcom,sm6350-camcc.h>
10
12
#include <dt-bindings/dma/qcom-gpi.h>
···
635
633
no-map;
636
634
};
637
635
638
-
pil_gpu_mem: memory@8b715400 {
639
-
reg = <0 0x8b715400 0 0x2000>;
640
-
no-map;
641
-
};
642
-
643
636
pil_modem_mem: memory@8b800000 {
644
637
reg = <0 0x8b800000 0 0xf800000>;
645
638
no-map;
···
655
658
no-map;
656
659
};
657
660
661
+
pil_gpu_mem: memory@f0d00000 {
662
+
reg = <0 0xf0d00000 0 0x1000>;
663
+
no-map;
664
+
};
665
+
658
666
debug_region: memory@ffb00000 {
659
667
reg = <0 0xffb00000 0 0xc0000>;
660
668
no-map;
···
675
673
reg = <0 0xffc00000 0 0x100000>;
676
674
record-size = <0x1000>;
677
675
console-size = <0x40000>;
678
-
msg-size = <0x20000 0x20000>;
676
+
pmsg-size = <0x20000>;
679
677
ecc-size = <16>;
680
678
no-map;
681
679
};
···
804
802
interrupt-controller;
805
803
#interrupt-cells = <3>;
806
804
#mbox-cells = <2>;
805
+
};
806
+
807
+
qfprom: qfprom@784000 {
808
+
compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
809
+
reg = <0 0x00784000 0 0x3000>;
810
+
#address-cells = <1>;
811
+
#size-cells = <1>;
812
+
813
+
gpu_speed_bin: gpu-speed-bin@2015 {
814
+
reg = <0x2015 0x1>;
815
+
bits = <0 8>;
816
+
};
807
817
};
808
818
809
819
rng: rng@793000 {
···
1322
1308
};
1323
1309
};
1324
1310
1311
+
gpu: gpu@3d00000 {
1312
+
compatible = "qcom,adreno-619.0", "qcom,adreno";
1313
+
reg = <0 0x03d00000 0 0x40000>,
1314
+
<0 0x03d9e000 0 0x1000>;
1315
+
reg-names = "kgsl_3d0_reg_memory",
1316
+
"cx_mem";
1317
+
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1318
+
1319
+
iommus = <&adreno_smmu 0>;
1320
+
operating-points-v2 = <&gpu_opp_table>;
1321
+
qcom,gmu = <&gmu>;
1322
+
nvmem-cells = <&gpu_speed_bin>;
1323
+
nvmem-cell-names = "speed_bin";
1324
+
1325
+
status = "disabled";
1326
+
1327
+
zap-shader {
1328
+
memory-region = <&pil_gpu_mem>;
1329
+
};
1330
+
1331
+
gpu_opp_table: opp-table {
1332
+
compatible = "operating-points-v2";
1333
+
1334
+
opp-850000000 {
1335
+
opp-hz = /bits/ 64 <850000000>;
1336
+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1337
+
opp-supported-hw = <0x02>;
1338
+
};
1339
+
1340
+
opp-800000000 {
1341
+
opp-hz = /bits/ 64 <800000000>;
1342
+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1343
+
opp-supported-hw = <0x04>;
1344
+
};
1345
+
1346
+
opp-650000000 {
1347
+
opp-hz = /bits/ 64 <650000000>;
1348
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1349
+
opp-supported-hw = <0x08>;
1350
+
};
1351
+
1352
+
opp-565000000 {
1353
+
opp-hz = /bits/ 64 <565000000>;
1354
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1355
+
opp-supported-hw = <0x10>;
1356
+
};
1357
+
1358
+
opp-430000000 {
1359
+
opp-hz = /bits/ 64 <430000000>;
1360
+
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1361
+
opp-supported-hw = <0xff>;
1362
+
};
1363
+
1364
+
opp-355000000 {
1365
+
opp-hz = /bits/ 64 <355000000>;
1366
+
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1367
+
opp-supported-hw = <0xff>;
1368
+
};
1369
+
1370
+
opp-253000000 {
1371
+
opp-hz = /bits/ 64 <253000000>;
1372
+
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1373
+
opp-supported-hw = <0xff>;
1374
+
};
1375
+
};
1376
+
};
1377
+
1378
+
adreno_smmu: iommu@3d40000 {
1379
+
compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1380
+
reg = <0 0x03d40000 0 0x10000>;
1381
+
#iommu-cells = <1>;
1382
+
#global-interrupts = <2>;
1383
+
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1384
+
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1385
+
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1386
+
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1387
+
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1388
+
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1389
+
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1390
+
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
1391
+
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
1392
+
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1393
+
1394
+
clocks = <&gpucc GPU_CC_AHB_CLK>,
1395
+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1396
+
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1397
+
clock-names = "ahb",
1398
+
"bus",
1399
+
"iface";
1400
+
1401
+
power-domains = <&gpucc GPU_CX_GDSC>;
1402
+
};
1403
+
1404
+
gmu: gmu@3d6a000 {
1405
+
compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1406
+
reg = <0 0x03d6a000 0 0x31000>,
1407
+
<0 0x0b290000 0 0x10000>,
1408
+
<0 0x0b490000 0 0x10000>;
1409
+
reg-names = "gmu",
1410
+
"gmu_pdc",
1411
+
"gmu_pdc_seq";
1412
+
1413
+
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1414
+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1415
+
interrupt-names = "hfi",
1416
+
"gmu";
1417
+
1418
+
clocks = <&gpucc GPU_CC_AHB_CLK>,
1419
+
<&gpucc GPU_CC_CX_GMU_CLK>,
1420
+
<&gpucc GPU_CC_CXO_CLK>,
1421
+
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
1422
+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1423
+
clock-names = "ahb",
1424
+
"gmu",
1425
+
"cxo",
1426
+
"axi",
1427
+
"memnoc";
1428
+
1429
+
power-domains = <&gpucc GPU_CX_GDSC>,
1430
+
<&gpucc GPU_GX_GDSC>;
1431
+
power-domain-names = "cx",
1432
+
"gx";
1433
+
1434
+
iommus = <&adreno_smmu 5>;
1435
+
1436
+
operating-points-v2 = <&gmu_opp_table>;
1437
+
1438
+
status = "disabled";
1439
+
1440
+
gmu_opp_table: opp-table {
1441
+
compatible = "operating-points-v2";
1442
+
1443
+
opp-200000000 {
1444
+
opp-hz = /bits/ 64 <200000000>;
1445
+
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1446
+
};
1447
+
};
1448
+
};
1449
+
1450
+
gpucc: clock-controller@3d90000 {
1451
+
compatible = "qcom,sm6350-gpucc";
1452
+
reg = <0 0x03d90000 0 0x9000>;
1453
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
1454
+
<&gcc GCC_GPU_GPLL0_CLK>,
1455
+
<&gcc GCC_GPU_GPLL0_DIV_CLK>;
1456
+
clock-names = "bi_tcxo",
1457
+
"gcc_gpu_gpll0_clk_src",
1458
+
"gcc_gpu_gpll0_div_clk_src";
1459
+
#clock-cells = <1>;
1460
+
#reset-cells = <1>;
1461
+
#power-domain-cells = <1>;
1462
+
};
1463
+
1325
1464
mpss: remoteproc@4080000 {
1326
1465
compatible = "qcom,sm6350-mpss-pas";
1327
1466
reg = <0x0 0x04080000 0x0 0x4040>;
···
1723
1556
qcom,bcm-voters = <&apps_bcm_voter>;
1724
1557
};
1725
1558
1559
+
pmu@90b6300 {
1560
+
compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1561
+
reg = <0x0 0x090b6300 0x0 0x600>;
1562
+
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
1563
+
1564
+
operating-points-v2 = <&llcc_bwmon_opp_table>;
1565
+
interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
1566
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;
1567
+
1568
+
llcc_bwmon_opp_table: opp-table {
1569
+
compatible = "operating-points-v2";
1570
+
1571
+
opp-0 {
1572
+
opp-peak-kBps = <2288000>;
1573
+
};
1574
+
1575
+
opp-1 {
1576
+
opp-peak-kBps = <4577000>;
1577
+
};
1578
+
1579
+
opp-2 {
1580
+
opp-peak-kBps = <7110000>;
1581
+
};
1582
+
1583
+
opp-3 {
1584
+
opp-peak-kBps = <9155000>;
1585
+
};
1586
+
1587
+
opp-4 {
1588
+
opp-peak-kBps = <12298000>;
1589
+
};
1590
+
1591
+
opp-5 {
1592
+
opp-peak-kBps = <14236000>;
1593
+
};
1594
+
1595
+
};
1596
+
};
1597
+
1598
+
pmu@90cd000 {
1599
+
compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1600
+
reg = <0x0 0x090cd000 0x0 0x1000>;
1601
+
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1602
+
1603
+
operating-points-v2 = <&cpu_bwmon_opp_table>;
1604
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
1605
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;
1606
+
1607
+
cpu_bwmon_opp_table: opp-table {
1608
+
compatible = "operating-points-v2";
1609
+
1610
+
opp-0 {
1611
+
opp-peak-kBps = <762000>;
1612
+
};
1613
+
1614
+
opp-1 {
1615
+
opp-peak-kBps = <1144000>;
1616
+
};
1617
+
1618
+
opp-2 {
1619
+
opp-peak-kBps = <1720000>;
1620
+
};
1621
+
1622
+
opp-3 {
1623
+
opp-peak-kBps = <2086000>;
1624
+
};
1625
+
1626
+
opp-4 {
1627
+
opp-peak-kBps = <2597000>;
1628
+
};
1629
+
1630
+
opp-5 {
1631
+
opp-peak-kBps = <2929000>;
1632
+
};
1633
+
1634
+
opp-6 {
1635
+
opp-peak-kBps = <3879000>;
1636
+
};
1637
+
1638
+
opp-7 {
1639
+
opp-peak-kBps = <5161000>;
1640
+
};
1641
+
1642
+
opp-8 {
1643
+
opp-peak-kBps = <5931000>;
1644
+
};
1645
+
1646
+
opp-9 {
1647
+
opp-peak-kBps = <6881000>;
1648
+
};
1649
+
1650
+
opp-10 {
1651
+
opp-peak-kBps = <7980000>;
1652
+
};
1653
+
};
1654
+
};
1655
+
1726
1656
usb_1: usb@a6f8800 {
1727
1657
compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1728
1658
reg = <0 0x0a6f8800 0 0x400>;
···
1967
1703
#power-domain-cells = <1>;
1968
1704
};
1969
1705
1706
+
mdss: display-subsystem@ae00000 {
1707
+
compatible = "qcom,sm6350-mdss";
1708
+
reg = <0 0x0ae00000 0 0x1000>;
1709
+
reg-names = "mdss";
1710
+
1711
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1712
+
interrupt-controller;
1713
+
#interrupt-cells = <1>;
1714
+
1715
+
clocks = <&gcc GCC_DISP_AHB_CLK>,
1716
+
<&gcc GCC_DISP_AXI_CLK>,
1717
+
<&dispcc DISP_CC_MDSS_MDP_CLK>;
1718
+
clock-names = "iface",
1719
+
"bus",
1720
+
"core";
1721
+
1722
+
power-domains = <&dispcc MDSS_GDSC>;
1723
+
iommus = <&apps_smmu 0x800 0x2>;
1724
+
1725
+
#address-cells = <2>;
1726
+
#size-cells = <2>;
1727
+
ranges;
1728
+
1729
+
status = "disabled";
1730
+
1731
+
mdss_mdp: display-controller@ae01000 {
1732
+
compatible = "qcom,sm6350-dpu";
1733
+
reg = <0 0x0ae01000 0 0x8f000>,
1734
+
<0 0x0aeb0000 0 0x2008>;
1735
+
reg-names = "mdp", "vbif";
1736
+
1737
+
interrupt-parent = <&mdss>;
1738
+
interrupts = <0>;
1739
+
1740
+
clocks = <&gcc GCC_DISP_AXI_CLK>,
1741
+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
1742
+
<&dispcc DISP_CC_MDSS_ROT_CLK>,
1743
+
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1744
+
<&dispcc DISP_CC_MDSS_MDP_CLK>,
1745
+
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1746
+
clock-names = "bus",
1747
+
"iface",
1748
+
"rot",
1749
+
"lut",
1750
+
"core",
1751
+
"vsync";
1752
+
1753
+
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1754
+
assigned-clock-rates = <19200000>;
1755
+
1756
+
operating-points-v2 = <&mdp_opp_table>;
1757
+
power-domains = <&rpmhpd SM6350_CX>;
1758
+
1759
+
ports {
1760
+
#address-cells = <1>;
1761
+
#size-cells = <0>;
1762
+
1763
+
port@0 {
1764
+
reg = <0>;
1765
+
1766
+
dpu_intf1_out: endpoint {
1767
+
remote-endpoint = <&mdss_dsi0_in>;
1768
+
};
1769
+
};
1770
+
};
1771
+
1772
+
mdp_opp_table: opp-table {
1773
+
compatible = "operating-points-v2";
1774
+
1775
+
opp-19200000 {
1776
+
opp-hz = /bits/ 64 <19200000>;
1777
+
required-opps = <&rpmhpd_opp_min_svs>;
1778
+
};
1779
+
1780
+
opp-200000000 {
1781
+
opp-hz = /bits/ 64 <200000000>;
1782
+
required-opps = <&rpmhpd_opp_low_svs>;
1783
+
};
1784
+
1785
+
opp-300000000 {
1786
+
opp-hz = /bits/ 64 <300000000>;
1787
+
required-opps = <&rpmhpd_opp_svs>;
1788
+
};
1789
+
1790
+
opp-373333333 {
1791
+
opp-hz = /bits/ 64 <373333333>;
1792
+
required-opps = <&rpmhpd_opp_svs_l1>;
1793
+
};
1794
+
1795
+
opp-448000000 {
1796
+
opp-hz = /bits/ 64 <448000000>;
1797
+
required-opps = <&rpmhpd_opp_nom>;
1798
+
};
1799
+
1800
+
opp-560000000 {
1801
+
opp-hz = /bits/ 64 <560000000>;
1802
+
required-opps = <&rpmhpd_opp_turbo>;
1803
+
};
1804
+
};
1805
+
};
1806
+
1807
+
mdss_dsi0: dsi@ae94000 {
1808
+
compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1809
+
reg = <0 0x0ae94000 0 0x400>;
1810
+
reg-names = "dsi_ctrl";
1811
+
1812
+
interrupt-parent = <&mdss>;
1813
+
interrupts = <4>;
1814
+
1815
+
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1816
+
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1817
+
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1818
+
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
1819
+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
1820
+
<&gcc GCC_DISP_AXI_CLK>;
1821
+
clock-names = "byte",
1822
+
"byte_intf",
1823
+
"pixel",
1824
+
"core",
1825
+
"iface",
1826
+
"bus";
1827
+
1828
+
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1829
+
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1830
+
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1831
+
1832
+
operating-points-v2 = <&mdss_dsi_opp_table>;
1833
+
power-domains = <&rpmhpd SM6350_MX>;
1834
+
1835
+
phys = <&mdss_dsi0_phy>;
1836
+
phy-names = "dsi";
1837
+
1838
+
#address-cells = <1>;
1839
+
#size-cells = <0>;
1840
+
1841
+
status = "disabled";
1842
+
1843
+
ports {
1844
+
#address-cells = <1>;
1845
+
#size-cells = <0>;
1846
+
1847
+
port@0 {
1848
+
reg = <0>;
1849
+
1850
+
mdss_dsi0_in: endpoint {
1851
+
remote-endpoint = <&dpu_intf1_out>;
1852
+
};
1853
+
};
1854
+
1855
+
port@1 {
1856
+
reg = <1>;
1857
+
1858
+
mdss_dsi0_out: endpoint {
1859
+
};
1860
+
};
1861
+
};
1862
+
1863
+
mdss_dsi_opp_table: opp-table {
1864
+
compatible = "operating-points-v2";
1865
+
1866
+
opp-187500000 {
1867
+
opp-hz = /bits/ 64 <187500000>;
1868
+
required-opps = <&rpmhpd_opp_low_svs>;
1869
+
};
1870
+
1871
+
opp-300000000 {
1872
+
opp-hz = /bits/ 64 <300000000>;
1873
+
required-opps = <&rpmhpd_opp_svs>;
1874
+
};
1875
+
1876
+
opp-358000000 {
1877
+
opp-hz = /bits/ 64 <358000000>;
1878
+
required-opps = <&rpmhpd_opp_svs_l1>;
1879
+
};
1880
+
};
1881
+
};
1882
+
1883
+
mdss_dsi0_phy: phy@ae94400 {
1884
+
compatible = "qcom,dsi-phy-10nm";
1885
+
reg = <0 0x0ae94400 0 0x200>,
1886
+
<0 0x0ae94600 0 0x280>,
1887
+
<0 0x0ae94a00 0 0x1e0>;
1888
+
reg-names = "dsi_phy",
1889
+
"dsi_phy_lane",
1890
+
"dsi_pll";
1891
+
1892
+
#clock-cells = <1>;
1893
+
#phy-cells = <0>;
1894
+
1895
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1896
+
<&rpmhcc RPMH_CXO_CLK>;
1897
+
clock-names = "iface", "ref";
1898
+
1899
+
status = "disabled";
1900
+
};
1901
+
};
1902
+
1903
+
dispcc: clock-controller@af00000 {
1904
+
compatible = "qcom,sm6350-dispcc";
1905
+
reg = <0 0x0af00000 0 0x20000>;
1906
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
1907
+
<&gcc GCC_DISP_GPLL0_CLK>,
1908
+
<&mdss_dsi0_phy 0>,
1909
+
<&mdss_dsi0_phy 1>,
1910
+
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
1911
+
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
1912
+
clock-names = "bi_tcxo",
1913
+
"gcc_disp_gpll0_clk",
1914
+
"dsi0_phy_pll_out_byteclk",
1915
+
"dsi0_phy_pll_out_dsiclk",
1916
+
"dp_phy_pll_link_clk",
1917
+
"dp_phy_pll_vco_div_clk";
1918
+
#clock-cells = <1>;
1919
+
#reset-cells = <1>;
1920
+
#power-domain-cells = <1>;
1921
+
};
1922
+
1970
1923
pdc: interrupt-controller@b220000 {
1971
1924
compatible = "qcom,sm6350-pdc", "qcom,pdc";
1972
1925
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
···
2261
1780
interrupt-controller;
2262
1781
#interrupt-cells = <2>;
2263
1782
gpio-ranges = <&tlmm 0 0 157>;
1783
+
wakeup-parent = <&pdc>;
2264
1784
2265
1785
cci0_default: cci0-default-state {
2266
1786
pins = "gpio39", "gpio40";
+179
-48
arch/arm64/boot/dts/qcom/sm6375.dtsi
+179
-48
arch/arm64/boot/dts/qcom/sm6375.dtsi
···
8
8
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9
9
#include <dt-bindings/dma/qcom-gpi.h>
10
10
#include <dt-bindings/firmware/qcom,scm.h>
11
+
#include <dt-bindings/interconnect/qcom,osm-l3.h>
11
12
#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13
#include <dt-bindings/mailbox/qcom-ipcc.h>
13
14
#include <dt-bindings/power/qcom-rpmpd.h>
···
46
45
enable-method = "psci";
47
46
next-level-cache = <&L2_0>;
48
47
qcom,freq-domain = <&cpufreq_hw 0>;
48
+
operating-points-v2 = <&cpu0_opp_table>;
49
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
49
50
power-domains = <&CPU_PD0>;
50
51
power-domain-names = "psci";
51
52
#cooling-cells = <2>;
···
72
69
enable-method = "psci";
73
70
next-level-cache = <&L2_100>;
74
71
qcom,freq-domain = <&cpufreq_hw 0>;
72
+
operating-points-v2 = <&cpu0_opp_table>;
73
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
75
74
power-domains = <&CPU_PD1>;
76
75
power-domain-names = "psci";
77
76
#cooling-cells = <2>;
···
93
88
enable-method = "psci";
94
89
next-level-cache = <&L2_200>;
95
90
qcom,freq-domain = <&cpufreq_hw 0>;
91
+
operating-points-v2 = <&cpu0_opp_table>;
92
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
96
93
power-domains = <&CPU_PD2>;
97
94
power-domain-names = "psci";
98
95
#cooling-cells = <2>;
···
114
107
enable-method = "psci";
115
108
next-level-cache = <&L2_300>;
116
109
qcom,freq-domain = <&cpufreq_hw 0>;
110
+
operating-points-v2 = <&cpu0_opp_table>;
111
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
117
112
power-domains = <&CPU_PD3>;
118
113
power-domain-names = "psci";
119
114
#cooling-cells = <2>;
···
135
126
enable-method = "psci";
136
127
next-level-cache = <&L2_400>;
137
128
qcom,freq-domain = <&cpufreq_hw 0>;
129
+
operating-points-v2 = <&cpu0_opp_table>;
130
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
138
131
power-domains = <&CPU_PD4>;
139
132
power-domain-names = "psci";
140
133
#cooling-cells = <2>;
···
156
145
enable-method = "psci";
157
146
next-level-cache = <&L2_500>;
158
147
qcom,freq-domain = <&cpufreq_hw 0>;
148
+
operating-points-v2 = <&cpu0_opp_table>;
149
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
159
150
power-domains = <&CPU_PD5>;
160
151
power-domain-names = "psci";
161
152
#cooling-cells = <2>;
···
177
164
enable-method = "psci";
178
165
next-level-cache = <&L2_600>;
179
166
qcom,freq-domain = <&cpufreq_hw 1>;
167
+
operating-points-v2 = <&cpu6_opp_table>;
168
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
180
169
power-domains = <&CPU_PD6>;
181
170
power-domain-names = "psci";
182
171
#cooling-cells = <2>;
···
198
183
enable-method = "psci";
199
184
next-level-cache = <&L2_700>;
200
185
qcom,freq-domain = <&cpufreq_hw 1>;
186
+
operating-points-v2 = <&cpu6_opp_table>;
187
+
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
201
188
power-domains = <&CPU_PD7>;
202
189
power-domain-names = "psci";
203
190
#cooling-cells = <2>;
···
315
298
device_type = "memory";
316
299
/* We expect the bootloader to fill in the size */
317
300
reg = <0x0 0x80000000 0x0 0x0>;
301
+
};
302
+
303
+
cpu0_opp_table: opp-table-cpu0 {
304
+
compatible = "operating-points-v2";
305
+
opp-shared;
306
+
307
+
opp-300000000 {
308
+
opp-hz = /bits/ 64 <300000000>;
309
+
opp-peak-kBps = <(300000 * 32)>;
310
+
};
311
+
312
+
opp-576000000 {
313
+
opp-hz = /bits/ 64 <576000000>;
314
+
opp-peak-kBps = <(556800 * 32)>;
315
+
};
316
+
317
+
opp-691200000 {
318
+
opp-hz = /bits/ 64 <691200000>;
319
+
opp-peak-kBps = <(652800 * 32)>;
320
+
};
321
+
322
+
opp-940800000 {
323
+
opp-hz = /bits/ 64 <940800000>;
324
+
opp-peak-kBps = <(921600 * 32)>;
325
+
};
326
+
327
+
opp-1113600000 {
328
+
opp-hz = /bits/ 64 <1113600000>;
329
+
opp-peak-kBps = <(921600 * 32)>;
330
+
};
331
+
332
+
opp-1324800000 {
333
+
opp-hz = /bits/ 64 <1324800000>;
334
+
opp-peak-kBps = <(1171200 * 32)>;
335
+
};
336
+
337
+
opp-1516800000 {
338
+
opp-hz = /bits/ 64 <1516800000>;
339
+
opp-peak-kBps = <(1497600 * 32)>;
340
+
};
341
+
342
+
opp-1651200000 {
343
+
opp-hz = /bits/ 64 <1651200000>;
344
+
opp-peak-kBps = <(1497600 * 32)>;
345
+
};
346
+
347
+
opp-1708800000 {
348
+
opp-hz = /bits/ 64 <1708800000>;
349
+
opp-peak-kBps = <(1497600 * 32)>;
350
+
};
351
+
352
+
opp-1804800000 {
353
+
opp-hz = /bits/ 64 <1804800000>;
354
+
opp-peak-kBps = <(1497600 * 32)>;
355
+
};
356
+
};
357
+
358
+
cpu6_opp_table: opp-table-cpu6 {
359
+
compatible = "operating-points-v2";
360
+
opp-shared;
361
+
362
+
opp-691200000 {
363
+
opp-hz = /bits/ 64 <691200000>;
364
+
opp-peak-kBps = <(556800 * 32)>;
365
+
};
366
+
367
+
opp-940800000 {
368
+
opp-hz = /bits/ 64 <940800000>;
369
+
opp-peak-kBps = <(921600 * 32)>;
370
+
};
371
+
372
+
opp-1228800000 {
373
+
opp-hz = /bits/ 64 <1228800000>;
374
+
opp-peak-kBps = <(1171200 * 32)>;
375
+
};
376
+
377
+
opp-1401600000 {
378
+
opp-hz = /bits/ 64 <1401600000>;
379
+
opp-peak-kBps = <(1382400 * 32)>;
380
+
};
381
+
382
+
opp-1516800000 {
383
+
opp-hz = /bits/ 64 <1516800000>;
384
+
opp-peak-kBps = <(1497600 * 32)>;
385
+
};
386
+
387
+
opp-1651200000 {
388
+
opp-hz = /bits/ 64 <1651200000>;
389
+
opp-peak-kBps = <(1497600 * 32)>;
390
+
};
391
+
392
+
opp-1804800000 {
393
+
opp-hz = /bits/ 64 <1804800000>;
394
+
opp-peak-kBps = <(1497600 * 32)>;
395
+
};
396
+
397
+
opp-1900800000 {
398
+
opp-hz = /bits/ 64 <1900800000>;
399
+
opp-peak-kBps = <(1497600 * 32)>;
400
+
};
401
+
402
+
opp-2054400000 {
403
+
opp-hz = /bits/ 64 <2054400000>;
404
+
opp-peak-kBps = <(1497600 * 32)>;
405
+
};
406
+
407
+
opp-2208000000 {
408
+
opp-hz = /bits/ 64 <2208000000>;
409
+
opp-peak-kBps = <(1497600 * 32)>;
410
+
};
318
411
};
319
412
320
413
pmu {
···
621
494
};
622
495
};
623
496
624
-
rpm-glink {
625
-
compatible = "qcom,glink-rpm";
626
-
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
627
-
IPCC_MPROC_SIGNAL_GLINK_QMP
628
-
IRQ_TYPE_EDGE_RISING>;
629
-
qcom,rpm-msg-ram = <&rpm_msg_ram>;
630
-
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
497
+
rpm: remoteproc {
498
+
compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc";
631
499
632
-
rpm_requests: rpm-requests {
633
-
compatible = "qcom,rpm-sm6375";
634
-
qcom,glink-channels = "rpm_requests";
500
+
glink-edge {
501
+
compatible = "qcom,glink-rpm";
502
+
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
503
+
IPCC_MPROC_SIGNAL_GLINK_QMP
504
+
IRQ_TYPE_EDGE_RISING>;
505
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
506
+
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
635
507
636
-
rpmcc: clock-controller {
637
-
compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
638
-
clocks = <&xo_board_clk>;
639
-
clock-names = "xo";
640
-
#clock-cells = <1>;
641
-
};
508
+
rpm_requests: rpm-requests {
509
+
compatible = "qcom,rpm-sm6375";
510
+
qcom,glink-channels = "rpm_requests";
642
511
643
-
rpmpd: power-controller {
644
-
compatible = "qcom,sm6375-rpmpd";
645
-
#power-domain-cells = <1>;
646
-
operating-points-v2 = <&rpmpd_opp_table>;
512
+
rpmcc: clock-controller {
513
+
compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
514
+
clocks = <&xo_board_clk>;
515
+
clock-names = "xo";
516
+
#clock-cells = <1>;
517
+
};
647
518
648
-
rpmpd_opp_table: opp-table {
649
-
compatible = "operating-points-v2";
519
+
rpmpd: power-controller {
520
+
compatible = "qcom,sm6375-rpmpd";
521
+
#power-domain-cells = <1>;
522
+
operating-points-v2 = <&rpmpd_opp_table>;
650
523
651
-
rpmpd_opp_ret: opp1 {
652
-
opp-level = <RPM_SMD_LEVEL_RETENTION>;
653
-
};
524
+
rpmpd_opp_table: opp-table {
525
+
compatible = "operating-points-v2";
654
526
655
-
rpmpd_opp_min_svs: opp2 {
656
-
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
657
-
};
527
+
rpmpd_opp_ret: opp1 {
528
+
opp-level = <RPM_SMD_LEVEL_RETENTION>;
529
+
};
658
530
659
-
rpmpd_opp_low_svs: opp3 {
660
-
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
661
-
};
531
+
rpmpd_opp_min_svs: opp2 {
532
+
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
533
+
};
662
534
663
-
rpmpd_opp_svs: opp4 {
664
-
opp-level = <RPM_SMD_LEVEL_SVS>;
665
-
};
535
+
rpmpd_opp_low_svs: opp3 {
536
+
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
537
+
};
666
538
667
-
rpmpd_opp_svs_plus: opp5 {
668
-
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
669
-
};
539
+
rpmpd_opp_svs: opp4 {
540
+
opp-level = <RPM_SMD_LEVEL_SVS>;
541
+
};
670
542
671
-
rpmpd_opp_nom: opp6 {
672
-
opp-level = <RPM_SMD_LEVEL_NOM>;
673
-
};
543
+
rpmpd_opp_svs_plus: opp5 {
544
+
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
545
+
};
674
546
675
-
rpmpd_opp_nom_plus: opp7 {
676
-
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
677
-
};
547
+
rpmpd_opp_nom: opp6 {
548
+
opp-level = <RPM_SMD_LEVEL_NOM>;
549
+
};
678
550
679
-
rpmpd_opp_turbo: opp8 {
680
-
opp-level = <RPM_SMD_LEVEL_TURBO>;
681
-
};
551
+
rpmpd_opp_nom_plus: opp7 {
552
+
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
553
+
};
682
554
683
-
rpmpd_opp_turbo_no_cpr: opp9 {
684
-
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
555
+
rpmpd_opp_turbo: opp8 {
556
+
opp-level = <RPM_SMD_LEVEL_TURBO>;
557
+
};
558
+
559
+
rpmpd_opp_turbo_no_cpr: opp9 {
560
+
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
561
+
};
685
562
};
686
563
};
687
564
};
+3
-3
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+3
-3
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
···
476
476
};
477
477
478
478
&pm7250b_adc {
479
-
adc-chan@4d {
479
+
channel@4d {
480
480
reg = <ADC5_AMUX_THM1_100K_PU>;
481
481
qcom,ratiometric;
482
482
qcom,hw-settle-time = <200>;
···
484
484
label = "charger_skin_therm";
485
485
};
486
486
487
-
adc-chan@4f {
487
+
channel@4f {
488
488
reg = <ADC5_AMUX_THM3_100K_PU>;
489
489
qcom,ratiometric;
490
490
qcom,hw-settle-time = <200>;
···
516
516
};
517
517
518
518
&pmk8350_vadc {
519
-
adc-chan@644 {
519
+
channel@644 {
520
520
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
521
521
qcom,ratiometric;
522
522
qcom,hw-settle-time = <200>;
+1
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+1
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+1
arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+1
arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+1
-1
arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
+3
-3
arch/arm64/boot/dts/qcom/sm8150.dtsi
+3
-3
arch/arm64/boot/dts/qcom/sm8150.dtsi
···
1231
1231
dma-names = "tx", "rx";
1232
1232
pinctrl-names = "default";
1233
1233
pinctrl-0 = <&qup_i2c7_default>;
1234
-
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1234
+
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1235
1235
#address-cells = <1>;
1236
1236
#size-cells = <0>;
1237
1237
status = "disabled";
···
3840
3840
};
3841
3841
3842
3842
mdss_dsi0_phy: phy@ae94400 {
3843
-
compatible = "qcom,dsi-phy-7nm";
3843
+
compatible = "qcom,dsi-phy-7nm-8150";
3844
3844
reg = <0 0x0ae94400 0 0x200>,
3845
3845
<0 0x0ae94600 0 0x280>,
3846
3846
<0 0x0ae94900 0 0x260>;
···
3914
3914
};
3915
3915
3916
3916
mdss_dsi1_phy: phy@ae96400 {
3917
-
compatible = "qcom,dsi-phy-7nm";
3917
+
compatible = "qcom,dsi-phy-7nm-8150";
3918
3918
reg = <0 0x0ae96400 0 0x200>,
3919
3919
<0 0x0ae96600 0 0x280>,
3920
3920
<0 0x0ae96900 0 0x260>;
+1
arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+1
arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+15
-7
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+15
-7
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
···
18
18
/ {
19
19
model = "Qualcomm Technologies, Inc. SM8250 MTP";
20
20
compatible = "qcom,sm8250-mtp", "qcom,sm8250";
21
+
chassis-type = "handset";
21
22
22
23
aliases {
23
24
serial0 = &uart12;
···
526
525
};
527
526
528
527
&pm8150_adc {
529
-
xo-therm@4c {
528
+
channel@4c {
530
529
reg = <ADC5_XO_THERM_100K_PU>;
531
530
qcom,ratiometric;
532
531
qcom,hw-settle-time = <200>;
532
+
label = "xo_therm";
533
533
};
534
534
535
-
skin-therm@4d {
535
+
channel@4d {
536
536
reg = <ADC5_AMUX_THM1_100K_PU>;
537
537
qcom,ratiometric;
538
538
qcom,hw-settle-time = <200>;
539
+
label = "skin_therm";
539
540
};
540
541
541
-
pa-therm1@4e {
542
+
channel@4e {
542
543
reg = <ADC5_AMUX_THM2_100K_PU>;
543
544
qcom,ratiometric;
544
545
qcom,hw-settle-time = <200>;
546
+
label = "pa_therm1";
545
547
};
546
548
};
547
549
···
574
570
};
575
571
576
572
&pm8150b_adc {
577
-
conn-therm@4f {
573
+
channel@4f {
578
574
reg = <ADC5_AMUX_THM3_100K_PU>;
579
575
qcom,ratiometric;
580
576
qcom,hw-settle-time = <200>;
577
+
label = "conn_therm";
581
578
};
582
579
};
583
580
···
619
614
};
620
615
621
616
&pm8150l_adc {
622
-
camera-flash-therm@4d {
617
+
channel@4d {
623
618
reg = <ADC5_AMUX_THM1_100K_PU>;
624
619
qcom,ratiometric;
625
620
qcom,hw-settle-time = <200>;
621
+
label = "camera_flash_therm";
626
622
};
627
623
628
-
skin-msm-therm@4e {
624
+
channel@4e {
629
625
reg = <ADC5_AMUX_THM2_100K_PU>;
630
626
qcom,ratiometric;
631
627
qcom,hw-settle-time = <200>;
628
+
label = "skin_msm_therm";
632
629
};
633
630
634
-
pa-therm2@4f {
631
+
channel@4f {
635
632
reg = <ADC5_AMUX_THM3_100K_PU>;
636
633
qcom,ratiometric;
637
634
qcom,hw-settle-time = <200>;
635
+
label = "pa_therm2";
638
636
};
639
637
};
640
638
+366
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts
+366
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts
···
14
14
};
15
15
16
16
/delete-node/ &vreg_l7f_1p8;
17
+
18
+
&i2c5 {
19
+
clock-frequency = <400000>;
20
+
status = "okay";
21
+
22
+
pmic@75 {
23
+
compatible = "dlg,slg51000";
24
+
reg = <0x75>;
25
+
dlg,cs-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
26
+
vin5-supply = <&vreg_s1f_1p2>;
27
+
vin6-supply = <&vreg_s1f_1p2>;
28
+
29
+
pinctrl-0 = <&cam_pwr_b_cs>;
30
+
pinctrl-names = "default";
31
+
32
+
regulators {
33
+
slg51000_1_ldo1: ldo1 {
34
+
regulator-name = "slg51000_b_ldo1";
35
+
regulator-min-microvolt = <2400000>;
36
+
regulator-max-microvolt = <3300000>;
37
+
};
38
+
39
+
slg51000_1_ldo2: ldo2 {
40
+
regulator-name = "slg51000_b_ldo2";
41
+
regulator-min-microvolt = <2400000>;
42
+
regulator-max-microvolt = <3300000>;
43
+
};
44
+
45
+
slg51000_1_ldo3: ldo3 {
46
+
regulator-name = "slg51000_b_ldo3";
47
+
regulator-min-microvolt = <1200000>;
48
+
regulator-max-microvolt = <3750000>;
49
+
};
50
+
51
+
slg51000_1_ldo4: ldo4 {
52
+
regulator-name = "slg51000_b_ldo4";
53
+
regulator-min-microvolt = <1200000>;
54
+
regulator-max-microvolt = <3750000>;
55
+
};
56
+
57
+
slg51000_1_ldo5: ldo5 {
58
+
regulator-name = "slg51000_b_ldo5";
59
+
regulator-min-microvolt = <500000>;
60
+
regulator-max-microvolt = <1200000>;
61
+
};
62
+
63
+
slg51000_1_ldo6: ldo6 {
64
+
regulator-name = "slg51000_b_ldo6";
65
+
regulator-min-microvolt = <500000>;
66
+
regulator-max-microvolt = <1200000>;
67
+
};
68
+
69
+
slg51000_1_ldo7: ldo7 {
70
+
regulator-name = "slg51000_b_ldo7";
71
+
regulator-min-microvolt = <1200000>;
72
+
regulator-max-microvolt = <3750000>;
73
+
};
74
+
};
75
+
};
76
+
};
77
+
78
+
&i2c15 {
79
+
pmic@75 {
80
+
compatible = "dlg,slg51000";
81
+
reg = <0x75>;
82
+
dlg,cs-gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>;
83
+
vin5-supply = <&vreg_l2f_1p3>;
84
+
vin6-supply = <&vreg_l2f_1p3>;
85
+
86
+
pinctrl-0 = <&cam_pwr_a_cs>;
87
+
pinctrl-names = "default";
88
+
89
+
regulators {
90
+
slg51000_0_ldo1: ldo1 {
91
+
regulator-name = "slg51000_a_ldo1";
92
+
regulator-min-microvolt = <2400000>;
93
+
regulator-max-microvolt = <3300000>;
94
+
};
95
+
96
+
slg51000_0_ldo2: ldo2 {
97
+
regulator-name = "slg51000_a_ldo2";
98
+
regulator-min-microvolt = <2400000>;
99
+
regulator-max-microvolt = <3300000>;
100
+
};
101
+
102
+
slg51000_0_ldo3: ldo3 {
103
+
regulator-name = "slg51000_a_ldo3";
104
+
regulator-min-microvolt = <1200000>;
105
+
regulator-max-microvolt = <3750000>;
106
+
};
107
+
108
+
slg51000_0_ldo4: ldo4 {
109
+
regulator-name = "slg51000_a_ldo4";
110
+
regulator-min-microvolt = <1200000>;
111
+
regulator-max-microvolt = <3750000>;
112
+
};
113
+
114
+
slg51000_0_ldo5: ldo5 {
115
+
regulator-name = "slg51000_a_ldo5";
116
+
regulator-min-microvolt = <500000>;
117
+
regulator-max-microvolt = <1200000>;
118
+
};
119
+
120
+
slg51000_0_ldo6: ldo6 {
121
+
regulator-name = "slg51000_a_ldo6";
122
+
regulator-min-microvolt = <500000>;
123
+
regulator-max-microvolt = <1200000>;
124
+
};
125
+
126
+
slg51000_0_ldo7: ldo7 {
127
+
regulator-name = "slg51000_a_ldo7";
128
+
regulator-min-microvolt = <1200000>;
129
+
regulator-max-microvolt = <3750000>;
130
+
};
131
+
};
132
+
};
133
+
};
134
+
135
+
&pm8009_gpios {
136
+
gpio-line-names = "NC", /* GPIO_1 */
137
+
"CAM_PWR_LD_EN",
138
+
"WIDEC_PWR_EN",
139
+
"NC";
140
+
};
141
+
142
+
&pm8150_gpios {
143
+
gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */
144
+
"OPTION_2",
145
+
"NC",
146
+
"PM_SLP_CLK_IN",
147
+
"OPTION_1",
148
+
"NC",
149
+
"NC",
150
+
"SP_ARI_PWR_ALARM",
151
+
"NC",
152
+
"NC"; /* GPIO_10 */
153
+
};
154
+
155
+
&pm8150b_gpios {
156
+
gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */
157
+
"FOCUS_N",
158
+
"NC",
159
+
"NC",
160
+
"RF_LCD_ID_EN",
161
+
"NC",
162
+
"NC",
163
+
"LCD_ID",
164
+
"NC",
165
+
"WLC_EN_N", /* GPIO_10 */
166
+
"NC",
167
+
"RF_ID";
168
+
};
169
+
170
+
&pm8150l_gpios {
171
+
gpio-line-names = "NC", /* GPIO_1 */
172
+
"PM3003A_EN",
173
+
"NC",
174
+
"NC",
175
+
"NC",
176
+
"AUX2_THERM",
177
+
"BB_HP_EN",
178
+
"FP_LDO_EN",
179
+
"PMX_RESET_N",
180
+
"AUX3_THERM", /* GPIO_10 */
181
+
"DTV_PWR_EN",
182
+
"PM3003A_MODE";
183
+
};
184
+
185
+
&tlmm {
186
+
gpio-line-names = "AP_CTI_IN", /* GPIO_0 */
187
+
"MDM2AP_ERR_FATAL",
188
+
"AP_CTI_OUT",
189
+
"MDM2AP_STATUS",
190
+
"NFC_I2C_SDA",
191
+
"NFC_I2C_SCL",
192
+
"NFC_EN",
193
+
"NFC_CLK_REQ",
194
+
"NFC_ESE_PWR_REQ",
195
+
"DVDT_WRT_DET_AND",
196
+
"SPK_AMP_RESET_N", /* GPIO_10 */
197
+
"SPK_AMP_INT_N",
198
+
"APPS_I2C_1_SDA",
199
+
"APPS_I2C_1_SCL",
200
+
"NC",
201
+
"TX_GTR_THRES_IN",
202
+
"HST_BT_UART_CTS",
203
+
"HST_BT_UART_RFR",
204
+
"HST_BT_UART_TX",
205
+
"HST_BT_UART_RX",
206
+
"HST_WLAN_EN", /* GPIO_20 */
207
+
"HST_BT_EN",
208
+
"RGBC_IR_PWR_EN",
209
+
"FP_INT_N",
210
+
"NC",
211
+
"NC",
212
+
"NC",
213
+
"NC",
214
+
"NFC_ESE_SPI_MISO",
215
+
"NFC_ESE_SPI_MOSI",
216
+
"NFC_ESE_SPI_SCLK", /* GPIO_30 */
217
+
"NFC_ESE_SPI_CS_N",
218
+
"WCD_RST_N",
219
+
"NC",
220
+
"SDM_DEBUG_UART_TX",
221
+
"SDM_DEBUG_UART_RX",
222
+
"TS_I2C_SDA",
223
+
"TS_I2C_SCL",
224
+
"TS_INT_N",
225
+
"FP_SPI_MISO", /* GPIO_40 */
226
+
"FP_SPI_MOSI",
227
+
"FP_SPI_SCLK",
228
+
"FP_SPI_CS_N",
229
+
"APPS_I2C_0_SDA",
230
+
"APPS_I2C_0_SCL",
231
+
"DISP_ERR_FG",
232
+
"UIM2_DETECT_EN",
233
+
"NC",
234
+
"NC",
235
+
"NC", /* GPIO_50 */
236
+
"NC",
237
+
"MDM_UART_CTS",
238
+
"MDM_UART_RFR",
239
+
"MDM_UART_TX",
240
+
"MDM_UART_RX",
241
+
"AP2MDM_STATUS",
242
+
"AP2MDM_ERR_FATAL",
243
+
"MDM_IPC_HS_UART_TX",
244
+
"MDM_IPC_HS_UART_RX",
245
+
"NC", /* GPIO_60 */
246
+
"NC",
247
+
"NC",
248
+
"NC",
249
+
"NC",
250
+
"USB_CC_DIR",
251
+
"DISP_VSYNC",
252
+
"NC",
253
+
"NC",
254
+
"CAM_PWR_B_CS",
255
+
"NC", /* GPIO_70 */
256
+
"CAM_PWR_A_CS",
257
+
"SBU_SW_SEL",
258
+
"SBU_SW_OE",
259
+
"FP_RESET_N",
260
+
"FP_RESET_N",
261
+
"DISP_RESET_N",
262
+
"DEBUG_GPIO0",
263
+
"TRAY_DET",
264
+
"CAM2_RST_N",
265
+
"PCIE0_RST_N",
266
+
"PCIE0_CLK_REQ_N", /* GPIO_80 */
267
+
"PCIE0_WAKE_N",
268
+
"DVDT_ENABLE",
269
+
"DVDT_WRT_DET_OR",
270
+
"NC",
271
+
"PCIE2_RST_N",
272
+
"PCIE2_CLK_REQ_N",
273
+
"PCIE2_WAKE_N",
274
+
"MDM_VFR_IRQ0",
275
+
"MDM_VFR_IRQ1",
276
+
"SW_SERVICE", /* GPIO_90 */
277
+
"CAM_SOF",
278
+
"CAM1_RST_N",
279
+
"CAM0_RST_N",
280
+
"CAM0_MCLK",
281
+
"CAM1_MCLK",
282
+
"CAM2_MCLK",
283
+
"CAM3_MCLK",
284
+
"CAM4_MCLK",
285
+
"TOF_RST_N",
286
+
"NC", /* GPIO_100 */
287
+
"CCI0_I2C_SDA",
288
+
"CCI0_I2C_SCL",
289
+
"CCI1_I2C_SDA",
290
+
"CCI1_I2C_SCL_",
291
+
"CCI2_I2C_SDA",
292
+
"CCI2_I2C_SCL",
293
+
"CCI3_I2C_SDA",
294
+
"CCI3_I2C_SCL",
295
+
"CAM3_RST_N",
296
+
"NFC_DWL_REQ", /* GPIO_110 */
297
+
"NFC_IRQ",
298
+
"XVS",
299
+
"NC",
300
+
"RF_ID_EXTENSION",
301
+
"SPK_AMP_I2C_SDA",
302
+
"SPK_AMP_I2C_SCL",
303
+
"NC",
304
+
"NC",
305
+
"WLC_I2C_SDA",
306
+
"WLC_I2C_SCL", /* GPIO_120 */
307
+
"ACC_COVER_OPEN",
308
+
"ALS_PROX_INT_N",
309
+
"ACCEL_INT",
310
+
"WLAN_SW_CTRL",
311
+
"CAMSENSOR_I2C_SDA",
312
+
"CAMSENSOR_I2C_SCL",
313
+
"UDON_SWITCH_SEL",
314
+
"WDOG_DISABLE",
315
+
"BAROMETER_INT",
316
+
"NC", /* GPIO_130 */
317
+
"NC",
318
+
"FORCED_USB_BOOT",
319
+
"NC",
320
+
"NC",
321
+
"WLC_INT_N",
322
+
"NC",
323
+
"NC",
324
+
"RGBC_IR_INT",
325
+
"NC",
326
+
"NC", /* GPIO_140 */
327
+
"NC",
328
+
"BT_SLIMBUS_CLK",
329
+
"BT_SLIMBUS_DATA",
330
+
"HW_ID_0",
331
+
"HW_ID_1",
332
+
"WCD_SWR_TX_CLK",
333
+
"WCD_SWR_TX_DATA0",
334
+
"WCD_SWR_TX_DATA1",
335
+
"WCD_SWR_RX_CLK",
336
+
"WCD_SWR_RX_DATA0", /* GPIO_150 */
337
+
"WCD_SWR_RX_DATA1",
338
+
"SDM_DMIC_CLK1",
339
+
"SDM_DMIC_DATA1",
340
+
"SDM_DMIC_CLK2",
341
+
"SDM_DMIC_DATA2",
342
+
"SPK_AMP_I2S_CLK",
343
+
"SPK_AMP_I2S_WS",
344
+
"SPK_AMP_I2S_ASP_DIN",
345
+
"SPK_AMP_I2S_ASP_DOUT",
346
+
"COMPASS_I2C_SDA", /* GPIO_160 */
347
+
"COMPASS_I2C_SCL",
348
+
"NC",
349
+
"NC",
350
+
"SSC_SPI_1_MISO",
351
+
"SSC_SPI_1_MOSI",
352
+
"SSC_SPI_1_CLK",
353
+
"SSC_SPI_1_CS_N",
354
+
"NC",
355
+
"NC",
356
+
"SSC_SENSOR_I2C_SDA", /* GPIO_170 */
357
+
"SSC_SENSOR_I2C_SCL",
358
+
"NC",
359
+
"NC",
360
+
"NC",
361
+
"NC",
362
+
"HST_BLE_SNS_UART6_TX",
363
+
"HST_BLE_SNS_UART6_RX",
364
+
"HST_WLAN_UART_TX",
365
+
"HST_WLAN_UART_RX";
366
+
367
+
cam_pwr_b_cs: cam-pwr-b-state {
368
+
pins = "gpio69";
369
+
function = "gpio";
370
+
drive-strength = <2>;
371
+
bias-disable;
372
+
output-low;
373
+
};
374
+
375
+
cam_pwr_a_cs: cam-pwr-a-state {
376
+
pins = "gpio71";
377
+
function = "gpio";
378
+
drive-strength = <2>;
379
+
bias-disable;
380
+
output-low;
381
+
};
382
+
};
+243
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
+243
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
···
20
20
};
21
21
22
22
&gpio_keys {
23
+
pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>;
24
+
23
25
g-assist-key {
24
26
label = "Google Assistant Key";
25
27
linux,code = <KEY_LEFTMETA>;
···
30
28
linux,can-disable;
31
29
wakeup-source;
32
30
};
31
+
};
32
+
33
+
&pm8009_gpios {
34
+
gpio-line-names = "NC", /* GPIO_1 */
35
+
"NC",
36
+
"WIDEC_PWR_EN",
37
+
"NC";
38
+
};
39
+
40
+
&pm8150_gpios {
41
+
gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */
42
+
"OPTION_2",
43
+
"NC",
44
+
"PM_SLP_CLK_IN",
45
+
"OPTION_1",
46
+
"G_ASSIST_N",
47
+
"NC",
48
+
"SP_ARI_PWR_ALARM",
49
+
"NC",
50
+
"NC"; /* GPIO_10 */
51
+
52
+
g_assist_n: g-assist-n-state {
53
+
pins = "gpio6";
54
+
function = "normal";
55
+
power-source = <1>;
56
+
bias-pull-up;
57
+
input-enable;
58
+
};
59
+
};
60
+
61
+
&pm8150b_gpios {
62
+
gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */
63
+
"FOCUS_N",
64
+
"NC",
65
+
"NC",
66
+
"RF_LCD_ID_EN",
67
+
"NC",
68
+
"NC",
69
+
"LCD_ID",
70
+
"NC",
71
+
"NC", /* GPIO_10 */
72
+
"NC",
73
+
"RF_ID";
74
+
};
75
+
76
+
&pm8150l_gpios {
77
+
gpio-line-names = "NC", /* GPIO_1 */
78
+
"PM3003A_EN",
79
+
"NC",
80
+
"NC",
81
+
"NC",
82
+
"AUX2_THERM",
83
+
"BB_HP_EN",
84
+
"FP_LDO_EN",
85
+
"PMX_RESET_N",
86
+
"NC", /* GPIO_10 */
87
+
"NC",
88
+
"PM3003A_MODE";
89
+
};
90
+
91
+
&tlmm {
92
+
gpio-line-names = "AP_CTI_IN", /* GPIO_0 */
93
+
"MDM2AP_ERR_FATAL",
94
+
"AP_CTI_OUT",
95
+
"MDM2AP_STATUS",
96
+
"NFC_I2C_SDA",
97
+
"NFC_I2C_SCL",
98
+
"NFC_EN",
99
+
"NFC_CLK_REQ",
100
+
"NFC_ESE_PWR_REQ",
101
+
"DVDT_WRT_DET_AND",
102
+
"SPK_AMP_RESET_N", /* GPIO_10 */
103
+
"SPK_AMP_INT_N",
104
+
"APPS_I2C_1_SDA",
105
+
"APPS_I2C_1_SCL",
106
+
"NC",
107
+
"TX_GTR_THRES_IN",
108
+
"HST_BT_UART_CTS",
109
+
"HST_BT_UART_RFR",
110
+
"HST_BT_UART_TX",
111
+
"HST_BT_UART_RX",
112
+
"HST_WLAN_EN", /* GPIO_20 */
113
+
"HST_BT_EN",
114
+
"RGBC_IR_PWR_EN",
115
+
"FP_INT_N",
116
+
"NC",
117
+
"NC",
118
+
"NC",
119
+
"NC",
120
+
"NFC_ESE_SPI_MISO",
121
+
"NFC_ESE_SPI_MOSI",
122
+
"NFC_ESE_SPI_SCLK", /* GPIO_30 */
123
+
"NFC_ESE_SPI_CS_N",
124
+
"WCD_RST_N",
125
+
"NC",
126
+
"SDM_DEBUG_UART_TX",
127
+
"SDM_DEBUG_UART_RX",
128
+
"TS_I2C_SDA",
129
+
"TS_I2C_SCL",
130
+
"TS_INT_N",
131
+
"FP_SPI_MISO", /* GPIO_40 */
132
+
"FP_SPI_MOSI",
133
+
"FP_SPI_SCLK",
134
+
"FP_SPI_CS_N",
135
+
"APPS_I2C_0_SDA",
136
+
"APPS_I2C_0_SCL",
137
+
"DISP_ERR_FG",
138
+
"UIM2_DETECT_EN",
139
+
"NC",
140
+
"NC",
141
+
"NC", /* GPIO_50 */
142
+
"NC",
143
+
"MDM_UART_CTS",
144
+
"MDM_UART_RFR",
145
+
"MDM_UART_TX",
146
+
"MDM_UART_RX",
147
+
"AP2MDM_STATUS",
148
+
"AP2MDM_ERR_FATAL",
149
+
"MDM_IPC_HS_UART_TX",
150
+
"MDM_IPC_HS_UART_RX",
151
+
"NC", /* GPIO_60 */
152
+
"NC",
153
+
"NC",
154
+
"NC",
155
+
"NC",
156
+
"USB_CC_DIR",
157
+
"DISP_VSYNC",
158
+
"NC",
159
+
"NC",
160
+
"CAM_PWR_B_CS",
161
+
"NC", /* GPIO_70 */
162
+
"FRONTC_PWR_EN",
163
+
"SBU_SW_SEL",
164
+
"SBU_SW_OE",
165
+
"FP_RESET_N",
166
+
"FP_RESET_N",
167
+
"DISP_RESET_N",
168
+
"DEBUG_GPIO0",
169
+
"TRAY_DET",
170
+
"CAM2_RST_N",
171
+
"PCIE0_RST_N",
172
+
"PCIE0_CLK_REQ_N", /* GPIO_80 */
173
+
"PCIE0_WAKE_N",
174
+
"DVDT_ENABLE",
175
+
"DVDT_WRT_DET_OR",
176
+
"NC",
177
+
"PCIE2_RST_N",
178
+
"PCIE2_CLK_REQ_N",
179
+
"PCIE2_WAKE_N",
180
+
"MDM_VFR_IRQ0",
181
+
"MDM_VFR_IRQ1",
182
+
"SW_SERVICE", /* GPIO_90 */
183
+
"CAM_SOF",
184
+
"CAM1_RST_N",
185
+
"CAM0_RST_N",
186
+
"CAM0_MCLK",
187
+
"CAM1_MCLK",
188
+
"CAM2_MCLK",
189
+
"CAM3_MCLK",
190
+
"NC",
191
+
"NC",
192
+
"NC", /* GPIO_100 */
193
+
"CCI0_I2C_SDA",
194
+
"CCI0_I2C_SCL",
195
+
"CCI1_I2C_SDA",
196
+
"CCI1_I2C_SCL_",
197
+
"CCI2_I2C_SDA",
198
+
"CCI2_I2C_SCL",
199
+
"CCI3_I2C_SDA",
200
+
"CCI3_I2C_SCL",
201
+
"CAM3_RST_N",
202
+
"NFC_DWL_REQ", /* GPIO_110 */
203
+
"NFC_IRQ",
204
+
"XVS",
205
+
"NC",
206
+
"RF_ID_EXTENSION",
207
+
"SPK_AMP_I2C_SDA",
208
+
"SPK_AMP_I2C_SCL",
209
+
"NC",
210
+
"NC",
211
+
"NC",
212
+
"NC",
213
+
"ACC_COVER_OPEN",
214
+
"ALS_PROX_INT_N",
215
+
"ACCEL_INT",
216
+
"WLAN_SW_CTRL",
217
+
"CAMSENSOR_I2C_SDA",
218
+
"CAMSENSOR_I2C_SCL",
219
+
"UDON_SWITCH_SEL",
220
+
"WDOG_DISABLE",
221
+
"BAROMETER_INT",
222
+
"NC", /* GPIO_130 */
223
+
"NC",
224
+
"FORCED_USB_BOOT",
225
+
"NC",
226
+
"NC",
227
+
"NC",
228
+
"NC",
229
+
"NC",
230
+
"RGBC_IR_INT",
231
+
"NC",
232
+
"NC", /* GPIO_140 */
233
+
"NC",
234
+
"BT_SLIMBUS_CLK",
235
+
"BT_SLIMBUS_DATA",
236
+
"HW_ID_0",
237
+
"HW_ID_1",
238
+
"WCD_SWR_TX_CLK",
239
+
"WCD_SWR_TX_DATA0",
240
+
"WCD_SWR_TX_DATA1",
241
+
"WCD_SWR_RX_CLK",
242
+
"WCD_SWR_RX_DATA0", /* GPIO_150 */
243
+
"WCD_SWR_RX_DATA1",
244
+
"SDM_DMIC_CLK1",
245
+
"SDM_DMIC_DATA1",
246
+
"SDM_DMIC_CLK2",
247
+
"SDM_DMIC_DATA2",
248
+
"SPK_AMP_I2S_CLK",
249
+
"SPK_AMP_I2S_WS",
250
+
"SPK_AMP_I2S_ASP_DIN",
251
+
"SPK_AMP_I2S_ASP_DOUT",
252
+
"COMPASS_I2C_SDA", /* GPIO_160 */
253
+
"COMPASS_I2C_SCL",
254
+
"NC",
255
+
"NC",
256
+
"SSC_SPI_1_MISO",
257
+
"SSC_SPI_1_MOSI",
258
+
"SSC_SPI_1_CLK",
259
+
"SSC_SPI_1_CS_N",
260
+
"NC",
261
+
"NC",
262
+
"SSC_SENSOR_I2C_SDA", /* GPIO_170 */
263
+
"SSC_SENSOR_I2C_SCL",
264
+
"NC",
265
+
"NC",
266
+
"NC",
267
+
"NC",
268
+
"HST_BLE_SNS_UART6_TX",
269
+
"HST_BLE_SNS_UART6_RX",
270
+
"HST_WLAN_UART_TX",
271
+
"HST_WLAN_UART_RX";
33
272
};
34
273
35
274
&vreg_l2f_1p3 {
+49
-14
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
+49
-14
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
···
51
51
gpio_keys: gpio-keys {
52
52
compatible = "gpio-keys";
53
53
54
-
/*
55
-
* Camera focus (light press) and camera snapshot (full press)
56
-
* seem not to work properly.. Adding the former one stalls the CPU
57
-
* and the latter kills the volume down key for whatever reason. In any
58
-
* case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1).
59
-
*/
54
+
pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>;
55
+
pinctrl-names = "default";
56
+
57
+
key-camera-focus {
58
+
label = "Camera Focus";
59
+
linux,code = <KEY_CAMERA_FOCUS>;
60
+
gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>;
61
+
debounce-interval = <15>;
62
+
linux,can-disable;
63
+
wakeup-source;
64
+
};
65
+
66
+
key-camera-snapshot {
67
+
label = "Camera Snapshot";
68
+
linux,code = <KEY_CAMERA>;
69
+
gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>;
70
+
debounce-interval = <15>;
71
+
linux,can-disable;
72
+
wakeup-source;
73
+
};
60
74
61
75
key-vol-down {
62
76
label = "Volume Down";
···
126
112
reg = <0x0 0xffc00000 0x0 0x100000>;
127
113
record-size = <0x1000>;
128
114
console-size = <0x40000>;
129
-
msg-size = <0x20000 0x20000>;
115
+
pmsg-size = <0x20000>;
130
116
ecc-size = <16>;
131
117
no-map;
132
118
};
···
500
486
};
501
487
};
502
488
503
-
&i2c5 {
504
-
status = "okay";
505
-
clock-frequency = <400000>;
506
-
507
-
/* Dialog SLG51000 CMIC @ 75 */
508
-
};
509
-
510
489
&i2c9 {
511
490
status = "okay";
512
491
clock-frequency = <400000>;
···
556
549
557
550
vdda-phy-supply = <&vreg_l5a_0p88>;
558
551
vdda-pll-supply = <&vreg_l9a_1p2>;
552
+
};
553
+
554
+
&pm8150_gpios {
555
+
vol_down_n: vol-down-n-state {
556
+
pins = "gpio1";
557
+
function = "normal";
558
+
power-source = <0>;
559
+
bias-pull-up;
560
+
input-enable;
561
+
};
562
+
};
563
+
564
+
&pm8150b_gpios {
565
+
snapshot_n: snapshot-n-state {
566
+
pins = "gpio1";
567
+
function = "normal";
568
+
power-source = <0>;
569
+
bias-pull-up;
570
+
input-enable;
571
+
};
572
+
573
+
focus_n: focus-n-state {
574
+
pins = "gpio2";
575
+
function = "normal";
576
+
power-source = <0>;
577
+
bias-pull-up;
578
+
input-enable;
579
+
};
559
580
};
560
581
561
582
&pon_pwrkey {
+1
-1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
+273
-141
arch/arm64/boot/dts/qcom/sm8250.dtsi
+273
-141
arch/arm64/boot/dts/qcom/sm8250.dtsi
···
16
16
#include <dt-bindings/interconnect/qcom,sm8250.h>
17
17
#include <dt-bindings/mailbox/qcom-ipcc.h>
18
18
#include <dt-bindings/power/qcom-rpmpd.h>
19
+
#include <dt-bindings/power/qcom,rpmhpd.h>
19
20
#include <dt-bindings/soc/qcom,apr.h>
20
21
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
21
22
#include <dt-bindings/sound/qcom,q6afe.h>
···
101
100
clocks = <&cpufreq_hw 0>;
102
101
enable-method = "psci";
103
102
capacity-dmips-mhz = <448>;
104
-
dynamic-power-coefficient = <205>;
103
+
dynamic-power-coefficient = <105>;
105
104
next-level-cache = <&L2_0>;
106
105
power-domains = <&CPU_PD0>;
107
106
power-domain-names = "psci";
···
132
131
clocks = <&cpufreq_hw 0>;
133
132
enable-method = "psci";
134
133
capacity-dmips-mhz = <448>;
135
-
dynamic-power-coefficient = <205>;
134
+
dynamic-power-coefficient = <105>;
136
135
next-level-cache = <&L2_100>;
137
136
power-domains = <&CPU_PD1>;
138
137
power-domain-names = "psci";
···
157
156
clocks = <&cpufreq_hw 0>;
158
157
enable-method = "psci";
159
158
capacity-dmips-mhz = <448>;
160
-
dynamic-power-coefficient = <205>;
159
+
dynamic-power-coefficient = <105>;
161
160
next-level-cache = <&L2_200>;
162
161
power-domains = <&CPU_PD2>;
163
162
power-domain-names = "psci";
···
182
181
clocks = <&cpufreq_hw 0>;
183
182
enable-method = "psci";
184
183
capacity-dmips-mhz = <448>;
185
-
dynamic-power-coefficient = <205>;
184
+
dynamic-power-coefficient = <105>;
186
185
next-level-cache = <&L2_300>;
187
186
power-domains = <&CPU_PD3>;
188
187
power-domain-names = "psci";
···
1037
1036
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1038
1037
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
1039
1038
dma-names = "tx", "rx";
1040
-
power-domains = <&rpmhpd SM8250_CX>;
1039
+
power-domains = <&rpmhpd RPMHPD_CX>;
1041
1040
operating-points-v2 = <&qup_opp_table>;
1042
1041
#address-cells = <1>;
1043
1042
#size-cells = <0>;
···
1069
1068
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1070
1069
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
1071
1070
dma-names = "tx", "rx";
1072
-
power-domains = <&rpmhpd SM8250_CX>;
1071
+
power-domains = <&rpmhpd RPMHPD_CX>;
1073
1072
operating-points-v2 = <&qup_opp_table>;
1074
1073
#address-cells = <1>;
1075
1074
#size-cells = <0>;
···
1101
1100
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1102
1101
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
1103
1102
dma-names = "tx", "rx";
1104
-
power-domains = <&rpmhpd SM8250_CX>;
1103
+
power-domains = <&rpmhpd RPMHPD_CX>;
1105
1104
operating-points-v2 = <&qup_opp_table>;
1106
1105
#address-cells = <1>;
1107
1106
#size-cells = <0>;
···
1133
1132
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1134
1133
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
1135
1134
dma-names = "tx", "rx";
1136
-
power-domains = <&rpmhpd SM8250_CX>;
1135
+
power-domains = <&rpmhpd RPMHPD_CX>;
1137
1136
operating-points-v2 = <&qup_opp_table>;
1138
1137
#address-cells = <1>;
1139
1138
#size-cells = <0>;
···
1148
1147
pinctrl-names = "default";
1149
1148
pinctrl-0 = <&qup_uart17_default>;
1150
1149
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1151
-
power-domains = <&rpmhpd SM8250_CX>;
1150
+
power-domains = <&rpmhpd RPMHPD_CX>;
1152
1151
operating-points-v2 = <&qup_opp_table>;
1153
1152
status = "disabled";
1154
1153
};
···
1178
1177
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1179
1178
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
1180
1179
dma-names = "tx", "rx";
1181
-
power-domains = <&rpmhpd SM8250_CX>;
1180
+
power-domains = <&rpmhpd RPMHPD_CX>;
1182
1181
operating-points-v2 = <&qup_opp_table>;
1183
1182
#address-cells = <1>;
1184
1183
#size-cells = <0>;
···
1193
1192
pinctrl-names = "default";
1194
1193
pinctrl-0 = <&qup_uart18_default>;
1195
1194
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1196
-
power-domains = <&rpmhpd SM8250_CX>;
1195
+
power-domains = <&rpmhpd RPMHPD_CX>;
1197
1196
operating-points-v2 = <&qup_opp_table>;
1198
1197
status = "disabled";
1199
1198
};
···
1223
1222
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1224
1223
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
1225
1224
dma-names = "tx", "rx";
1226
-
power-domains = <&rpmhpd SM8250_CX>;
1225
+
power-domains = <&rpmhpd RPMHPD_CX>;
1227
1226
operating-points-v2 = <&qup_opp_table>;
1228
1227
#address-cells = <1>;
1229
1228
#size-cells = <0>;
···
1291
1290
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1292
1291
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
1293
1292
dma-names = "tx", "rx";
1294
-
power-domains = <&rpmhpd SM8250_CX>;
1293
+
power-domains = <&rpmhpd RPMHPD_CX>;
1295
1294
operating-points-v2 = <&qup_opp_table>;
1296
1295
#address-cells = <1>;
1297
1296
#size-cells = <0>;
···
1323
1322
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1324
1323
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
1325
1324
dma-names = "tx", "rx";
1326
-
power-domains = <&rpmhpd SM8250_CX>;
1325
+
power-domains = <&rpmhpd RPMHPD_CX>;
1327
1326
operating-points-v2 = <&qup_opp_table>;
1328
1327
#address-cells = <1>;
1329
1328
#size-cells = <0>;
···
1355
1354
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1356
1355
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
1357
1356
dma-names = "tx", "rx";
1358
-
power-domains = <&rpmhpd SM8250_CX>;
1357
+
power-domains = <&rpmhpd RPMHPD_CX>;
1359
1358
operating-points-v2 = <&qup_opp_table>;
1360
1359
#address-cells = <1>;
1361
1360
#size-cells = <0>;
···
1370
1369
pinctrl-names = "default";
1371
1370
pinctrl-0 = <&qup_uart2_default>;
1372
1371
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1373
-
power-domains = <&rpmhpd SM8250_CX>;
1372
+
power-domains = <&rpmhpd RPMHPD_CX>;
1374
1373
operating-points-v2 = <&qup_opp_table>;
1375
1374
status = "disabled";
1376
1375
};
···
1400
1399
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1401
1400
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
1402
1401
dma-names = "tx", "rx";
1403
-
power-domains = <&rpmhpd SM8250_CX>;
1402
+
power-domains = <&rpmhpd RPMHPD_CX>;
1404
1403
operating-points-v2 = <&qup_opp_table>;
1405
1404
#address-cells = <1>;
1406
1405
#size-cells = <0>;
···
1432
1431
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1433
1432
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
1434
1433
dma-names = "tx", "rx";
1435
-
power-domains = <&rpmhpd SM8250_CX>;
1434
+
power-domains = <&rpmhpd RPMHPD_CX>;
1436
1435
operating-points-v2 = <&qup_opp_table>;
1437
1436
#address-cells = <1>;
1438
1437
#size-cells = <0>;
···
1464
1463
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1465
1464
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
1466
1465
dma-names = "tx", "rx";
1467
-
power-domains = <&rpmhpd SM8250_CX>;
1466
+
power-domains = <&rpmhpd RPMHPD_CX>;
1468
1467
operating-points-v2 = <&qup_opp_table>;
1469
1468
#address-cells = <1>;
1470
1469
#size-cells = <0>;
···
1496
1495
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1497
1496
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
1498
1497
dma-names = "tx", "rx";
1499
-
power-domains = <&rpmhpd SM8250_CX>;
1498
+
power-domains = <&rpmhpd RPMHPD_CX>;
1500
1499
operating-points-v2 = <&qup_opp_table>;
1501
1500
#address-cells = <1>;
1502
1501
#size-cells = <0>;
···
1511
1510
pinctrl-names = "default";
1512
1511
pinctrl-0 = <&qup_uart6_default>;
1513
1512
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1514
-
power-domains = <&rpmhpd SM8250_CX>;
1513
+
power-domains = <&rpmhpd RPMHPD_CX>;
1515
1514
operating-points-v2 = <&qup_opp_table>;
1516
1515
status = "disabled";
1517
1516
};
···
1541
1540
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1542
1541
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
1543
1542
dma-names = "tx", "rx";
1544
-
power-domains = <&rpmhpd SM8250_CX>;
1543
+
power-domains = <&rpmhpd RPMHPD_CX>;
1545
1544
operating-points-v2 = <&qup_opp_table>;
1546
1545
#address-cells = <1>;
1547
1546
#size-cells = <0>;
···
1606
1605
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1607
1606
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
1608
1607
dma-names = "tx", "rx";
1609
-
power-domains = <&rpmhpd SM8250_CX>;
1608
+
power-domains = <&rpmhpd RPMHPD_CX>;
1610
1609
operating-points-v2 = <&qup_opp_table>;
1611
1610
#address-cells = <1>;
1612
1611
#size-cells = <0>;
···
1638
1637
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1639
1638
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
1640
1639
dma-names = "tx", "rx";
1641
-
power-domains = <&rpmhpd SM8250_CX>;
1640
+
power-domains = <&rpmhpd RPMHPD_CX>;
1642
1641
operating-points-v2 = <&qup_opp_table>;
1643
1642
#address-cells = <1>;
1644
1643
#size-cells = <0>;
···
1670
1669
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1671
1670
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
1672
1671
dma-names = "tx", "rx";
1673
-
power-domains = <&rpmhpd SM8250_CX>;
1672
+
power-domains = <&rpmhpd RPMHPD_CX>;
1674
1673
operating-points-v2 = <&qup_opp_table>;
1675
1674
#address-cells = <1>;
1676
1675
#size-cells = <0>;
···
1702
1701
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1703
1702
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
1704
1703
dma-names = "tx", "rx";
1705
-
power-domains = <&rpmhpd SM8250_CX>;
1704
+
power-domains = <&rpmhpd RPMHPD_CX>;
1706
1705
operating-points-v2 = <&qup_opp_table>;
1707
1706
#address-cells = <1>;
1708
1707
#size-cells = <0>;
···
1734
1733
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1735
1734
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
1736
1735
dma-names = "tx", "rx";
1737
-
power-domains = <&rpmhpd SM8250_CX>;
1736
+
power-domains = <&rpmhpd RPMHPD_CX>;
1738
1737
operating-points-v2 = <&qup_opp_table>;
1739
1738
#address-cells = <1>;
1740
1739
#size-cells = <0>;
···
1749
1748
pinctrl-names = "default";
1750
1749
pinctrl-0 = <&qup_uart12_default>;
1751
1750
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1752
-
power-domains = <&rpmhpd SM8250_CX>;
1751
+
power-domains = <&rpmhpd RPMHPD_CX>;
1753
1752
operating-points-v2 = <&qup_opp_table>;
1754
1753
status = "disabled";
1755
1754
};
···
1779
1778
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1780
1779
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
1781
1780
dma-names = "tx", "rx";
1782
-
power-domains = <&rpmhpd SM8250_CX>;
1781
+
power-domains = <&rpmhpd RPMHPD_CX>;
1783
1782
operating-points-v2 = <&qup_opp_table>;
1784
1783
#address-cells = <1>;
1785
1784
#size-cells = <0>;
···
1906
1905
1907
1906
pinctrl-names = "default";
1908
1907
pinctrl-0 = <&pcie0_default_state>;
1908
+
dma-coherent;
1909
1909
1910
1910
status = "disabled";
1911
1911
};
···
2013
2011
2014
2012
pinctrl-names = "default";
2015
2013
pinctrl-0 = <&pcie1_default_state>;
2014
+
dma-coherent;
2016
2015
2017
2016
status = "disabled";
2018
2017
};
···
2122
2119
2123
2120
pinctrl-names = "default";
2124
2121
pinctrl-0 = <&pcie2_default_state>;
2122
+
dma-coherent;
2125
2123
2126
2124
status = "disabled";
2127
2125
};
···
2207
2203
<0 0>,
2208
2204
<0 0>,
2209
2205
<0 0>;
2206
+
2207
+
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2208
+
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2209
+
interconnect-names = "ufs-ddr", "cpu-ufs";
2210
2210
2211
2211
status = "disabled";
2212
2212
};
···
2734
2726
clock-names = "ahb", "bus", "iface";
2735
2727
2736
2728
power-domains = <&gpucc GPU_CX_GDSC>;
2729
+
dma-coherent;
2737
2730
};
2738
2731
2739
2732
slpi: remoteproc@5c00000 {
···
2752
2743
clocks = <&rpmhcc RPMH_CXO_CLK>;
2753
2744
clock-names = "xo";
2754
2745
2755
-
power-domains = <&rpmhpd SM8250_LCX>,
2756
-
<&rpmhpd SM8250_LMX>;
2746
+
power-domains = <&rpmhpd RPMHPD_LCX>,
2747
+
<&rpmhpd RPMHPD_LMX>;
2757
2748
power-domain-names = "lcx", "lmx";
2758
2749
2759
2750
memory-region = <&slpi_mem>;
···
3068
3059
port@7 {
3069
3060
reg = <7>;
3070
3061
funnel_swao_in_funnel_merg: endpoint {
3071
-
remote-endpoint= <&funnel_merg_out_funnel_swao>;
3062
+
remote-endpoint = <&funnel_merg_out_funnel_swao>;
3072
3063
};
3073
3064
};
3074
3065
};
···
3472
3463
clocks = <&rpmhcc RPMH_CXO_CLK>;
3473
3464
clock-names = "xo";
3474
3465
3475
-
power-domains = <&rpmhpd SM8250_CX>;
3466
+
power-domains = <&rpmhpd RPMHPD_CX>;
3476
3467
3477
3468
memory-region = <&cdsp_mem>;
3478
3469
···
3669
3660
iommus = <&apps_smmu 0x4a0 0x0>;
3670
3661
qcom,dll-config = <0x0007642c>;
3671
3662
qcom,ddr-config = <0x80040868>;
3672
-
power-domains = <&rpmhpd SM8250_CX>;
3663
+
power-domains = <&rpmhpd RPMHPD_CX>;
3673
3664
operating-points-v2 = <&sdhc2_opp_table>;
3674
3665
3675
3666
status = "disabled";
···
3695
3686
opp-202000000 {
3696
3687
opp-hz = /bits/ 64 <202000000>;
3697
3688
required-opps = <&rpmhpd_opp_svs_l1>;
3689
+
};
3690
+
};
3691
+
};
3692
+
3693
+
pmu@9091000 {
3694
+
compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3695
+
reg = <0 0x09091000 0 0x1000>;
3696
+
3697
+
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3698
+
3699
+
interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
3700
+
3701
+
operating-points-v2 = <&llcc_bwmon_opp_table>;
3702
+
3703
+
llcc_bwmon_opp_table: opp-table {
3704
+
compatible = "operating-points-v2";
3705
+
3706
+
opp-800000 {
3707
+
opp-peak-kBps = <(200 * 4 * 1000)>;
3708
+
};
3709
+
3710
+
opp-1200000 {
3711
+
opp-peak-kBps = <(300 * 4 * 1000)>;
3712
+
};
3713
+
3714
+
opp-1804000 {
3715
+
opp-peak-kBps = <(451 * 4 * 1000)>;
3716
+
};
3717
+
3718
+
opp-2188000 {
3719
+
opp-peak-kBps = <(547 * 4 * 1000)>;
3720
+
};
3721
+
3722
+
opp-2724000 {
3723
+
opp-peak-kBps = <(681 * 4 * 1000)>;
3724
+
};
3725
+
3726
+
opp-3072000 {
3727
+
opp-peak-kBps = <(768 * 4 * 1000)>;
3728
+
};
3729
+
3730
+
opp-4068000 {
3731
+
opp-peak-kBps = <(1017 * 4 * 1000)>;
3732
+
};
3733
+
3734
+
/* 1353 MHz, LPDDR4X */
3735
+
3736
+
opp-6220000 {
3737
+
opp-peak-kBps = <(1555 * 4 * 1000)>;
3738
+
};
3739
+
3740
+
opp-7216000 {
3741
+
opp-peak-kBps = <(1804 * 4 * 1000)>;
3742
+
};
3743
+
3744
+
opp-8368000 {
3745
+
opp-peak-kBps = <(2092 * 4 * 1000)>;
3746
+
};
3747
+
3748
+
/* LPDDR5 */
3749
+
opp-10944000 {
3750
+
opp-peak-kBps = <(2736 * 4 * 1000)>;
3751
+
};
3752
+
};
3753
+
};
3754
+
3755
+
pmu@90b6400 {
3756
+
compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
3757
+
reg = <0 0x090b6400 0 0x600>;
3758
+
3759
+
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3760
+
3761
+
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
3762
+
operating-points-v2 = <&cpu_bwmon_opp_table>;
3763
+
3764
+
cpu_bwmon_opp_table: opp-table {
3765
+
compatible = "operating-points-v2";
3766
+
3767
+
opp-800000 {
3768
+
opp-peak-kBps = <(200 * 4 * 1000)>;
3769
+
};
3770
+
3771
+
opp-1804000 {
3772
+
opp-peak-kBps = <(451 * 4 * 1000)>;
3773
+
};
3774
+
3775
+
opp-2188000 {
3776
+
opp-peak-kBps = <(547 * 4 * 1000)>;
3777
+
};
3778
+
3779
+
opp-2724000 {
3780
+
opp-peak-kBps = <(681 * 4 * 1000)>;
3781
+
};
3782
+
3783
+
opp-3072000 {
3784
+
opp-peak-kBps = <(768 * 4 * 1000)>;
3785
+
};
3786
+
3787
+
/* 1017MHz, 1353 MHz, LPDDR4X */
3788
+
3789
+
opp-6220000 {
3790
+
opp-peak-kBps = <(1555 * 4 * 1000)>;
3791
+
};
3792
+
3793
+
opp-6832000 {
3794
+
opp-peak-kBps = <(1708 * 4 * 1000)>;
3795
+
};
3796
+
3797
+
opp-8368000 {
3798
+
opp-peak-kBps = <(2092 * 4 * 1000)>;
3799
+
};
3800
+
3801
+
/* 2133MHz, LPDDR4X */
3802
+
3803
+
/* LPDDR5 */
3804
+
opp-10944000 {
3805
+
opp-peak-kBps = <(2736 * 4 * 1000)>;
3806
+
};
3807
+
3808
+
/* LPDDR5 */
3809
+
opp-12784000 {
3810
+
opp-peak-kBps = <(3196 * 4 * 1000)>;
3698
3811
};
3699
3812
};
3700
3813
};
···
3967
3836
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3968
3837
power-domains = <&videocc MVS0C_GDSC>,
3969
3838
<&videocc MVS0_GDSC>,
3970
-
<&rpmhpd SM8250_MX>;
3839
+
<&rpmhpd RPMHPD_MX>;
3971
3840
power-domain-names = "venus", "vcodec0", "mx";
3972
3841
operating-points-v2 = <&venus_opp_table>;
3973
3842
···
4028
3897
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4029
3898
<&rpmhcc RPMH_CXO_CLK>,
4030
3899
<&rpmhcc RPMH_CXO_CLK_A>;
4031
-
power-domains = <&rpmhpd SM8250_MMCX>;
3900
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4032
3901
required-opps = <&rpmhpd_opp_low_svs>;
4033
3902
clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4034
3903
#clock-cells = <1>;
···
4308
4177
<&rpmhcc RPMH_CXO_CLK_A>,
4309
4178
<&sleep_clk>;
4310
4179
clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4311
-
power-domains = <&rpmhpd SM8250_MMCX>;
4180
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4312
4181
required-opps = <&rpmhpd_opp_low_svs>;
4313
4182
status = "disabled";
4314
4183
#clock-cells = <1>;
···
4361
4230
assigned-clock-rates = <19200000>;
4362
4231
4363
4232
operating-points-v2 = <&mdp_opp_table>;
4364
-
power-domains = <&rpmhpd SM8250_MMCX>;
4233
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4365
4234
4366
4235
interrupt-parent = <&mdss>;
4367
4236
interrupts = <0>;
···
4436
4305
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4437
4306
4438
4307
operating-points-v2 = <&dsi_opp_table>;
4439
-
power-domains = <&rpmhpd SM8250_MMCX>;
4308
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4440
4309
4441
4310
phys = <&mdss_dsi0_phy>;
4442
4311
···
4528
4397
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4529
4398
4530
4399
operating-points-v2 = <&dsi_opp_table>;
4531
-
power-domains = <&rpmhpd SM8250_MMCX>;
4400
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4532
4401
4533
4402
phys = <&mdss_dsi1_phy>;
4534
4403
···
4579
4448
dispcc: clock-controller@af00000 {
4580
4449
compatible = "qcom,sm8250-dispcc";
4581
4450
reg = <0 0x0af00000 0 0x10000>;
4582
-
power-domains = <&rpmhpd SM8250_MMCX>;
4451
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4583
4452
required-opps = <&rpmhpd_opp_low_svs>;
4584
4453
clocks = <&rpmhcc RPMH_CXO_CLK>,
4585
4454
<&mdss_dsi0_phy 0>,
···
5429
5298
reg = <0 0x15000000 0 0x100000>;
5430
5299
#iommu-cells = <2>;
5431
5300
#global-interrupts = <2>;
5432
-
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5433
-
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5434
-
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5435
-
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5436
-
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5437
-
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5438
-
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5439
-
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5440
-
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5441
-
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5442
-
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5443
-
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5444
-
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5445
-
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5446
-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5447
-
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5448
-
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5449
-
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5450
-
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5451
-
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5452
-
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5453
-
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5454
-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5455
-
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5456
-
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5457
-
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5458
-
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5459
-
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5460
-
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5461
-
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5462
-
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5463
-
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5464
-
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5465
-
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5466
-
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5467
-
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5468
-
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5469
-
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5470
-
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5471
-
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5472
-
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5473
-
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5474
-
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5475
-
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5476
-
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5477
-
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5478
-
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5479
-
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5480
-
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5481
-
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5482
-
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5483
-
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5484
-
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5485
-
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5486
-
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5487
-
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5488
-
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5489
-
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5490
-
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5491
-
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5492
-
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5493
-
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5494
-
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5495
-
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5496
-
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5497
-
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5498
-
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5499
-
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5500
-
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5501
-
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5502
-
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5503
-
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5504
-
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5505
-
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5506
-
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5507
-
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5508
-
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5509
-
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5510
-
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5511
-
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5512
-
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5513
-
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5514
-
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5515
-
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5516
-
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5517
-
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5518
-
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5519
-
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5520
-
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5521
-
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5522
-
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5523
-
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5524
-
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5525
-
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5526
-
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5527
-
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5528
-
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5529
-
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5301
+
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5302
+
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5303
+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5304
+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5305
+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5306
+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5307
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5308
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5309
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5310
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5311
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5312
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5313
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5314
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5315
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5316
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5317
+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5318
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5319
+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5320
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5321
+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5322
+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5323
+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5324
+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5325
+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5326
+
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5327
+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5328
+
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5329
+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5330
+
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5331
+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5332
+
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5333
+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5334
+
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5335
+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5336
+
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5337
+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5338
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5339
+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5340
+
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5341
+
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5342
+
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5343
+
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5344
+
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5345
+
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5346
+
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5347
+
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5348
+
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5349
+
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5350
+
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5351
+
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5352
+
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5353
+
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5354
+
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5355
+
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5356
+
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5357
+
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5358
+
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5359
+
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5360
+
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5361
+
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5362
+
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5363
+
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5364
+
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5365
+
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5366
+
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5367
+
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5368
+
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5369
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5370
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5371
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5372
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5373
+
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5374
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5375
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5376
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5377
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5378
+
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5379
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5380
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5381
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5382
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5383
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5384
+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5385
+
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5386
+
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5387
+
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5388
+
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5389
+
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5390
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5391
+
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5392
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5393
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5394
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5395
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5396
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5397
+
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5398
+
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5399
+
dma-coherent;
5530
5400
};
5531
5401
5532
5402
adsp: remoteproc@17300000 {
···
5545
5413
clocks = <&rpmhcc RPMH_CXO_CLK>;
5546
5414
clock-names = "xo";
5547
5415
5548
-
power-domains = <&rpmhpd SM8250_LCX>,
5549
-
<&rpmhpd SM8250_LMX>;
5416
+
power-domains = <&rpmhpd RPMHPD_LCX>,
5417
+
<&rpmhpd RPMHPD_LMX>;
5550
5418
power-domain-names = "lcx", "lmx";
5551
5419
5552
5420
memory-region = <&adsp_mem>;
+24
-11
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+24
-11
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
···
7
7
8
8
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9
9
#include "sm8350.dtsi"
10
+
#include "pmk8350.dtsi"
10
11
11
12
/ {
12
13
model = "Qualcomm Technologies, Inc. SM8350 HDK";
13
14
compatible = "qcom,sm8350-hdk", "qcom,sm8350";
15
+
chassis-type = "embedded";
14
16
15
17
aliases {
16
18
serial0 = &uart2;
···
350
348
vcc-supply = <&vreg_bob>;
351
349
mode-switch;
352
350
orientation-switch;
353
-
svid = /bits/ 16 <0xff01>;
354
351
355
-
ports {
356
-
#address-cells = <1>;
357
-
#size-cells = <0>;
358
-
359
-
port@0 {
360
-
reg = <0>;
361
-
362
-
fsa4480_sbu_mux: endpoint {
363
-
remote-endpoint = <&pmic_glink_sbu>;
364
-
};
352
+
port {
353
+
fsa4480_sbu_mux: endpoint {
354
+
remote-endpoint = <&pmic_glink_sbu>;
365
355
};
366
356
};
367
357
};
···
465
471
};
466
472
467
473
&qupv3_id_2 {
474
+
status = "okay";
475
+
};
476
+
477
+
&sdhc_2 {
478
+
cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
479
+
pinctrl-names = "default", "sleep";
480
+
pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
481
+
pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
482
+
vmmc-supply = <&vreg_l9c_2p96>;
483
+
vqmmc-supply = <&vreg_l6c_1p8>;
484
+
no-sdio;
485
+
no-mmc;
468
486
status = "okay";
469
487
};
470
488
···
737
731
drive-strength = <2>;
738
732
bias-pull-up;
739
733
};
734
+
};
735
+
736
+
sdc2_card_det_n: sd-card-det-n-state {
737
+
pins = "gpio92";
738
+
function = "gpio";
739
+
drive-strength = <2>;
740
+
bias-pull-up;
740
741
};
741
742
};
742
743
+1
arch/arm64/boot/dts/qcom/sm8350-mtp.dts
+1
arch/arm64/boot/dts/qcom/sm8350-mtp.dts
+250
-149
arch/arm64/boot/dts/qcom/sm8350.dtsi
+250
-149
arch/arm64/boot/dts/qcom/sm8350.dtsi
···
15
15
#include <dt-bindings/mailbox/qcom-ipcc.h>
16
16
#include <dt-bindings/phy/phy-qcom-qmp.h>
17
17
#include <dt-bindings/power/qcom-rpmpd.h>
18
+
#include <dt-bindings/power/qcom,rpmhpd.h>
19
+
#include <dt-bindings/soc/qcom,apr.h>
18
20
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
21
+
#include <dt-bindings/sound/qcom,q6afe.h>
19
22
#include <dt-bindings/thermal/thermal.h>
20
23
#include <dt-bindings/interconnect/qcom,sm8350.h>
21
24
···
51
48
52
49
CPU0: cpu@0 {
53
50
device_type = "cpu";
54
-
compatible = "qcom,kryo685";
51
+
compatible = "arm,cortex-a55";
55
52
reg = <0x0 0x0>;
56
53
clocks = <&cpufreq_hw 0>;
57
54
enable-method = "psci";
···
75
72
76
73
CPU1: cpu@100 {
77
74
device_type = "cpu";
78
-
compatible = "qcom,kryo685";
75
+
compatible = "arm,cortex-a55";
79
76
reg = <0x0 0x100>;
80
77
clocks = <&cpufreq_hw 0>;
81
78
enable-method = "psci";
···
94
91
95
92
CPU2: cpu@200 {
96
93
device_type = "cpu";
97
-
compatible = "qcom,kryo685";
94
+
compatible = "arm,cortex-a55";
98
95
reg = <0x0 0x200>;
99
96
clocks = <&cpufreq_hw 0>;
100
97
enable-method = "psci";
···
113
110
114
111
CPU3: cpu@300 {
115
112
device_type = "cpu";
116
-
compatible = "qcom,kryo685";
113
+
compatible = "arm,cortex-a55";
117
114
reg = <0x0 0x300>;
118
115
clocks = <&cpufreq_hw 0>;
119
116
enable-method = "psci";
···
132
129
133
130
CPU4: cpu@400 {
134
131
device_type = "cpu";
135
-
compatible = "qcom,kryo685";
132
+
compatible = "arm,cortex-a78";
136
133
reg = <0x0 0x400>;
137
134
clocks = <&cpufreq_hw 1>;
138
135
enable-method = "psci";
···
151
148
152
149
CPU5: cpu@500 {
153
150
device_type = "cpu";
154
-
compatible = "qcom,kryo685";
151
+
compatible = "arm,cortex-a78";
155
152
reg = <0x0 0x500>;
156
153
clocks = <&cpufreq_hw 1>;
157
154
enable-method = "psci";
···
170
167
171
168
CPU6: cpu@600 {
172
169
device_type = "cpu";
173
-
compatible = "qcom,kryo685";
170
+
compatible = "arm,cortex-a78";
174
171
reg = <0x0 0x600>;
175
172
clocks = <&cpufreq_hw 1>;
176
173
enable-method = "psci";
···
189
186
190
187
CPU7: cpu@700 {
191
188
device_type = "cpu";
192
-
compatible = "qcom,kryo685";
189
+
compatible = "arm,cortex-x1";
193
190
reg = <0x0 0x700>;
194
191
clocks = <&cpufreq_hw 2>;
195
192
enable-method = "psci";
···
249
246
compatible = "arm,idle-state";
250
247
idle-state-name = "silver-rail-power-collapse";
251
248
arm,psci-suspend-param = <0x40000004>;
252
-
entry-latency-us = <355>;
253
-
exit-latency-us = <909>;
249
+
entry-latency-us = <360>;
250
+
exit-latency-us = <531>;
254
251
min-residency-us = <3934>;
255
252
local-timer-stop;
256
253
};
···
259
256
compatible = "arm,idle-state";
260
257
idle-state-name = "gold-rail-power-collapse";
261
258
arm,psci-suspend-param = <0x40000004>;
262
-
entry-latency-us = <241>;
263
-
exit-latency-us = <1461>;
259
+
entry-latency-us = <702>;
260
+
exit-latency-us = <1061>;
264
261
min-residency-us = <4488>;
265
262
local-timer-stop;
266
263
};
267
264
};
268
265
269
266
domain-idle-states {
270
-
CLUSTER_SLEEP_0: cluster-sleep-0 {
267
+
CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
268
+
compatible = "domain-idle-state";
269
+
arm,psci-suspend-param = <0x41000044>;
270
+
entry-latency-us = <2752>;
271
+
exit-latency-us = <3048>;
272
+
min-residency-us = <6118>;
273
+
};
274
+
275
+
CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
271
276
compatible = "domain-idle-state";
272
277
arm,psci-suspend-param = <0x4100c344>;
273
278
entry-latency-us = <3263>;
···
357
346
358
347
CLUSTER_PD: power-domain-cpu-cluster0 {
359
348
#power-domain-cells = <0>;
360
-
domain-idle-states = <&CLUSTER_SLEEP_0>;
349
+
domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
361
350
};
362
351
};
363
352
···
748
737
clock-names = "se";
749
738
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
750
739
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
751
-
power-domains = <&rpmhpd SM8350_CX>;
740
+
power-domains = <&rpmhpd RPMHPD_CX>;
752
741
operating-points-v2 = <&qup_opp_table_120mhz>;
753
742
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
754
743
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
···
780
769
clock-names = "se";
781
770
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
782
771
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
783
-
power-domains = <&rpmhpd SM8350_CX>;
772
+
power-domains = <&rpmhpd RPMHPD_CX>;
784
773
operating-points-v2 = <&qup_opp_table_120mhz>;
785
774
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
786
775
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
···
812
801
clock-names = "se";
813
802
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
814
803
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
815
-
power-domains = <&rpmhpd SM8350_CX>;
804
+
power-domains = <&rpmhpd RPMHPD_CX>;
816
805
operating-points-v2 = <&qup_opp_table_100mhz>;
817
806
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
818
807
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
···
844
833
clock-names = "se";
845
834
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
846
835
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
847
-
power-domains = <&rpmhpd SM8350_CX>;
836
+
power-domains = <&rpmhpd RPMHPD_CX>;
848
837
operating-points-v2 = <&qup_opp_table_100mhz>;
849
838
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
850
839
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
···
862
851
clock-names = "se";
863
852
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
864
853
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
865
-
power-domains = <&rpmhpd SM8350_CX>;
854
+
power-domains = <&rpmhpd RPMHPD_CX>;
866
855
operating-points-v2 = <&qup_opp_table_100mhz>;
867
856
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
868
857
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
···
880
869
pinctrl-names = "default";
881
870
pinctrl-0 = <&qup_uart18_default>;
882
871
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
883
-
power-domains = <&rpmhpd SM8350_CX>;
872
+
power-domains = <&rpmhpd RPMHPD_CX>;
884
873
operating-points-v2 = <&qup_opp_table_100mhz>;
885
874
status = "disabled";
886
875
};
···
907
896
clock-names = "se";
908
897
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
909
898
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
910
-
power-domains = <&rpmhpd SM8350_CX>;
899
+
power-domains = <&rpmhpd RPMHPD_CX>;
911
900
operating-points-v2 = <&qup_opp_table_100mhz>;
912
901
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
913
902
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
···
974
963
clock-names = "se";
975
964
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
976
965
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
977
-
power-domains = <&rpmhpd SM8350_CX>;
966
+
power-domains = <&rpmhpd RPMHPD_CX>;
978
967
operating-points-v2 = <&qup_opp_table_100mhz>;
979
968
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
980
969
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
···
1006
995
clock-names = "se";
1007
996
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1008
997
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1009
-
power-domains = <&rpmhpd SM8350_CX>;
998
+
power-domains = <&rpmhpd RPMHPD_CX>;
1010
999
operating-points-v2 = <&qup_opp_table_100mhz>;
1011
1000
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1012
1001
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
···
1038
1027
clock-names = "se";
1039
1028
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1040
1029
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1041
-
power-domains = <&rpmhpd SM8350_CX>;
1030
+
power-domains = <&rpmhpd RPMHPD_CX>;
1042
1031
operating-points-v2 = <&qup_opp_table_100mhz>;
1043
1032
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1044
1033
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
···
1056
1045
pinctrl-names = "default";
1057
1046
pinctrl-0 = <&qup_uart3_default_state>;
1058
1047
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1059
-
power-domains = <&rpmhpd SM8350_CX>;
1048
+
power-domains = <&rpmhpd RPMHPD_CX>;
1060
1049
operating-points-v2 = <&qup_opp_table_100mhz>;
1061
1050
status = "disabled";
1062
1051
};
···
1069
1058
clock-names = "se";
1070
1059
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1071
1060
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1072
-
power-domains = <&rpmhpd SM8350_CX>;
1061
+
power-domains = <&rpmhpd RPMHPD_CX>;
1073
1062
operating-points-v2 = <&qup_opp_table_100mhz>;
1074
1063
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1075
1064
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
···
1101
1090
clock-names = "se";
1102
1091
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1103
1092
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1104
-
power-domains = <&rpmhpd SM8350_CX>;
1093
+
power-domains = <&rpmhpd RPMHPD_CX>;
1105
1094
operating-points-v2 = <&qup_opp_table_100mhz>;
1106
1095
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1107
1096
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
···
1133
1122
clock-names = "se";
1134
1123
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1135
1124
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1136
-
power-domains = <&rpmhpd SM8350_CX>;
1125
+
power-domains = <&rpmhpd RPMHPD_CX>;
1137
1126
operating-points-v2 = <&qup_opp_table_100mhz>;
1138
1127
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1139
1128
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
···
1165
1154
clock-names = "se";
1166
1155
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1167
1156
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1168
-
power-domains = <&rpmhpd SM8350_CX>;
1157
+
power-domains = <&rpmhpd RPMHPD_CX>;
1169
1158
operating-points-v2 = <&qup_opp_table_100mhz>;
1170
1159
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1171
1160
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
···
1183
1172
pinctrl-names = "default";
1184
1173
pinctrl-0 = <&qup_uart6_default>;
1185
1174
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1186
-
power-domains = <&rpmhpd SM8350_CX>;
1175
+
power-domains = <&rpmhpd RPMHPD_CX>;
1187
1176
operating-points-v2 = <&qup_opp_table_100mhz>;
1188
1177
status = "disabled";
1189
1178
};
···
1210
1199
clock-names = "se";
1211
1200
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1212
1201
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1213
-
power-domains = <&rpmhpd SM8350_CX>;
1202
+
power-domains = <&rpmhpd RPMHPD_CX>;
1214
1203
operating-points-v2 = <&qup_opp_table_100mhz>;
1215
1204
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1216
1205
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
···
1277
1266
clock-names = "se";
1278
1267
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1279
1268
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1280
-
power-domains = <&rpmhpd SM8350_CX>;
1269
+
power-domains = <&rpmhpd RPMHPD_CX>;
1281
1270
operating-points-v2 = <&qup_opp_table_120mhz>;
1282
1271
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1283
1272
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
···
1309
1298
clock-names = "se";
1310
1299
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1311
1300
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1312
-
power-domains = <&rpmhpd SM8350_CX>;
1301
+
power-domains = <&rpmhpd RPMHPD_CX>;
1313
1302
operating-points-v2 = <&qup_opp_table_100mhz>;
1314
1303
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1315
1304
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
···
1341
1330
clock-names = "se";
1342
1331
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1343
1332
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1344
-
power-domains = <&rpmhpd SM8350_CX>;
1333
+
power-domains = <&rpmhpd RPMHPD_CX>;
1345
1334
operating-points-v2 = <&qup_opp_table_100mhz>;
1346
1335
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1347
1336
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
···
1373
1362
clock-names = "se";
1374
1363
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1375
1364
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1376
-
power-domains = <&rpmhpd SM8350_CX>;
1365
+
power-domains = <&rpmhpd RPMHPD_CX>;
1377
1366
operating-points-v2 = <&qup_opp_table_100mhz>;
1378
1367
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1379
1368
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
···
1405
1394
clock-names = "se";
1406
1395
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1407
1396
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1408
-
power-domains = <&rpmhpd SM8350_CX>;
1397
+
power-domains = <&rpmhpd RPMHPD_CX>;
1409
1398
operating-points-v2 = <&qup_opp_table_100mhz>;
1410
1399
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1411
1400
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
···
1437
1426
clock-names = "se";
1438
1427
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1439
1428
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1440
-
power-domains = <&rpmhpd SM8350_CX>;
1429
+
power-domains = <&rpmhpd RPMHPD_CX>;
1441
1430
operating-points-v2 = <&qup_opp_table_100mhz>;
1442
1431
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1443
1432
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
···
1813
1802
#hwlock-cells = <1>;
1814
1803
};
1815
1804
1805
+
lpass_tlmm: pinctrl@33c0000 {
1806
+
compatible = "qcom,sm8350-lpass-lpi-pinctrl";
1807
+
reg = <0 0x033c0000 0 0x20000>,
1808
+
<0 0x03550000 0 0x10000>;
1809
+
1810
+
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1811
+
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1812
+
clock-names = "core", "audio";
1813
+
1814
+
gpio-controller;
1815
+
#gpio-cells = <2>;
1816
+
gpio-ranges = <&lpass_tlmm 0 0 15>;
1817
+
};
1818
+
1816
1819
gpu: gpu@3d00000 {
1817
1820
compatible = "qcom,adreno-660.1", "qcom,adreno";
1818
1821
···
2028
2003
clocks = <&rpmhcc RPMH_CXO_CLK>;
2029
2004
clock-names = "xo";
2030
2005
2031
-
power-domains = <&rpmhpd SM8350_CX>,
2032
-
<&rpmhpd SM8350_MSS>;
2006
+
power-domains = <&rpmhpd RPMHPD_CX>,
2007
+
<&rpmhpd RPMHPD_MSS>;
2033
2008
power-domain-names = "cx", "mss";
2034
2009
2035
2010
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
···
2069
2044
clocks = <&rpmhcc RPMH_CXO_CLK>;
2070
2045
clock-names = "xo";
2071
2046
2072
-
power-domains = <&rpmhpd SM8350_LCX>,
2073
-
<&rpmhpd SM8350_LMX>;
2047
+
power-domains = <&rpmhpd RPMHPD_LCX>,
2048
+
<&rpmhpd RPMHPD_LMX>;
2074
2049
power-domain-names = "lcx", "lmx";
2075
2050
2076
2051
memory-region = <&pil_slpi_mem>;
···
2139
2114
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2140
2115
interconnect-names = "sdhc-ddr","cpu-sdhc";
2141
2116
iommus = <&apps_smmu 0x4a0 0x0>;
2142
-
power-domains = <&rpmhpd SM8350_CX>;
2117
+
power-domains = <&rpmhpd RPMHPD_CX>;
2143
2118
operating-points-v2 = <&sdhc2_opp_table>;
2144
2119
bus-width = <4>;
2145
2120
dma-coherent;
···
2500
2475
assigned-clock-rates = <19200000>;
2501
2476
2502
2477
operating-points-v2 = <&dpu_opp_table>;
2503
-
power-domains = <&rpmhpd SM8350_MMCX>;
2478
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2504
2479
2505
2480
interrupt-parent = <&mdss>;
2506
2481
interrupts = <0>;
···
2563
2538
#sound-dai-cells = <0>;
2564
2539
2565
2540
operating-points-v2 = <&dp_opp_table>;
2566
-
power-domains = <&rpmhpd SM8350_MMCX>;
2541
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2567
2542
2568
2543
status = "disabled";
2569
2544
···
2631
2606
<&mdss_dsi0_phy 1>;
2632
2607
2633
2608
operating-points-v2 = <&dsi0_opp_table>;
2634
-
power-domains = <&rpmhpd SM8350_MMCX>;
2609
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2635
2610
2636
2611
phys = <&mdss_dsi0_phy>;
2637
2612
···
2729
2704
<&mdss_dsi1_phy 1>;
2730
2705
2731
2706
operating-points-v2 = <&dsi1_opp_table>;
2732
-
power-domains = <&rpmhpd SM8350_MMCX>;
2707
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2733
2708
2734
2709
phys = <&mdss_dsi1_phy>;
2735
2710
···
2820
2795
#reset-cells = <1>;
2821
2796
#power-domain-cells = <1>;
2822
2797
2823
-
power-domains = <&rpmhpd SM8350_MMCX>;
2798
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2824
2799
};
2825
2800
2826
2801
pdc: interrupt-controller@b220000 {
···
3098
3073
reg = <0 0x15000000 0 0x100000>;
3099
3074
#iommu-cells = <2>;
3100
3075
#global-interrupts = <2>;
3101
-
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3102
-
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3103
-
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3104
-
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3105
-
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3106
-
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3107
-
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3108
-
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3109
-
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3110
-
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3111
-
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3112
-
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3113
-
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3114
-
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3115
-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3116
-
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3117
-
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3118
-
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3119
-
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3120
-
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3121
-
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3122
-
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3123
-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3124
-
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3125
-
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3126
-
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3127
-
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3128
-
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3129
-
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3130
-
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3131
-
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3132
-
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3133
-
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3134
-
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3135
-
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3136
-
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3137
-
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3138
-
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3139
-
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3140
-
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3141
-
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3142
-
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3143
-
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3144
-
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3145
-
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3146
-
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3147
-
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3148
-
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3149
-
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3150
-
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3151
-
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3152
-
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3153
-
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3154
-
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3155
-
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3156
-
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3157
-
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3158
-
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3159
-
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3160
-
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3161
-
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3162
-
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3163
-
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3164
-
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3165
-
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3166
-
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3167
-
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3168
-
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3169
-
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3170
-
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3171
-
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3172
-
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3173
-
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3174
-
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3175
-
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3176
-
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3177
-
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3178
-
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3179
-
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3180
-
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3181
-
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3182
-
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3183
-
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3184
-
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3185
-
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3186
-
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3187
-
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3188
-
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3189
-
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3190
-
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3191
-
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3192
-
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3193
-
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3194
-
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3195
-
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3196
-
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3197
-
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3198
-
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3076
+
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3077
+
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3078
+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3079
+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3080
+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3081
+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3082
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3083
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3084
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3085
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3086
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3087
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3088
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3089
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3090
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3091
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3092
+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3093
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3094
+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3095
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3096
+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3097
+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3098
+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3099
+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3100
+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3101
+
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3102
+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3103
+
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3104
+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3105
+
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3106
+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3107
+
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3108
+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3109
+
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3110
+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3111
+
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3112
+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3113
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3114
+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3115
+
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3116
+
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3117
+
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3118
+
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3119
+
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3120
+
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3121
+
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3122
+
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3123
+
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3124
+
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3125
+
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3126
+
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3127
+
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3128
+
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3129
+
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3130
+
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3131
+
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3132
+
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3133
+
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3134
+
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3135
+
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3136
+
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3137
+
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3138
+
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3139
+
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3140
+
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3141
+
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3142
+
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3143
+
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3144
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3145
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3146
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3147
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3148
+
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3149
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3150
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3151
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3152
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3153
+
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3154
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3155
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3156
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3157
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3158
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3159
+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3160
+
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3161
+
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3162
+
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3163
+
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3164
+
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3165
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3166
+
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3167
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3168
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3169
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3170
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3171
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3172
+
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3173
+
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3199
3174
};
3200
3175
3201
3176
adsp: remoteproc@17300000 {
···
3213
3188
clocks = <&rpmhcc RPMH_CXO_CLK>;
3214
3189
clock-names = "xo";
3215
3190
3216
-
power-domains = <&rpmhpd SM8350_LCX>,
3217
-
<&rpmhpd SM8350_LMX>;
3191
+
power-domains = <&rpmhpd RPMHPD_LCX>,
3192
+
<&rpmhpd RPMHPD_LMX>;
3218
3193
power-domain-names = "lcx", "lmx";
3219
3194
3220
3195
memory-region = <&pil_adsp_mem>;
···
3235
3210
3236
3211
label = "lpass";
3237
3212
qcom,remote-pid = <2>;
3213
+
3214
+
apr {
3215
+
compatible = "qcom,apr-v2";
3216
+
qcom,glink-channels = "apr_audio_svc";
3217
+
qcom,domain = <APR_DOMAIN_ADSP>;
3218
+
#address-cells = <1>;
3219
+
#size-cells = <0>;
3220
+
3221
+
service@3 {
3222
+
reg = <APR_SVC_ADSP_CORE>;
3223
+
compatible = "qcom,q6core";
3224
+
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3225
+
};
3226
+
3227
+
q6afe: service@4 {
3228
+
compatible = "qcom,q6afe";
3229
+
reg = <APR_SVC_AFE>;
3230
+
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3231
+
3232
+
q6afedai: dais {
3233
+
compatible = "qcom,q6afe-dais";
3234
+
#address-cells = <1>;
3235
+
#size-cells = <0>;
3236
+
#sound-dai-cells = <1>;
3237
+
};
3238
+
3239
+
q6afecc: clock-controller {
3240
+
compatible = "qcom,q6afe-clocks";
3241
+
#clock-cells = <2>;
3242
+
};
3243
+
};
3244
+
3245
+
q6asm: service@7 {
3246
+
compatible = "qcom,q6asm";
3247
+
reg = <APR_SVC_ASM>;
3248
+
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3249
+
3250
+
q6asmdai: dais {
3251
+
compatible = "qcom,q6asm-dais";
3252
+
#address-cells = <1>;
3253
+
#size-cells = <0>;
3254
+
#sound-dai-cells = <1>;
3255
+
iommus = <&apps_smmu 0x1801 0x0>;
3256
+
3257
+
dai@0 {
3258
+
reg = <0>;
3259
+
};
3260
+
3261
+
dai@1 {
3262
+
reg = <1>;
3263
+
};
3264
+
3265
+
dai@2 {
3266
+
reg = <2>;
3267
+
};
3268
+
};
3269
+
};
3270
+
3271
+
q6adm: service@8 {
3272
+
compatible = "qcom,q6adm";
3273
+
reg = <APR_SVC_ADM>;
3274
+
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3275
+
3276
+
q6routing: routing {
3277
+
compatible = "qcom,q6adm-routing";
3278
+
#sound-dai-cells = <0>;
3279
+
};
3280
+
};
3281
+
};
3238
3282
3239
3283
fastrpc {
3240
3284
compatible = "qcom,fastrpc";
···
3489
3395
<0 0x18593000 0 0x1000>;
3490
3396
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3491
3397
3398
+
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3399
+
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3400
+
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3401
+
interrupt-names = "dcvsh-irq-0",
3402
+
"dcvsh-irq-1",
3403
+
"dcvsh-irq-2";
3404
+
3492
3405
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3493
3406
clock-names = "xo", "alternate";
3494
3407
···
3518
3417
clocks = <&rpmhcc RPMH_CXO_CLK>;
3519
3418
clock-names = "xo";
3520
3419
3521
-
power-domains = <&rpmhpd SM8350_CX>,
3522
-
<&rpmhpd SM8350_MXC>;
3420
+
power-domains = <&rpmhpd RPMHPD_CX>,
3421
+
<&rpmhpd RPMHPD_MXC>;
3523
3422
power-domain-names = "cx", "mxc";
3524
3423
3525
3424
interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+291
-12
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+291
-12
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
···
6
6
/dts-v1/;
7
7
8
8
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9
+
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10
+
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
11
+
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12
+
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
9
13
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
10
14
#include "sm8450.dtsi"
11
15
#include "pm8350.dtsi"
···
18
14
#include "pm8450.dtsi"
19
15
#include "pmk8350.dtsi"
20
16
#include "pmr735a.dtsi"
21
-
#include "pmr735b.dtsi"
22
17
23
18
/ {
24
19
model = "Qualcomm Technologies, Inc. SM8450 HDK";
25
20
compatible = "qcom,sm8450-hdk", "qcom,sm8450";
21
+
chassis-type = "embedded";
26
22
27
23
aliases {
28
24
serial0 = &uart7;
···
130
126
};
131
127
};
132
128
129
+
};
130
+
};
131
+
};
132
+
133
+
thermal-zones {
134
+
camera-thermal {
135
+
polling-delay-passive = <250>;
136
+
polling-delay = <0>;
137
+
thermal-sensors = <&pmk8350_adc_tm 2>;
138
+
139
+
trips {
140
+
active-config0 {
141
+
temperature = <75000>;
142
+
hysteresis = <4000>;
143
+
type = "passive";
144
+
};
145
+
};
146
+
};
147
+
148
+
rear-tof-thermal {
149
+
polling-delay-passive = <250>;
150
+
polling-delay = <0>;
151
+
thermal-sensors = <&pmk8350_adc_tm 5>;
152
+
153
+
trips {
154
+
active-config0 {
155
+
temperature = <75000>;
156
+
hysteresis = <4000>;
157
+
type = "passive";
158
+
};
159
+
};
160
+
};
161
+
162
+
skin-msm-thermal {
163
+
polling-delay-passive = <250>;
164
+
polling-delay = <0>;
165
+
thermal-sensors = <&pmk8350_adc_tm 1>;
166
+
167
+
trips {
168
+
active-config0 {
169
+
temperature = <75000>;
170
+
hysteresis = <4000>;
171
+
type = "passive";
172
+
};
173
+
};
174
+
};
175
+
176
+
therm1-thermal {
177
+
polling-delay-passive = <250>;
178
+
polling-delay = <0>;
179
+
thermal-sensors = <&pmk8350_adc_tm 3>;
180
+
181
+
trips {
182
+
active-config0 {
183
+
temperature = <75000>;
184
+
hysteresis = <4000>;
185
+
type = "passive";
186
+
};
187
+
};
188
+
};
189
+
190
+
therm2-thermal {
191
+
polling-delay-passive = <250>;
192
+
polling-delay = <0>;
193
+
thermal-sensors = <&pmk8350_adc_tm 6>;
194
+
195
+
trips {
196
+
active-config0 {
197
+
temperature = <75000>;
198
+
hysteresis = <4000>;
199
+
type = "passive";
200
+
};
201
+
};
202
+
};
203
+
204
+
usb-conn-thermal {
205
+
polling-delay-passive = <250>;
206
+
polling-delay = <0>;
207
+
thermal-sensors = <&pmk8350_adc_tm 7>;
208
+
209
+
trips {
210
+
active-config0 {
211
+
temperature = <75000>;
212
+
hysteresis = <4000>;
213
+
type = "passive";
214
+
};
215
+
};
216
+
};
217
+
218
+
wide-rfc-thermal {
219
+
polling-delay-passive = <250>;
220
+
polling-delay = <0>;
221
+
thermal-sensors = <&pmk8350_adc_tm 4>;
222
+
223
+
trips {
224
+
active-config0 {
225
+
temperature = <75000>;
226
+
hysteresis = <4000>;
227
+
type = "passive";
228
+
};
229
+
};
230
+
};
231
+
232
+
xo-thermal {
233
+
polling-delay-passive = <0>;
234
+
polling-delay = <0>;
235
+
thermal-sensors = <&pmk8350_adc_tm 0>;
236
+
237
+
trips {
238
+
active-config0 {
239
+
temperature = <50000>;
240
+
hysteresis = <4000>;
241
+
type = "passive";
242
+
};
133
243
};
134
244
};
135
245
};
···
635
517
vcc-supply = <&vreg_bob>;
636
518
mode-switch;
637
519
orientation-switch;
638
-
svid = /bits/ 16 <0xff01>;
639
520
640
-
ports {
641
-
#address-cells = <1>;
642
-
#size-cells = <0>;
643
-
644
-
port@0 {
645
-
reg = <0>;
646
-
647
-
fsa4480_sbu_mux: endpoint {
648
-
remote-endpoint = <&pmic_glink_sbu>;
649
-
};
521
+
port {
522
+
fsa4480_sbu_mux: endpoint {
523
+
remote-endpoint = <&pmic_glink_sbu>;
650
524
};
651
525
};
652
526
};
···
697
587
status = "okay";
698
588
vdda-phy-supply = <&vreg_l2h_0p91>;
699
589
vdda-pll-supply = <&vreg_l6b_1p2>;
590
+
};
591
+
592
+
&pm8350_temp_alarm {
593
+
io-channels = <&pmk8350_vadc PM8350_ADC7_DIE_TEMP(1)>;
594
+
io-channel-names = "thermal";
595
+
};
596
+
597
+
&pm8350b_temp_alarm {
598
+
io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>;
599
+
io-channel-names = "thermal";
600
+
};
601
+
602
+
&pmr735a_temp_alarm {
603
+
io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>;
604
+
io-channel-names = "thermal";
605
+
};
606
+
607
+
&pmk8350_adc_tm {
608
+
status = "okay";
609
+
610
+
xo-therm@0 {
611
+
reg = <0>;
612
+
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
613
+
qcom,ratiometric;
614
+
qcom,hw-settle-time-us = <200>;
615
+
};
616
+
617
+
skin-msm-therm@1 {
618
+
reg = <1>;
619
+
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
620
+
qcom,ratiometric;
621
+
qcom,hw-settle-time-us = <200>;
622
+
};
623
+
624
+
camera-therm@2 {
625
+
reg = <2>;
626
+
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
627
+
qcom,ratiometric;
628
+
qcom,hw-settle-time-us = <200>;
629
+
};
630
+
631
+
therm1-therm@3 {
632
+
reg = <3>;
633
+
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
634
+
qcom,ratiometric;
635
+
qcom,hw-settle-time-us = <200>;
636
+
};
637
+
638
+
wide-rfc-therm@4 {
639
+
reg = <4>;
640
+
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
641
+
qcom,ratiometric;
642
+
qcom,hw-settle-time-us = <200>;
643
+
};
644
+
645
+
rear-tof-therm@5 {
646
+
reg = <5>;
647
+
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
648
+
qcom,ratiometric;
649
+
qcom,hw-settle-time-us = <200>;
650
+
};
651
+
652
+
therm2-therm@6 {
653
+
reg = <6>;
654
+
io-channels = <&pmk8350_vadc PM8350_ADC7_GPIO3_100K_PU(1)>;
655
+
qcom,ratiometric;
656
+
qcom,hw-settle-time-us = <200>;
657
+
};
658
+
659
+
usb-conn-therm@7 {
660
+
reg = <7>;
661
+
io-channels = <&pmk8350_vadc PM8350B_ADC7_AMUX_THM5_100K_PU>;
662
+
qcom,ratiometric;
663
+
qcom,hw-settle-time-us = <200>;
664
+
};
665
+
};
666
+
667
+
&pmk8350_vadc {
668
+
status = "okay";
669
+
670
+
channel@3 {
671
+
reg = <PMK8350_ADC7_DIE_TEMP>;
672
+
label = "pmk8350_die_temp";
673
+
};
674
+
675
+
channel@44 {
676
+
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
677
+
qcom,hw-settle-time = <200>;
678
+
qcom,ratiometric;
679
+
label = "pmk8350_xo_therm";
680
+
};
681
+
682
+
channel@103 {
683
+
reg = <PM8350_ADC7_DIE_TEMP(1)>;
684
+
label = "pm8350_die_temp";
685
+
};
686
+
687
+
channel@144 {
688
+
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
689
+
qcom,hw-settle-time = <200>;
690
+
qcom,ratiometric;
691
+
label = "skin_msm_temp";
692
+
};
693
+
694
+
channel@145 {
695
+
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
696
+
qcom,hw-settle-time = <200>;
697
+
qcom,ratiometric;
698
+
label = "camera_temp";
699
+
};
700
+
701
+
channel@146 {
702
+
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
703
+
qcom,hw-settle-time = <200>;
704
+
qcom,ratiometric;
705
+
label = "therm1_temp";
706
+
};
707
+
708
+
channel@147 {
709
+
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
710
+
qcom,hw-settle-time = <200>;
711
+
qcom,ratiometric;
712
+
label = "wide_rfc_temp";
713
+
};
714
+
715
+
channel@148 {
716
+
reg = <PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
717
+
qcom,hw-settle-time = <200>;
718
+
qcom,ratiometric;
719
+
label = "rear_tof_temp";
720
+
};
721
+
722
+
channel@14c {
723
+
reg = <PM8350_ADC7_GPIO3_100K_PU(1)>;
724
+
qcom,hw-settle-time = <200>;
725
+
qcom,ratiometric;
726
+
label = "therm2_temp";
727
+
};
728
+
729
+
channel@303 {
730
+
reg = <PM8350B_ADC7_DIE_TEMP>;
731
+
label = "pm8350b_die_temp";
732
+
};
733
+
734
+
channel@348 {
735
+
reg = <PM8350B_ADC7_AMUX_THM5_100K_PU>;
736
+
qcom,hw-settle-time = <200>;
737
+
qcom,ratiometric;
738
+
label = "usb_conn_temp";
739
+
};
740
+
741
+
channel@403 {
742
+
reg = <PMR735A_ADC7_DIE_TEMP>;
743
+
label = "pmr735a_die_temp";
744
+
};
745
+
746
+
channel@44a {
747
+
reg = <PMR735A_ADC7_GPIO1_100K_PU>;
748
+
qcom,hw-settle-time = <200>;
749
+
qcom,ratiometric;
750
+
label = "qtm_w_temp";
751
+
};
752
+
753
+
channel@44b {
754
+
reg = <PMR735A_ADC7_GPIO2_100K_PU>;
755
+
qcom,hw-settle-time = <200>;
756
+
qcom,ratiometric;
757
+
label = "qtm_n_temp";
758
+
};
700
759
};
701
760
702
761
&remoteproc_adsp {
+1
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+1
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+147
-127
arch/arm64/boot/dts/qcom/sm8450.dtsi
+147
-127
arch/arm64/boot/dts/qcom/sm8450.dtsi
···
13
13
#include <dt-bindings/gpio/gpio.h>
14
14
#include <dt-bindings/mailbox/qcom-ipcc.h>
15
15
#include <dt-bindings/phy/phy-qcom-qmp.h>
16
+
#include <dt-bindings/power/qcom,rpmhpd.h>
16
17
#include <dt-bindings/power/qcom-rpmpd.h>
18
+
#include <dt-bindings/interconnect/qcom,icc.h>
17
19
#include <dt-bindings/interconnect/qcom,sm8450.h>
18
20
#include <dt-bindings/soc/qcom,gpr.h>
19
21
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
···
1151
1149
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1152
1150
pinctrl-names = "default";
1153
1151
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1154
-
power-domains = <&rpmhpd SM8450_CX>;
1152
+
power-domains = <&rpmhpd RPMHPD_CX>;
1155
1153
operating-points-v2 = <&qup_opp_table_100mhz>;
1156
1154
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1157
1155
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
···
1314
1312
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1315
1313
pinctrl-names = "default";
1316
1314
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1317
-
power-domains = <&rpmhpd SM8450_CX>;
1315
+
power-domains = <&rpmhpd RPMHPD_CX>;
1318
1316
operating-points-v2 = <&qup_opp_table_100mhz>;
1319
1317
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1320
1318
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
···
1738
1736
};
1739
1737
};
1740
1738
1739
+
rng: rng@10c3000 {
1740
+
compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee";
1741
+
reg = <0 0x010c3000 0 0x1000>;
1742
+
};
1743
+
1741
1744
pcie0: pci@1c00000 {
1742
1745
compatible = "qcom,pcie-sm8450-pcie0";
1743
1746
reg = <0 0x01c00000 0 0x3000>,
···
2104
2097
clocks = <&rpmhcc RPMH_CXO_CLK>;
2105
2098
clock-names = "xo";
2106
2099
2107
-
power-domains = <&rpmhpd SM8450_LCX>,
2108
-
<&rpmhpd SM8450_LMX>;
2100
+
power-domains = <&rpmhpd RPMHPD_LCX>,
2101
+
<&rpmhpd RPMHPD_LMX>;
2109
2102
power-domain-names = "lcx", "lmx";
2110
2103
2111
2104
memory-region = <&slpi_mem>;
···
2379
2372
clocks = <&rpmhcc RPMH_CXO_CLK>;
2380
2373
clock-names = "xo";
2381
2374
2382
-
power-domains = <&rpmhpd SM8450_LCX>,
2383
-
<&rpmhpd SM8450_LMX>;
2375
+
power-domains = <&rpmhpd RPMHPD_LCX>,
2376
+
<&rpmhpd RPMHPD_LMX>;
2384
2377
power-domain-names = "lcx", "lmx";
2385
2378
2386
2379
memory-region = <&adsp_mem>;
···
2484
2477
clocks = <&rpmhcc RPMH_CXO_CLK>;
2485
2478
clock-names = "xo";
2486
2479
2487
-
power-domains = <&rpmhpd SM8450_CX>,
2488
-
<&rpmhpd SM8450_MXC>;
2480
+
power-domains = <&rpmhpd RPMHPD_CX>,
2481
+
<&rpmhpd RPMHPD_MXC>;
2489
2482
power-domain-names = "cx", "mxc";
2490
2483
2491
2484
memory-region = <&cdsp_mem>;
···
2591
2584
clocks = <&rpmhcc RPMH_CXO_CLK>;
2592
2585
clock-names = "xo";
2593
2586
2594
-
power-domains = <&rpmhpd SM8450_CX>,
2595
-
<&rpmhpd SM8450_MSS>;
2587
+
power-domains = <&rpmhpd RPMHPD_CX>,
2588
+
<&rpmhpd RPMHPD_MSS>;
2596
2589
power-domain-names = "cx", "mss";
2597
2590
2598
2591
memory-region = <&mpss_mem>;
···
2620
2613
reg = <0 0x0aaf0000 0 0x10000>;
2621
2614
clocks = <&rpmhcc RPMH_CXO_CLK>,
2622
2615
<&gcc GCC_VIDEO_AHB_CLK>;
2623
-
power-domains = <&rpmhpd SM8450_MMCX>;
2616
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2624
2617
required-opps = <&rpmhpd_opp_low_svs>;
2625
2618
#clock-cells = <1>;
2626
2619
#reset-cells = <1>;
···
2712
2705
<&rpmhcc RPMH_CXO_CLK>,
2713
2706
<&rpmhcc RPMH_CXO_CLK_A>,
2714
2707
<&sleep_clk>;
2715
-
power-domains = <&rpmhpd SM8450_MMCX>;
2708
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2716
2709
required-opps = <&rpmhpd_opp_low_svs>;
2717
2710
#clock-cells = <1>;
2718
2711
#reset-cells = <1>;
···
2727
2720
2728
2721
/* same path used twice */
2729
2722
interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2730
-
<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
2731
-
interconnect-names = "mdp0-mem", "mdp1-mem";
2723
+
<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2724
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2725
+
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2726
+
interconnect-names = "mdp0-mem",
2727
+
"mdp1-mem",
2728
+
"cpu-cfg";
2732
2729
2733
2730
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2734
2731
···
2778
2767
assigned-clock-rates = <19200000>;
2779
2768
2780
2769
operating-points-v2 = <&mdp_opp_table>;
2781
-
power-domains = <&rpmhpd SM8450_MMCX>;
2770
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2782
2771
2783
2772
interrupt-parent = <&mdss>;
2784
2773
interrupts = <0>;
···
2870
2859
#sound-dai-cells = <0>;
2871
2860
2872
2861
operating-points-v2 = <&dp_opp_table>;
2873
-
power-domains = <&rpmhpd SM8450_MMCX>;
2862
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2874
2863
2875
2864
status = "disabled";
2876
2865
···
2936
2925
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2937
2926
2938
2927
operating-points-v2 = <&mdss_dsi_opp_table>;
2939
-
power-domains = <&rpmhpd SM8450_MMCX>;
2928
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2940
2929
2941
2930
phys = <&mdss_dsi0_phy>;
2942
2931
phy-names = "dsi";
···
3028
3017
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3029
3018
3030
3019
operating-points-v2 = <&mdss_dsi_opp_table>;
3031
-
power-domains = <&rpmhpd SM8450_MMCX>;
3020
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
3032
3021
3033
3022
phys = <&mdss_dsi1_phy>;
3034
3023
phy-names = "dsi";
···
3096
3085
<0>,
3097
3086
<0>, /* dp3 */
3098
3087
<0>;
3099
-
power-domains = <&rpmhpd SM8450_MMCX>;
3088
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
3100
3089
required-opps = <&rpmhpd_opp_low_svs>;
3101
3090
#clock-cells = <1>;
3102
3091
#reset-cells = <1>;
···
3144
3133
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3145
3134
3146
3135
#clock-cells = <0>;
3136
+
};
3137
+
3138
+
sram@c3f0000 {
3139
+
compatible = "qcom,rpmh-stats";
3140
+
reg = <0 0x0c3f0000 0 0x400>;
3147
3141
};
3148
3142
3149
3143
spmi_bus: spmi@c400000 {
···
3826
3810
reg = <0 0x15000000 0 0x100000>;
3827
3811
#iommu-cells = <2>;
3828
3812
#global-interrupts = <1>;
3829
-
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3830
-
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3831
-
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3832
-
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3833
-
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3834
-
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3835
-
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3836
-
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3837
-
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3838
-
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3839
-
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3840
-
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3841
-
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3842
-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3843
-
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3844
-
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3845
-
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3846
-
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3847
-
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3848
-
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3849
-
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3850
-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3851
-
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3852
-
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3853
-
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3854
-
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3855
-
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3856
-
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3857
-
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3858
-
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3859
-
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3860
-
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3861
-
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3862
-
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3863
-
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3864
-
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3865
-
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3866
-
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3867
-
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3868
-
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3869
-
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3870
-
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3871
-
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3872
-
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3873
-
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3874
-
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3875
-
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3876
-
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3877
-
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3878
-
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3879
-
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3880
-
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3881
-
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3882
-
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3883
-
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3884
-
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3885
-
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3886
-
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3887
-
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3888
-
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3889
-
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3890
-
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3891
-
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3892
-
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3893
-
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3894
-
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3895
-
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3896
-
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3897
-
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3898
-
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3899
-
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3900
-
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3901
-
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3902
-
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3903
-
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3904
-
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3905
-
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3906
-
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3907
-
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3908
-
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3909
-
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3910
-
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3911
-
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3912
-
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3913
-
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3914
-
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3915
-
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3916
-
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3917
-
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3918
-
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3919
-
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3920
-
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3921
-
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3922
-
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3923
-
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3924
-
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3925
-
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
3813
+
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3814
+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3815
+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3816
+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3817
+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3818
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3819
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3820
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3821
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3822
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3823
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3824
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3825
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3826
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3827
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3828
+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3829
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3830
+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3831
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3832
+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3833
+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3834
+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3835
+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3836
+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3837
+
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3838
+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3839
+
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3840
+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3841
+
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3842
+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3843
+
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3844
+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3845
+
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3846
+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3847
+
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3848
+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3849
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3850
+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3851
+
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3852
+
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3853
+
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3854
+
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3855
+
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3856
+
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3857
+
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3858
+
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3859
+
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3860
+
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3861
+
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3862
+
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3863
+
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3864
+
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3865
+
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3866
+
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3867
+
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3868
+
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3869
+
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3870
+
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3871
+
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3872
+
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3873
+
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3874
+
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3875
+
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3876
+
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3877
+
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3878
+
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3879
+
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3880
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3881
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3882
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3883
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3884
+
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3885
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3886
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3887
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3888
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3889
+
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3890
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3891
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3892
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3893
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3894
+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3895
+
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3896
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3897
+
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3898
+
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3899
+
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3900
+
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3901
+
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3902
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3903
+
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3904
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3905
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3906
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3907
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3908
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3909
+
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
3926
3910
};
3927
3911
3928
3912
intc: interrupt-controller@17100000 {
···
4136
4120
ufs_mem_hc: ufshc@1d84000 {
4137
4121
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4138
4122
"jedec,ufs-2.0";
4139
-
reg = <0 0x01d84000 0 0x3000>,
4140
-
<0 0x01d88000 0 0x8000>;
4141
-
reg-names = "std", "ice";
4123
+
reg = <0 0x01d84000 0 0x3000>;
4142
4124
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4143
4125
phys = <&ufs_mem_phy_lanes>;
4144
4126
phy-names = "ufsphy";
···
4161
4147
"ref_clk",
4162
4148
"tx_lane0_sync_clk",
4163
4149
"rx_lane0_sync_clk",
4164
-
"rx_lane1_sync_clk",
4165
-
"ice_core_clk";
4150
+
"rx_lane1_sync_clk";
4166
4151
clocks =
4167
4152
<&gcc GCC_UFS_PHY_AXI_CLK>,
4168
4153
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
···
4170
4157
<&rpmhcc RPMH_CXO_CLK>,
4171
4158
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4172
4159
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4173
-
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
4174
-
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4160
+
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4175
4161
freq-table-hz =
4176
4162
<75000000 300000000>,
4177
4163
<0 0>,
···
4179
4167
<75000000 300000000>,
4180
4168
<0 0>,
4181
4169
<0 0>,
4182
-
<0 0>,
4183
-
<75000000 300000000>;
4170
+
<0 0>;
4171
+
qcom,ice = <&ice>;
4172
+
4184
4173
status = "disabled";
4185
4174
};
4186
4175
···
4211
4198
};
4212
4199
};
4213
4200
4201
+
ice: crypto@1d88000 {
4202
+
compatible = "qcom,sm8450-inline-crypto-engine",
4203
+
"qcom,inline-crypto-engine";
4204
+
reg = <0 0x01d88000 0 0x8000>;
4205
+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4206
+
};
4207
+
4214
4208
cryptobam: dma-controller@1dc4000 {
4215
4209
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4216
4210
reg = <0 0x01dc4000 0 0x28000>;
···
4232
4212
<&apps_smmu 0x59f 0x0>;
4233
4213
};
4234
4214
4235
-
crypto: crypto@1de0000 {
4215
+
crypto: crypto@1dfa000 {
4236
4216
compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4237
4217
reg = <0 0x01dfa000 0 0x6000>;
4238
4218
dmas = <&cryptobam 4>, <&cryptobam 5>;
···
4263
4243
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4264
4244
interconnect-names = "sdhc-ddr","cpu-sdhc";
4265
4245
iommus = <&apps_smmu 0x4a0 0x0>;
4266
-
power-domains = <&rpmhpd SM8450_CX>;
4246
+
power-domains = <&rpmhpd RPMHPD_CX>;
4267
4247
operating-points-v2 = <&sdhc2_opp_table>;
4268
4248
bus-width = <4>;
4269
4249
dma-coherent;
+59
-2
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+59
-2
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
···
18
18
/ {
19
19
model = "Qualcomm Technologies, Inc. SM8550 MTP";
20
20
compatible = "qcom,sm8550-mtp", "qcom,sm8550";
21
+
chassis-type = "handset";
21
22
22
23
aliases {
23
24
serial0 = &uart7;
···
81
80
reg = <1>;
82
81
83
82
pmic_glink_ss_in: endpoint {
84
-
remote-endpoint = <&usb_1_dwc3_ss>;
83
+
remote-endpoint = <&usb_dp_qmpphy_out>;
84
+
};
85
+
};
86
+
87
+
port@2 {
88
+
reg = <2>;
89
+
90
+
pmic_glink_sbu: endpoint {
91
+
remote-endpoint = <&fsa4480_sbu_mux>;
85
92
};
86
93
};
87
94
};
···
195
186
196
187
vdd-bob1-supply = <&vph_pwr>;
197
188
vdd-bob2-supply = <&vph_pwr>;
189
+
vdd-l1-l4-l10-supply = <&vreg_s6g_1p8>;
198
190
vdd-l2-l13-l14-supply = <&vreg_bob1>;
199
191
vdd-l3-supply = <&vreg_s4g_1p3>;
200
192
vdd-l5-l16-supply = <&vreg_bob1>;
···
510
500
};
511
501
};
512
502
503
+
&i2c_master_hub_0 {
504
+
status = "okay";
505
+
};
506
+
507
+
&i2c_hub_2 {
508
+
status = "okay";
509
+
510
+
typec-mux@42 {
511
+
compatible = "fcs,fsa4480";
512
+
reg = <0x42>;
513
+
514
+
vcc-supply = <&vreg_bob1>;
515
+
516
+
mode-switch;
517
+
orientation-switch;
518
+
519
+
port {
520
+
fsa4480_sbu_mux: endpoint {
521
+
remote-endpoint = <&pmic_glink_sbu>;
522
+
};
523
+
};
524
+
};
525
+
};
526
+
513
527
&lpass_tlmm {
514
528
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
515
529
pins = "gpio17";
···
590
556
&mdss_dsi0_phy {
591
557
vdds-supply = <&vreg_l1e_0p88>;
592
558
status = "okay";
559
+
};
560
+
561
+
&mdss_dp0 {
562
+
status = "okay";
563
+
};
564
+
565
+
&mdss_dp0_out {
566
+
data-lanes = <0 1>;
567
+
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
593
568
};
594
569
595
570
&pcie_1_phy_aux_clk {
···
824
781
};
825
782
826
783
&usb_1_dwc3_ss {
827
-
remote-endpoint = <&pmic_glink_ss_in>;
784
+
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
828
785
};
829
786
830
787
&usb_1_hsphy {
···
840
797
vdda-phy-supply = <&vreg_l3e_1p2>;
841
798
vdda-pll-supply = <&vreg_l3f_0p91>;
842
799
800
+
orientation-switch;
801
+
843
802
status = "okay";
803
+
};
804
+
805
+
&usb_dp_qmpphy_dp_in {
806
+
remote-endpoint = <&mdss_dp0_out>;
807
+
};
808
+
809
+
&usb_dp_qmpphy_out {
810
+
remote-endpoint = <&pmic_glink_ss_in>;
811
+
};
812
+
813
+
&usb_dp_qmpphy_usb_ss_in {
814
+
remote-endpoint = <&usb_1_dwc3_ss>;
844
815
};
845
816
846
817
&xo_board {
+90
-2
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+90
-2
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
···
19
19
/ {
20
20
model = "Qualcomm Technologies, Inc. SM8550 QRD";
21
21
compatible = "qcom,sm8550-qrd", "qcom,sm8550";
22
+
chassis-type = "handset";
22
23
23
24
aliases {
24
25
serial0 = &uart7;
···
98
97
reg = <1>;
99
98
100
99
pmic_glink_ss_in: endpoint {
101
-
remote-endpoint = <&usb_1_dwc3_ss>;
100
+
remote-endpoint = <&redriver_ss_out>;
101
+
};
102
+
};
103
+
104
+
port@2 {
105
+
reg = <2>;
106
+
107
+
pmic_glink_sbu: endpoint {
108
+
remote-endpoint = <&fsa4480_sbu_mux>;
102
109
};
103
110
};
104
111
};
···
526
517
};
527
518
};
528
519
520
+
&i2c_master_hub_0 {
521
+
status = "okay";
522
+
};
523
+
524
+
&i2c_hub_2 {
525
+
status = "okay";
526
+
527
+
typec-retimer@1c {
528
+
compatible = "onnn,nb7vpq904m";
529
+
reg = <0x1c>;
530
+
531
+
vcc-supply = <&vreg_l15b_1p8>;
532
+
533
+
retimer-switch;
534
+
orientation-switch;
535
+
536
+
ports {
537
+
#address-cells = <1>;
538
+
#size-cells = <0>;
539
+
540
+
port@0 {
541
+
reg = <0>;
542
+
543
+
redriver_ss_out: endpoint {
544
+
remote-endpoint = <&pmic_glink_ss_in>;
545
+
};
546
+
};
547
+
548
+
port@1 {
549
+
reg = <1>;
550
+
551
+
redriver_ss_in: endpoint {
552
+
data-lanes = <3 2 1 0>;
553
+
remote-endpoint = <&usb_dp_qmpphy_out>;
554
+
};
555
+
};
556
+
};
557
+
};
558
+
559
+
typec-mux@42 {
560
+
compatible = "fcs,fsa4480";
561
+
reg = <0x42>;
562
+
563
+
vcc-supply = <&vreg_bob1>;
564
+
565
+
mode-switch;
566
+
orientation-switch;
567
+
568
+
port {
569
+
fsa4480_sbu_mux: endpoint {
570
+
remote-endpoint = <&pmic_glink_sbu>;
571
+
};
572
+
};
573
+
};
574
+
};
575
+
529
576
&gcc {
530
577
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
531
578
<&pcie0_phy>,
···
649
584
&mdss_dsi0_phy {
650
585
vdds-supply = <&vreg_l1e_0p88>;
651
586
status = "okay";
587
+
};
588
+
589
+
&mdss_dp0 {
590
+
status = "okay";
591
+
};
592
+
593
+
&mdss_dp0_out {
594
+
data-lanes = <0 1>;
595
+
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
652
596
};
653
597
654
598
&pcie_1_phy_aux_clk {
···
916
842
};
917
843
918
844
&usb_1_dwc3_ss {
919
-
remote-endpoint = <&pmic_glink_ss_in>;
845
+
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
920
846
};
921
847
922
848
&usb_1_hsphy {
···
932
858
vdda-phy-supply = <&vreg_l3e_1p2>;
933
859
vdda-pll-supply = <&vreg_l3f_0p88>;
934
860
861
+
orientation-switch;
862
+
935
863
status = "okay";
864
+
};
865
+
866
+
&usb_dp_qmpphy_dp_in {
867
+
remote-endpoint = <&mdss_dp0_out>;
868
+
};
869
+
870
+
&usb_dp_qmpphy_out {
871
+
remote-endpoint = <&redriver_ss_in>;
872
+
};
873
+
874
+
&usb_dp_qmpphy_usb_ss_in {
875
+
remote-endpoint = <&usb_1_dwc3_ss>;
936
876
};
937
877
938
878
&xo_board {
+139
-112
arch/arm64/boot/dts/qcom/sm8550.dtsi
+139
-112
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
15
15
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
16
16
#include <dt-bindings/mailbox/qcom-ipcc.h>
17
17
#include <dt-bindings/power/qcom-rpmpd.h>
18
+
#include <dt-bindings/power/qcom,rpmhpd.h>
18
19
#include <dt-bindings/soc/qcom,gpr.h>
19
20
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20
21
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
···
1601
1600
pinctrl-0 = <&qup_uart7_default>;
1602
1601
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1603
1602
interconnect-names = "qup-core", "qup-config";
1604
-
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1603
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605
1604
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1606
1605
status = "disabled";
1607
1606
};
···
1990
1989
clocks = <&rpmhcc RPMH_CXO_CLK>;
1991
1990
clock-names = "xo";
1992
1991
1993
-
power-domains = <&rpmhpd SM8550_CX>,
1994
-
<&rpmhpd SM8550_MSS>;
1992
+
power-domains = <&rpmhpd RPMHPD_CX>,
1993
+
<&rpmhpd RPMHPD_MSS>;
1995
1994
power-domain-names = "cx", "mss";
1996
1995
1997
1996
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
···
2369
2368
iommus = <&apps_smmu 0x540 0>;
2370
2369
qcom,dll-config = <0x0007642c>;
2371
2370
qcom,ddr-config = <0x80040868>;
2372
-
power-domains = <&rpmhpd SM8550_CX>;
2371
+
power-domains = <&rpmhpd RPMHPD_CX>;
2373
2372
operating-points-v2 = <&sdhc2_opp_table>;
2374
2373
2375
2374
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
···
2413
2412
reg = <0 0x0aaf0000 0 0x10000>;
2414
2413
clocks = <&bi_tcxo_div2>,
2415
2414
<&gcc GCC_VIDEO_AHB_CLK>;
2416
-
power-domains = <&rpmhpd SM8550_MMCX>;
2415
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2417
2416
required-opps = <&rpmhpd_opp_low_svs>;
2418
2417
#clock-cells = <1>;
2419
2418
#reset-cells = <1>;
···
2472
2471
"core",
2473
2472
"vsync";
2474
2473
2475
-
power-domains = <&rpmhpd SM8550_MMCX>;
2474
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2476
2475
2477
2476
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2478
2477
assigned-clock-rates = <19200000>;
···
2561
2560
#sound-dai-cells = <0>;
2562
2561
2563
2562
operating-points-v2 = <&dp_opp_table>;
2564
-
power-domains = <&rpmhpd SM8550_MMCX>;
2563
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2565
2564
2566
2565
status = "disabled";
2567
2566
···
2629
2628
"iface",
2630
2629
"bus";
2631
2630
2632
-
power-domains = <&rpmhpd SM8550_MMCX>;
2631
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2633
2632
2634
2633
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2635
2634
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
···
2724
2723
"iface",
2725
2724
"bus";
2726
2725
2727
-
power-domains = <&rpmhpd SM8550_MMCX>;
2726
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2728
2727
2729
2728
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2730
2729
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
···
2799
2798
<0>,
2800
2799
<0>, /* dp3 */
2801
2800
<0>;
2802
-
power-domains = <&rpmhpd SM8550_MMCX>;
2801
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
2803
2802
required-opps = <&rpmhpd_opp_low_svs>;
2804
2803
#clock-cells = <1>;
2805
2804
#reset-cells = <1>;
···
2839
2838
#phy-cells = <1>;
2840
2839
2841
2840
status = "disabled";
2841
+
2842
+
ports {
2843
+
#address-cells = <1>;
2844
+
#size-cells = <0>;
2845
+
2846
+
port@0 {
2847
+
reg = <0>;
2848
+
2849
+
usb_dp_qmpphy_out: endpoint {
2850
+
};
2851
+
};
2852
+
2853
+
port@1 {
2854
+
reg = <1>;
2855
+
2856
+
usb_dp_qmpphy_usb_ss_in: endpoint {
2857
+
};
2858
+
};
2859
+
2860
+
port@2 {
2861
+
reg = <2>;
2862
+
2863
+
usb_dp_qmpphy_dp_in: endpoint {
2864
+
};
2865
+
};
2866
+
};
2842
2867
};
2843
2868
2844
2869
usb_1: usb@a6f8800 {
···
3544
3517
reg = <0 0x15000000 0 0x100000>;
3545
3518
#iommu-cells = <2>;
3546
3519
#global-interrupts = <1>;
3547
-
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548
-
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3549
-
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3550
-
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3551
-
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3552
-
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3553
-
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3554
-
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3555
-
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3556
-
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3557
-
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3558
-
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3559
-
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3560
-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3561
-
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3562
-
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3563
-
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3564
-
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3565
-
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3566
-
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3567
-
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3568
-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3569
-
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3570
-
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3571
-
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3572
-
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3573
-
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3574
-
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3575
-
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3576
-
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3577
-
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3578
-
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3579
-
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3580
-
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3581
-
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3582
-
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3583
-
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3584
-
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3585
-
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3586
-
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3587
-
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3588
-
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3589
-
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3590
-
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3591
-
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3592
-
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3593
-
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3594
-
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3595
-
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3596
-
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3597
-
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3598
-
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3599
-
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3600
-
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3601
-
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3602
-
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3603
-
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3604
-
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3605
-
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3606
-
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3607
-
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3608
-
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3609
-
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3610
-
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3611
-
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3612
-
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3613
-
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3614
-
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3615
-
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3616
-
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3617
-
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3618
-
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3619
-
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3620
-
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3621
-
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3622
-
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3623
-
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3624
-
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3625
-
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3626
-
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3627
-
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3628
-
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3629
-
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3630
-
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3631
-
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3632
-
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3633
-
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3634
-
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3635
-
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3636
-
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3637
-
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3638
-
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3639
-
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3640
-
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3641
-
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3642
-
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3643
-
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3520
+
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3521
+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3522
+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3523
+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3524
+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3525
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3526
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3527
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3528
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3529
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3530
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3531
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3532
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3533
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3534
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3535
+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3536
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3537
+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3538
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3539
+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3540
+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3541
+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3542
+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3543
+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3544
+
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3545
+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3546
+
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3547
+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3548
+
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3549
+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3550
+
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3551
+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3552
+
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3553
+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3554
+
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3555
+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3556
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3557
+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3558
+
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3559
+
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3560
+
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3561
+
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3562
+
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3563
+
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3564
+
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3565
+
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3566
+
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3567
+
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3568
+
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3569
+
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3570
+
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3571
+
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3572
+
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3573
+
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3574
+
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3575
+
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3576
+
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3577
+
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3578
+
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3579
+
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3580
+
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3581
+
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3582
+
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3583
+
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3584
+
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3585
+
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3586
+
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3587
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3588
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3589
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3590
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3591
+
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3592
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3593
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3594
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3595
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3596
+
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3597
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3598
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3599
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3600
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3601
+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3602
+
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3603
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3604
+
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3605
+
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3606
+
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3607
+
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3608
+
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3609
+
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3610
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3611
+
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3612
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3613
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3614
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3615
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3616
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3644
3617
};
3645
3618
3646
3619
intc: interrupt-controller@17100000 {
···
3960
3933
clocks = <&rpmhcc RPMH_CXO_CLK>;
3961
3934
clock-names = "xo";
3962
3935
3963
-
power-domains = <&rpmhpd SM8550_LCX>,
3964
-
<&rpmhpd SM8550_LMX>;
3936
+
power-domains = <&rpmhpd RPMHPD_LCX>,
3937
+
<&rpmhpd RPMHPD_LMX>;
3965
3938
power-domain-names = "lcx", "lmx";
3966
3939
3967
3940
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
···
4092
4065
clocks = <&rpmhcc RPMH_CXO_CLK>;
4093
4066
clock-names = "xo";
4094
4067
4095
-
power-domains = <&rpmhpd SM8550_CX>,
4096
-
<&rpmhpd SM8550_MXC>,
4097
-
<&rpmhpd SM8550_NSP>;
4068
+
power-domains = <&rpmhpd RPMHPD_CX>,
4069
+
<&rpmhpd RPMHPD_MXC>,
4070
+
<&rpmhpd RPMHPD_NSP>;
4098
4071
power-domain-names = "cx", "mxc", "nsp";
4099
4072
4100
4073
interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+183
include/dt-bindings/clock/qcom,gcc-ipq5018.h
+183
include/dt-bindings/clock/qcom,gcc-ipq5018.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
7
+
#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
8
+
9
+
#define GPLL0_MAIN 0
10
+
#define GPLL0 1
11
+
#define GPLL2_MAIN 2
12
+
#define GPLL2 3
13
+
#define GPLL4_MAIN 4
14
+
#define GPLL4 5
15
+
#define UBI32_PLL_MAIN 6
16
+
#define UBI32_PLL 7
17
+
#define ADSS_PWM_CLK_SRC 8
18
+
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9
19
+
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10
20
+
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11
21
+
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12
22
+
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13
23
+
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14
24
+
#define BLSP1_UART1_APPS_CLK_SRC 15
25
+
#define BLSP1_UART2_APPS_CLK_SRC 16
26
+
#define CRYPTO_CLK_SRC 17
27
+
#define GCC_ADSS_PWM_CLK 18
28
+
#define GCC_BLSP1_AHB_CLK 19
29
+
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20
30
+
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21
31
+
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22
32
+
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23
33
+
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24
34
+
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25
35
+
#define GCC_BLSP1_UART1_APPS_CLK 26
36
+
#define GCC_BLSP1_UART2_APPS_CLK 27
37
+
#define GCC_BTSS_LPO_CLK 28
38
+
#define GCC_CMN_BLK_AHB_CLK 29
39
+
#define GCC_CMN_BLK_SYS_CLK 30
40
+
#define GCC_CRYPTO_AHB_CLK 31
41
+
#define GCC_CRYPTO_AXI_CLK 32
42
+
#define GCC_CRYPTO_CLK 33
43
+
#define GCC_CRYPTO_PPE_CLK 34
44
+
#define GCC_DCC_CLK 35
45
+
#define GCC_GEPHY_RX_CLK 36
46
+
#define GCC_GEPHY_TX_CLK 37
47
+
#define GCC_GMAC0_CFG_CLK 38
48
+
#define GCC_GMAC0_PTP_CLK 39
49
+
#define GCC_GMAC0_RX_CLK 40
50
+
#define GCC_GMAC0_SYS_CLK 41
51
+
#define GCC_GMAC0_TX_CLK 42
52
+
#define GCC_GMAC1_CFG_CLK 43
53
+
#define GCC_GMAC1_PTP_CLK 44
54
+
#define GCC_GMAC1_RX_CLK 45
55
+
#define GCC_GMAC1_SYS_CLK 46
56
+
#define GCC_GMAC1_TX_CLK 47
57
+
#define GCC_GP1_CLK 48
58
+
#define GCC_GP2_CLK 49
59
+
#define GCC_GP3_CLK 50
60
+
#define GCC_LPASS_CORE_AXIM_CLK 51
61
+
#define GCC_LPASS_SWAY_CLK 52
62
+
#define GCC_MDIO0_AHB_CLK 53
63
+
#define GCC_MDIO1_AHB_CLK 54
64
+
#define GCC_PCIE0_AHB_CLK 55
65
+
#define GCC_PCIE0_AUX_CLK 56
66
+
#define GCC_PCIE0_AXI_M_CLK 57
67
+
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58
68
+
#define GCC_PCIE0_AXI_S_CLK 59
69
+
#define GCC_PCIE0_PIPE_CLK 60
70
+
#define GCC_PCIE1_AHB_CLK 61
71
+
#define GCC_PCIE1_AUX_CLK 62
72
+
#define GCC_PCIE1_AXI_M_CLK 63
73
+
#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64
74
+
#define GCC_PCIE1_AXI_S_CLK 65
75
+
#define GCC_PCIE1_PIPE_CLK 66
76
+
#define GCC_PRNG_AHB_CLK 67
77
+
#define GCC_Q6_AXIM_CLK 68
78
+
#define GCC_Q6_AXIM2_CLK 69
79
+
#define GCC_Q6_AXIS_CLK 70
80
+
#define GCC_Q6_AHB_CLK 71
81
+
#define GCC_Q6_AHB_S_CLK 72
82
+
#define GCC_Q6_TSCTR_1TO2_CLK 73
83
+
#define GCC_Q6SS_ATBM_CLK 74
84
+
#define GCC_Q6SS_PCLKDBG_CLK 75
85
+
#define GCC_Q6SS_TRIG_CLK 76
86
+
#define GCC_QDSS_AT_CLK 77
87
+
#define GCC_QDSS_CFG_AHB_CLK 78
88
+
#define GCC_QDSS_DAP_AHB_CLK 79
89
+
#define GCC_QDSS_DAP_CLK 80
90
+
#define GCC_QDSS_ETR_USB_CLK 81
91
+
#define GCC_QDSS_EUD_AT_CLK 82
92
+
#define GCC_QDSS_STM_CLK 83
93
+
#define GCC_QDSS_TRACECLKIN_CLK 84
94
+
#define GCC_QDSS_TSCTR_DIV8_CLK 85
95
+
#define GCC_QPIC_AHB_CLK 86
96
+
#define GCC_QPIC_CLK 87
97
+
#define GCC_QPIC_IO_MACRO_CLK 88
98
+
#define GCC_SDCC1_AHB_CLK 89
99
+
#define GCC_SDCC1_APPS_CLK 90
100
+
#define GCC_SLEEP_CLK_SRC 91
101
+
#define GCC_SNOC_GMAC0_AHB_CLK 92
102
+
#define GCC_SNOC_GMAC0_AXI_CLK 93
103
+
#define GCC_SNOC_GMAC1_AHB_CLK 94
104
+
#define GCC_SNOC_GMAC1_AXI_CLK 95
105
+
#define GCC_SNOC_LPASS_AXIM_CLK 96
106
+
#define GCC_SNOC_LPASS_SWAY_CLK 97
107
+
#define GCC_SNOC_UBI0_AXI_CLK 98
108
+
#define GCC_SYS_NOC_PCIE0_AXI_CLK 99
109
+
#define GCC_SYS_NOC_PCIE1_AXI_CLK 100
110
+
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101
111
+
#define GCC_SYS_NOC_USB0_AXI_CLK 102
112
+
#define GCC_SYS_NOC_WCSS_AHB_CLK 103
113
+
#define GCC_UBI0_AXI_CLK 104
114
+
#define GCC_UBI0_CFG_CLK 105
115
+
#define GCC_UBI0_CORE_CLK 106
116
+
#define GCC_UBI0_DBG_CLK 107
117
+
#define GCC_UBI0_NC_AXI_CLK 108
118
+
#define GCC_UBI0_UTCM_CLK 109
119
+
#define GCC_UNIPHY_AHB_CLK 110
120
+
#define GCC_UNIPHY_RX_CLK 111
121
+
#define GCC_UNIPHY_SYS_CLK 112
122
+
#define GCC_UNIPHY_TX_CLK 113
123
+
#define GCC_USB0_AUX_CLK 114
124
+
#define GCC_USB0_EUD_AT_CLK 115
125
+
#define GCC_USB0_LFPS_CLK 116
126
+
#define GCC_USB0_MASTER_CLK 117
127
+
#define GCC_USB0_MOCK_UTMI_CLK 118
128
+
#define GCC_USB0_PHY_CFG_AHB_CLK 119
129
+
#define GCC_USB0_SLEEP_CLK 120
130
+
#define GCC_WCSS_ACMT_CLK 121
131
+
#define GCC_WCSS_AHB_S_CLK 122
132
+
#define GCC_WCSS_AXI_M_CLK 123
133
+
#define GCC_WCSS_AXI_S_CLK 124
134
+
#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125
135
+
#define GCC_WCSS_DBG_IFC_APB_CLK 126
136
+
#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127
137
+
#define GCC_WCSS_DBG_IFC_ATB_CLK 128
138
+
#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129
139
+
#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130
140
+
#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131
141
+
#define GCC_WCSS_DBG_IFC_NTS_CLK 132
142
+
#define GCC_WCSS_ECAHB_CLK 133
143
+
#define GCC_XO_CLK 134
144
+
#define GCC_XO_CLK_SRC 135
145
+
#define GMAC0_RX_CLK_SRC 136
146
+
#define GMAC0_TX_CLK_SRC 137
147
+
#define GMAC1_RX_CLK_SRC 138
148
+
#define GMAC1_TX_CLK_SRC 139
149
+
#define GMAC_CLK_SRC 140
150
+
#define GP1_CLK_SRC 141
151
+
#define GP2_CLK_SRC 142
152
+
#define GP3_CLK_SRC 143
153
+
#define LPASS_AXIM_CLK_SRC 144
154
+
#define LPASS_SWAY_CLK_SRC 145
155
+
#define PCIE0_AUX_CLK_SRC 146
156
+
#define PCIE0_AXI_CLK_SRC 147
157
+
#define PCIE1_AUX_CLK_SRC 148
158
+
#define PCIE1_AXI_CLK_SRC 149
159
+
#define PCNOC_BFDCD_CLK_SRC 150
160
+
#define Q6_AXI_CLK_SRC 151
161
+
#define QDSS_AT_CLK_SRC 152
162
+
#define QDSS_STM_CLK_SRC 153
163
+
#define QDSS_TSCTR_CLK_SRC 154
164
+
#define QDSS_TRACECLKIN_CLK_SRC 155
165
+
#define QPIC_IO_MACRO_CLK_SRC 156
166
+
#define SDCC1_APPS_CLK_SRC 157
167
+
#define SYSTEM_NOC_BFDCD_CLK_SRC 158
168
+
#define UBI0_AXI_CLK_SRC 159
169
+
#define UBI0_CORE_CLK_SRC 160
170
+
#define USB0_AUX_CLK_SRC 161
171
+
#define USB0_LFPS_CLK_SRC 162
172
+
#define USB0_MASTER_CLK_SRC 163
173
+
#define USB0_MOCK_UTMI_CLK_SRC 164
174
+
#define WCSS_AHB_CLK_SRC 165
175
+
#define PCIE0_PIPE_CLK_SRC 166
176
+
#define PCIE1_PIPE_CLK_SRC 167
177
+
#define USB0_PIPE_CLK_SRC 168
178
+
#define GCC_USB0_PIPE_CLK 169
179
+
#define GMAC0_RX_DIV_CLK_SRC 170
180
+
#define GMAC0_TX_DIV_CLK_SRC 171
181
+
#define GMAC1_RX_DIV_CLK_SRC 172
182
+
#define GMAC1_TX_DIV_CLK_SRC 173
183
+
#endif
+3
include/dt-bindings/clock/qcom,gcc-msm8998.h
+3
include/dt-bindings/clock/qcom,gcc-msm8998.h
+10
include/dt-bindings/clock/qcom,gcc-sc8280xp.h
+10
include/dt-bindings/clock/qcom,gcc-sc8280xp.h
···
494
494
#define USB30_SEC_GDSC 11
495
495
#define EMAC_0_GDSC 12
496
496
#define EMAC_1_GDSC 13
497
+
#define USB4_1_GDSC 14
498
+
#define USB4_GDSC 15
499
+
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 16
500
+
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 17
501
+
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 18
502
+
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 19
503
+
#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 20
504
+
#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 21
505
+
#define HLOS1_VOTE_TURING_MMU_TBU2_GDSC 22
506
+
#define HLOS1_VOTE_TURING_MMU_TBU3_GDSC 23
497
507
498
508
#endif
+2
include/dt-bindings/clock/qcom,ipq9574-gcc.h
+2
include/dt-bindings/clock/qcom,ipq9574-gcc.h
+30
include/dt-bindings/power/qcom,rpmhpd.h
+30
include/dt-bindings/power/qcom,rpmhpd.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_POWER_QCOM_RPMHPD_H
7
+
#define _DT_BINDINGS_POWER_QCOM_RPMHPD_H
8
+
9
+
/* Generic RPMH Power Domain Indexes */
10
+
#define RPMHPD_CX 0
11
+
#define RPMHPD_CX_AO 1
12
+
#define RPMHPD_EBI 2
13
+
#define RPMHPD_GFX 3
14
+
#define RPMHPD_LCX 4
15
+
#define RPMHPD_LMX 5
16
+
#define RPMHPD_MMCX 6
17
+
#define RPMHPD_MMCX_AO 7
18
+
#define RPMHPD_MX 8
19
+
#define RPMHPD_MX_AO 9
20
+
#define RPMHPD_MXC 10
21
+
#define RPMHPD_MXC_AO 11
22
+
#define RPMHPD_MSS 12
23
+
#define RPMHPD_NSP 13
24
+
#define RPMHPD_NSP0 14
25
+
#define RPMHPD_NSP1 15
26
+
#define RPMHPD_QPHY 16
27
+
#define RPMHPD_DDR 17
28
+
#define RPMHPD_XO 18
29
+
30
+
#endif
+122
include/dt-bindings/reset/qcom,gcc-ipq5018.h
+122
include/dt-bindings/reset/qcom,gcc-ipq5018.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
7
+
#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
8
+
9
+
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0
10
+
#define GCC_BLSP1_BCR 1
11
+
#define GCC_BLSP1_QUP1_BCR 2
12
+
#define GCC_BLSP1_QUP2_BCR 3
13
+
#define GCC_BLSP1_QUP3_BCR 4
14
+
#define GCC_BLSP1_UART1_BCR 5
15
+
#define GCC_BLSP1_UART2_BCR 6
16
+
#define GCC_BOOT_ROM_BCR 7
17
+
#define GCC_BTSS_BCR 8
18
+
#define GCC_CMN_BLK_BCR 9
19
+
#define GCC_CMN_LDO_BCR 10
20
+
#define GCC_CE_BCR 11
21
+
#define GCC_CRYPTO_BCR 12
22
+
#define GCC_DCC_BCR 13
23
+
#define GCC_DCD_BCR 14
24
+
#define GCC_DDRSS_BCR 15
25
+
#define GCC_EDPD_BCR 16
26
+
#define GCC_GEPHY_BCR 17
27
+
#define GCC_GEPHY_MDC_SW_ARES 18
28
+
#define GCC_GEPHY_DSP_HW_ARES 19
29
+
#define GCC_GEPHY_RX_ARES 20
30
+
#define GCC_GEPHY_TX_ARES 21
31
+
#define GCC_GMAC0_BCR 22
32
+
#define GCC_GMAC0_CFG_ARES 23
33
+
#define GCC_GMAC0_SYS_ARES 24
34
+
#define GCC_GMAC1_BCR 25
35
+
#define GCC_GMAC1_CFG_ARES 26
36
+
#define GCC_GMAC1_SYS_ARES 27
37
+
#define GCC_IMEM_BCR 28
38
+
#define GCC_LPASS_BCR 29
39
+
#define GCC_MDIO0_BCR 30
40
+
#define GCC_MDIO1_BCR 31
41
+
#define GCC_MPM_BCR 32
42
+
#define GCC_PCIE0_BCR 33
43
+
#define GCC_PCIE0_LINK_DOWN_BCR 34
44
+
#define GCC_PCIE0_PHY_BCR 35
45
+
#define GCC_PCIE0PHY_PHY_BCR 36
46
+
#define GCC_PCIE0_PIPE_ARES 37
47
+
#define GCC_PCIE0_SLEEP_ARES 38
48
+
#define GCC_PCIE0_CORE_STICKY_ARES 39
49
+
#define GCC_PCIE0_AXI_MASTER_ARES 40
50
+
#define GCC_PCIE0_AXI_SLAVE_ARES 41
51
+
#define GCC_PCIE0_AHB_ARES 42
52
+
#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43
53
+
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44
54
+
#define GCC_PCIE1_BCR 45
55
+
#define GCC_PCIE1_LINK_DOWN_BCR 46
56
+
#define GCC_PCIE1_PHY_BCR 47
57
+
#define GCC_PCIE1PHY_PHY_BCR 48
58
+
#define GCC_PCIE1_PIPE_ARES 49
59
+
#define GCC_PCIE1_SLEEP_ARES 50
60
+
#define GCC_PCIE1_CORE_STICKY_ARES 51
61
+
#define GCC_PCIE1_AXI_MASTER_ARES 52
62
+
#define GCC_PCIE1_AXI_SLAVE_ARES 53
63
+
#define GCC_PCIE1_AHB_ARES 54
64
+
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55
65
+
#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56
66
+
#define GCC_PCNOC_BCR 57
67
+
#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
68
+
#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
69
+
#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
70
+
#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
71
+
#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
72
+
#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
73
+
#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
74
+
#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
75
+
#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
76
+
#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
77
+
#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68
78
+
#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69
79
+
#define GCC_PRNG_BCR 70
80
+
#define GCC_Q6SS_DBG_ARES 71
81
+
#define GCC_Q6_AHB_S_ARES 72
82
+
#define GCC_Q6_AHB_ARES 73
83
+
#define GCC_Q6_AXIM2_ARES 74
84
+
#define GCC_Q6_AXIM_ARES 75
85
+
#define GCC_Q6_AXIS_ARES 76
86
+
#define GCC_QDSS_BCR 77
87
+
#define GCC_QPIC_BCR 78
88
+
#define GCC_QUSB2_0_PHY_BCR 79
89
+
#define GCC_SDCC1_BCR 80
90
+
#define GCC_SEC_CTRL_BCR 81
91
+
#define GCC_SPDM_BCR 82
92
+
#define GCC_SYSTEM_NOC_BCR 83
93
+
#define GCC_TCSR_BCR 84
94
+
#define GCC_TLMM_BCR 85
95
+
#define GCC_UBI0_AXI_ARES 86
96
+
#define GCC_UBI0_AHB_ARES 87
97
+
#define GCC_UBI0_NC_AXI_ARES 88
98
+
#define GCC_UBI0_DBG_ARES 89
99
+
#define GCC_UBI0_UTCM_ARES 90
100
+
#define GCC_UBI0_CORE_ARES 91
101
+
#define GCC_UBI32_BCR 92
102
+
#define GCC_UNIPHY_BCR 93
103
+
#define GCC_UNIPHY_AHB_ARES 94
104
+
#define GCC_UNIPHY_SYS_ARES 95
105
+
#define GCC_UNIPHY_RX_ARES 96
106
+
#define GCC_UNIPHY_TX_ARES 97
107
+
#define GCC_USB0_BCR 98
108
+
#define GCC_USB0_PHY_BCR 99
109
+
#define GCC_WCSS_BCR 100
110
+
#define GCC_WCSS_DBG_ARES 101
111
+
#define GCC_WCSS_ECAHB_ARES 102
112
+
#define GCC_WCSS_ACMT_ARES 103
113
+
#define GCC_WCSS_DBG_BDG_ARES 104
114
+
#define GCC_WCSS_AHB_S_ARES 105
115
+
#define GCC_WCSS_AXI_M_ARES 106
116
+
#define GCC_WCSS_AXI_S_ARES 107
117
+
#define GCC_WCSS_Q6_BCR 108
118
+
#define GCC_WCSSAON_RESET 109
119
+
#define GCC_UNIPHY_SOFT_RESET 110
120
+
#define GCC_GEPHY_MISC_ARES 111
121
+
122
+
#endif