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ARM: at91: remove default values for PMC_PLL_ACR

Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL and load them from PLL
characteristics structure

Co-developed-by: Andrei Simion <andrei.simion@microchip.com>
Signed-off-by: Andrei Simion <andrei.simion@microchip.com>
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
[nicolas.ferre@microchip.com: fix pll acr write sequence, preserve val]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>

authored by

Cristian Birsan and committed by
Nicolas Ferre 652b08af bfa2bddf

+2 -7
+2 -5
drivers/clk/at91/clk-sam9x60-pll.c
··· 103 103 (cmul == frac->mul && cfrac == frac->frac)) 104 104 goto unlock; 105 105 106 - /* Recommended value for PMC_PLL_ACR */ 107 - if (core->characteristics->upll) 108 - val = AT91_PMC_PLL_ACR_DEFAULT_UPLL; 109 - else 110 - val = AT91_PMC_PLL_ACR_DEFAULT_PLLA; 106 + /* Load recommended value for PMC_PLL_ACR */ 107 + val = core->characteristics->acr; 111 108 regmap_write(regmap, AT91_PMC_PLL_ACR, val); 112 109 113 110 regmap_write(regmap, AT91_PMC_PLL_CTRL1,
-2
include/linux/clk/at91_pmc.h
··· 47 47 #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 48 48 49 49 #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ 50 - #define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */ 51 - #define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */ 52 50 #define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ 53 51 #define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ 54 52