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clk: qcom: gcc-sm6115: Move alpha pll bramo overrides

sm6115 uses a modified default and bramo alpha pll offsets. Put them in
the same place for consistency.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-3-iskren.chernev@gmail.com

authored by

Iskren Chernev and committed by
Bjorn Andersson
65f1fa35 068a0605

+12 -14
+12 -14
drivers/clk/qcom/gcc-sm6115.c
··· 65 65 [PLL_OFF_CONFIG_CTL] = 0x20, 66 66 [PLL_OFF_STATUS] = 0x24, 67 67 }, 68 + [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 69 + [PLL_OFF_L_VAL] = 0x04, 70 + [PLL_OFF_ALPHA_VAL] = 0x08, 71 + [PLL_OFF_ALPHA_VAL_U] = 0x0c, 72 + [PLL_OFF_TEST_CTL] = 0x10, 73 + [PLL_OFF_TEST_CTL_U] = 0x14, 74 + [PLL_OFF_USER_CTL] = 0x18, 75 + [PLL_OFF_CONFIG_CTL] = 0x1C, 76 + [PLL_OFF_STATUS] = 0x20, 77 + }, 68 78 }; 69 79 70 80 static struct clk_alpha_pll gpll0 = { ··· 114 104 .num_parents = 1, 115 105 .ops = &clk_alpha_pll_postdiv_ro_ops, 116 106 }, 117 - }; 118 - 119 - /* listed as BRAMMO, but it doesn't really match */ 120 - static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = { 121 - [PLL_OFF_L_VAL] = 0x04, 122 - [PLL_OFF_ALPHA_VAL] = 0x08, 123 - [PLL_OFF_ALPHA_VAL_U] = 0x0c, 124 - [PLL_OFF_TEST_CTL] = 0x10, 125 - [PLL_OFF_TEST_CTL_U] = 0x14, 126 - [PLL_OFF_USER_CTL] = 0x18, 127 - [PLL_OFF_CONFIG_CTL] = 0x1C, 128 - [PLL_OFF_STATUS] = 0x20, 129 107 }; 130 108 131 109 static const struct clk_div_table post_div_table_gpll0_out_main[] = { ··· 443 445 .offset = 0x9000, 444 446 .vco_table = gpll9_vco, 445 447 .num_vco = ARRAY_SIZE(gpll9_vco), 446 - .regs = clk_gpll9_regs, 448 + .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 447 449 .clkr = { 448 450 .enable_reg = 0x79000, 449 451 .enable_mask = BIT(9), ··· 469 471 .post_div_table = post_div_table_gpll9_out_main, 470 472 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 471 473 .width = 2, 472 - .regs = clk_gpll9_regs, 474 + .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 473 475 .clkr.hw.init = &(struct clk_init_data){ 474 476 .name = "gpll9_out_main", 475 477 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },