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x86/bugs: Make sure MSR_SPEC_CTRL is updated properly upon resume from S3

The "force" argument to write_spec_ctrl_current() is currently ambiguous
as it does not guarantee the MSR write. This is due to the optimization
that writes to the MSR happen only when the new value differs from the
cached value.

This is fine in most cases, but breaks for S3 resume when the cached MSR
value gets out of sync with the hardware MSR value due to S3 resetting
it.

When x86_spec_ctrl_current is same as x86_spec_ctrl_base, the MSR write
is skipped. Which results in SPEC_CTRL mitigations not getting restored.

Move the MSR write from write_spec_ctrl_current() to a new function that
unconditionally writes to the MSR. Update the callers accordingly and
rename functions.

[ bp: Rework a bit. ]

Fixes: caa0ff24d5d0 ("x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value")
Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/806d39b0bfec2fe8f50dc5446dff20f5bb24a959.1669821572.git.pawan.kumar.gupta@linux.intel.com
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

Pawan Gupta and committed by
Linus Torvalds 66065157 a1e9185d

+16 -9
+1 -1
arch/x86/include/asm/nospec-branch.h
··· 321 321 /* The Intel SPEC CTRL MSR base value cache */ 322 322 extern u64 x86_spec_ctrl_base; 323 323 DECLARE_PER_CPU(u64, x86_spec_ctrl_current); 324 - extern void write_spec_ctrl_current(u64 val, bool force); 324 + extern void update_spec_ctrl_cond(u64 val); 325 325 extern u64 spec_ctrl_current(void); 326 326 327 327 /*
+14 -7
arch/x86/kernel/cpu/bugs.c
··· 60 60 61 61 static DEFINE_MUTEX(spec_ctrl_mutex); 62 62 63 + /* Update SPEC_CTRL MSR and its cached copy unconditionally */ 64 + static void update_spec_ctrl(u64 val) 65 + { 66 + this_cpu_write(x86_spec_ctrl_current, val); 67 + wrmsrl(MSR_IA32_SPEC_CTRL, val); 68 + } 69 + 63 70 /* 64 71 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ 65 72 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). 66 73 */ 67 - void write_spec_ctrl_current(u64 val, bool force) 74 + void update_spec_ctrl_cond(u64 val) 68 75 { 69 76 if (this_cpu_read(x86_spec_ctrl_current) == val) 70 77 return; ··· 82 75 * When KERNEL_IBRS this MSR is written on return-to-user, unless 83 76 * forced the update can be delayed until that time. 84 77 */ 85 - if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 78 + if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 86 79 wrmsrl(MSR_IA32_SPEC_CTRL, val); 87 80 } 88 81 ··· 1335 1328 1336 1329 if (ia32_cap & ARCH_CAP_RRSBA) { 1337 1330 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S; 1338 - write_spec_ctrl_current(x86_spec_ctrl_base, true); 1331 + update_spec_ctrl(x86_spec_ctrl_base); 1339 1332 } 1340 1333 } 1341 1334 ··· 1457 1450 1458 1451 if (spectre_v2_in_ibrs_mode(mode)) { 1459 1452 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; 1460 - write_spec_ctrl_current(x86_spec_ctrl_base, true); 1453 + update_spec_ctrl(x86_spec_ctrl_base); 1461 1454 } 1462 1455 1463 1456 switch (mode) { ··· 1571 1564 static void update_stibp_msr(void * __unused) 1572 1565 { 1573 1566 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP); 1574 - write_spec_ctrl_current(val, true); 1567 + update_spec_ctrl(val); 1575 1568 } 1576 1569 1577 1570 /* Update x86_spec_ctrl_base in case SMT state changed. */ ··· 1804 1797 x86_amd_ssb_disable(); 1805 1798 } else { 1806 1799 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; 1807 - write_spec_ctrl_current(x86_spec_ctrl_base, true); 1800 + update_spec_ctrl(x86_spec_ctrl_base); 1808 1801 } 1809 1802 } 1810 1803 ··· 2055 2048 void x86_spec_ctrl_setup_ap(void) 2056 2049 { 2057 2050 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 2058 - write_spec_ctrl_current(x86_spec_ctrl_base, true); 2051 + update_spec_ctrl(x86_spec_ctrl_base); 2059 2052 2060 2053 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) 2061 2054 x86_amd_ssb_disable();
+1 -1
arch/x86/kernel/process.c
··· 600 600 } 601 601 602 602 if (updmsr) 603 - write_spec_ctrl_current(msr, false); 603 + update_spec_ctrl_cond(msr); 604 604 } 605 605 606 606 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)