Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: added xgmi ras error reset sequence
added mechanism to clear xgmi ras status inbetween error queries
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
John Clements
and committed by
Alex Deucher
66399248
3aa0115d
+31
+30
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+30
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
···
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adev->gmc.xgmi.num_physical_nodes == 0)
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return 0;
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+
amdgpu_xgmi_reset_ras_error_count(adev);
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+
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if (!adev->gmc.xgmi.ras_if) {
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adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->gmc.xgmi.ras_if)
···
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dev_warn(adev->dev, "failed to enable DF-Cstate\n");
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return addr + dram_base_addr;
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+
}
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+
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static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
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{
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WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
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WREG32_PCIE(pcs_status_reg, 0);
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}
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+
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void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
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{
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uint32_t i;
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+
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switch (adev->asic_type) {
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case CHIP_ARCTURUS:
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for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
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pcs_clear_status(adev,
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xgmi_pcs_err_status_reg_arct[i]);
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break;
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case CHIP_VEGA20:
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for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
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pcs_clear_status(adev,
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xgmi_pcs_err_status_reg_vg20[i]);
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break;
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default:
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break;
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}
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}
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static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
···
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}
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break;
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}
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+
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amdgpu_xgmi_reset_ras_error_count(adev);
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err_data->ue_count += ue_cnt;
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err_data->ce_count += ce_cnt;
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
···
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uint64_t addr);
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int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status);
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+
void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev);
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static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
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struct amdgpu_device *bo_adev)