Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/imx: dc: Sort bits and bitfields in descending order
Consistently sort bits and bitfields from highest to lowest bits.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Link: https://lore.kernel.org/r/20251014114148.43922-1-marek.vasut@mailbox.org
authored by
Marek Vasut
and committed by
Liu Ying
6674f54b
33ea4d52
+27
-27
+4
-4
drivers/gpu/drm/imx/dc/dc-ed.c
+4
-4
drivers/gpu/drm/imx/dc/dc-ed.c
···
15
15
#include "dc-pe.h"
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#define PIXENGCFG_STATIC 0x8
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-
#define POWERDOWN BIT(4)
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-
#define SYNC_MODE BIT(8)
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-
#define SINGLE 0
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18
#define DIV_MASK GENMASK(23, 16)
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#define DIV(x) FIELD_PREP(DIV_MASK, (x))
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#define DIV_RESET 0x80
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+
#define SYNC_MODE BIT(8)
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+
#define SINGLE 0
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+
#define POWERDOWN BIT(4)
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#define PIXENGCFG_DYNAMIC 0xc
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···
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#define SYNC_TRIGGER BIT(0)
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#define STATICCONTROL 0x8
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+
#define PERFCOUNTMODE BIT(12)
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#define KICK_MODE BIT(8)
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#define EXTERNAL BIT(8)
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-
#define PERFCOUNTMODE BIT(12)
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#define CONTROL 0xc
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#define GAMMAAPPLYENABLE BIT(0)
+2
-2
drivers/gpu/drm/imx/dc/dc-fg.c
+2
-2
drivers/gpu/drm/imx/dc/dc-fg.c
···
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#define FGINCTRL 0x5c
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#define FGINCTRLPANIC 0x60
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-
#define FGDM_MASK GENMASK(2, 0)
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-
#define ENPRIMALPHA BIT(3)
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#define ENSECALPHA BIT(4)
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+
#define ENPRIMALPHA BIT(3)
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+
#define FGDM_MASK GENMASK(2, 0)
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#define FGCCR 0x64
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#define CCGREEN(x) FIELD_PREP(GENMASK(19, 10), (x))
+5
-5
drivers/gpu/drm/imx/dc/dc-fu.c
+5
-5
drivers/gpu/drm/imx/dc/dc-fu.c
···
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#define BASEADDRESSAUTOUPDATE(x) FIELD_PREP(BASEADDRESSAUTOUPDATE_MASK, (x))
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/* BURSTBUFFERMANAGEMENT */
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+
#define LINEMODE_MASK BIT(31)
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#define SETBURSTLENGTH_MASK GENMASK(12, 8)
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#define SETBURSTLENGTH(x) FIELD_PREP(SETBURSTLENGTH_MASK, (x))
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#define SETNUMBUFFERS_MASK GENMASK(7, 0)
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#define SETNUMBUFFERS(x) FIELD_PREP(SETNUMBUFFERS_MASK, (x))
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-
#define LINEMODE_MASK BIT(31)
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/* SOURCEBUFFERATTRIBUTES */
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#define BITSPERPIXEL_MASK GENMASK(21, 16)
···
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#define STRIDE(x) FIELD_PREP(STRIDE_MASK, (x) - 1)
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/* SOURCEBUFFERDIMENSION */
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-
#define LINEWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x))
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#define LINECOUNT(x) FIELD_PREP(GENMASK(29, 16), (x))
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+
#define LINEWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x))
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/* LAYEROFFSET */
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-
#define LAYERXOFFSET(x) FIELD_PREP(GENMASK(14, 0), (x))
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#define LAYERYOFFSET(x) FIELD_PREP(GENMASK(30, 16), (x))
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+
#define LAYERXOFFSET(x) FIELD_PREP(GENMASK(14, 0), (x))
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/* CLIPWINDOWOFFSET */
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-
#define CLIPWINDOWXOFFSET(x) FIELD_PREP(GENMASK(14, 0), (x))
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#define CLIPWINDOWYOFFSET(x) FIELD_PREP(GENMASK(30, 16), (x))
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+
#define CLIPWINDOWXOFFSET(x) FIELD_PREP(GENMASK(14, 0), (x))
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/* CLIPWINDOWDIMENSIONS */
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-
#define CLIPWINDOWWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x) - 1)
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#define CLIPWINDOWHEIGHT(x) FIELD_PREP(GENMASK(29, 16), (x) - 1)
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+
#define CLIPWINDOWWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x) - 1)
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enum dc_linemode {
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/*
+2
-2
drivers/gpu/drm/imx/dc/dc-fu.h
+2
-2
drivers/gpu/drm/imx/dc/dc-fu.h
···
33
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#define A_SHIFT(x) FIELD_PREP_CONST(GENMASK(4, 0), (x))
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/* LAYERPROPERTY */
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+
#define SOURCEBUFFERENABLE BIT(31)
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#define YUVCONVERSIONMODE_MASK GENMASK(18, 17)
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#define YUVCONVERSIONMODE(x) FIELD_PREP(YUVCONVERSIONMODE_MASK, (x))
38
-
#define SOURCEBUFFERENABLE BIT(31)
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/* FRAMEDIMENSIONS */
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-
#define FRAMEWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x))
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#define FRAMEHEIGHT(x) FIELD_PREP(GENMASK(29, 16), (x))
42
+
#define FRAMEWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x))
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/* CONTROL */
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#define INPUTSELECT_MASK GENMASK(4, 3)
+14
-14
drivers/gpu/drm/imx/dc/dc-lb.c
+14
-14
drivers/gpu/drm/imx/dc/dc-lb.c
···
17
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#include "dc-pe.h"
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#define PIXENGCFG_DYNAMIC 0x8
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-
#define PIXENGCFG_DYNAMIC_PRIM_SEL_MASK GENMASK(5, 0)
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-
#define PIXENGCFG_DYNAMIC_PRIM_SEL(x) \
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-
FIELD_PREP(PIXENGCFG_DYNAMIC_PRIM_SEL_MASK, (x))
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#define PIXENGCFG_DYNAMIC_SEC_SEL_MASK GENMASK(13, 8)
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21
#define PIXENGCFG_DYNAMIC_SEC_SEL(x) \
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FIELD_PREP(PIXENGCFG_DYNAMIC_SEC_SEL_MASK, (x))
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+
#define PIXENGCFG_DYNAMIC_PRIM_SEL_MASK GENMASK(5, 0)
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+
#define PIXENGCFG_DYNAMIC_PRIM_SEL(x) \
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+
FIELD_PREP(PIXENGCFG_DYNAMIC_PRIM_SEL_MASK, (x))
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#define STATICCONTROL 0x8
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#define SHDTOKSEL_MASK GENMASK(4, 3)
···
37
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#define BLENDCONTROL 0x10
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#define ALPHA_MASK GENMASK(23, 16)
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#define ALPHA(x) FIELD_PREP(ALPHA_MASK, (x))
40
-
#define PRIM_C_BLD_FUNC_MASK GENMASK(2, 0)
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-
#define PRIM_C_BLD_FUNC(x) \
42
-
FIELD_PREP(PRIM_C_BLD_FUNC_MASK, (x))
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-
#define SEC_C_BLD_FUNC_MASK GENMASK(6, 4)
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-
#define SEC_C_BLD_FUNC(x) \
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-
FIELD_PREP(SEC_C_BLD_FUNC_MASK, (x))
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-
#define PRIM_A_BLD_FUNC_MASK GENMASK(10, 8)
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-
#define PRIM_A_BLD_FUNC(x) \
48
-
FIELD_PREP(PRIM_A_BLD_FUNC_MASK, (x))
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40
#define SEC_A_BLD_FUNC_MASK GENMASK(14, 12)
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#define SEC_A_BLD_FUNC(x) \
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FIELD_PREP(SEC_A_BLD_FUNC_MASK, (x))
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+
#define PRIM_A_BLD_FUNC_MASK GENMASK(10, 8)
44
+
#define PRIM_A_BLD_FUNC(x) \
45
+
FIELD_PREP(PRIM_A_BLD_FUNC_MASK, (x))
46
+
#define SEC_C_BLD_FUNC_MASK GENMASK(6, 4)
47
+
#define SEC_C_BLD_FUNC(x) \
48
+
FIELD_PREP(SEC_C_BLD_FUNC_MASK, (x))
49
+
#define PRIM_C_BLD_FUNC_MASK GENMASK(2, 0)
50
+
#define PRIM_C_BLD_FUNC(x) \
51
+
FIELD_PREP(PRIM_C_BLD_FUNC_MASK, (x))
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#define POSITION 0x14
54
-
#define XPOS_MASK GENMASK(15, 0)
55
-
#define XPOS(x) FIELD_PREP(XPOS_MASK, (x))
56
54
#define YPOS_MASK GENMASK(31, 16)
57
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#define YPOS(x) FIELD_PREP(YPOS_MASK, (x))
56
+
#define XPOS_MASK GENMASK(15, 0)
57
+
#define XPOS(x) FIELD_PREP(XPOS_MASK, (x))
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enum dc_lb_blend_func {
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DC_LAYERBLEND_BLEND_ZERO,