Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Add Kaanapali SSPP sub-block support
Add support for Kaanapali platform SSPP sub-blocks, which
introduce structural changes including register additions,
removals, and relocations. Add the new common and rectangle
blocks, and update register definitions and handling to
ensure compatibility with DPU v13.0.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698712/
Link: https://lore.kernel.org/r/20260115092749.533-11-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Yuanjie Yang
and committed by
Dmitry Baryshkov
688c7734
cc4b81f1
+373
-4
+1
drivers/gpu/drm/msm/Makefile
+1
drivers/gpu/drm/msm/Makefile
+14
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+14
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
209
209
};
210
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/**
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+
* struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
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* @name: string name for debug purposes
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* @base: offset of this sub-block relative to the block offset
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* @len: register block length of this sub-block
216
+
*/
217
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struct dpu_sspp_v13_rec_blk {
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char name[DPU_HW_BLK_NAME_LEN];
219
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u32 base;
220
+
u32 len;
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};
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+
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+
/**
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* enum dpu_qos_lut_usage - define QoS LUT use cases
213
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*/
214
226
enum dpu_qos_lut_usage {
···
306
294
u32 qseed_ver;
307
295
struct dpu_scaler_blk scaler_blk;
308
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struct dpu_pp_blk csc_blk;
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+
struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
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+
struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
309
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const u32 *format_list;
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u32 num_formats;
+12
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+12
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
···
247
247
}
248
248
}
249
249
250
+
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
251
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u32 hbb = ctx->ubwc->highest_bank_bit - 13;
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+
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DPU_REG_WRITE(&ctx->hw, SSPP_FETCH_CONFIG,
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DPU_FETCH_CONFIG_RESET_VALUE |
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hbb << 18);
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+
}
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+
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dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
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unpack_pat_off, format_off,
252
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ubwc_ctrl_off, ubwc_error_off);
···
315
307
if (MSM_FORMAT_IS_UBWC(fmt))
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opmode |= MDSS_MDP_OP_BWC_EN;
317
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src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
318
-
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
319
-
DPU_FETCH_CONFIG_RESET_VALUE |
320
-
hbb << 18);
321
310
322
311
if (ctx->ubwc->ubwc_enc_version == UBWC_1_0) {
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fast_clear = fmt->alpha_enable ? BIT(31) : 0;
···
747
742
748
743
hw_pipe->mdss_ver = mdss_rev;
749
744
750
-
_setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
745
+
if (mdss_rev->core_major_ver >= 13)
746
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dpu_hw_sspp_init_v13(hw_pipe, hw_pipe->cap->features, mdss_rev);
747
+
else
748
+
_setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
751
749
752
750
return hw_pipe;
753
751
}
+4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
···
384
384
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
385
385
bool danger_safe_en, u32 ctrl_off);
386
386
387
+
void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
388
+
unsigned long features,
389
+
const struct dpu_mdss_version *mdss_rev);
390
+
387
391
#endif /*_DPU_HW_SSPP_H */
388
392
+321
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
+321
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/printk.h>
7
+
#include <linux/soc/qcom/ubwc.h>
8
+
9
+
#include "dpu_hw_sspp.h"
10
+
11
+
/* >= v13 DPU */
12
+
/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
13
+
/* Name Offset */
14
+
#define SSPP_CMN_CLK_CTRL 0x0
15
+
#define SSPP_CMN_CLK_STATUS 0x4
16
+
#define SSPP_CMN_MULTI_REC_OP_MODE 0x10
17
+
#define SSPP_CMN_ADDR_CONFIG 0x14
18
+
#define SSPP_CMN_CAC_CTRL 0x20
19
+
#define SSPP_CMN_SYS_CACHE_MODE 0x24
20
+
#define SSPP_CMN_QOS_CTRL 0x28
21
+
22
+
#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c
23
+
#define SSPP_CMN_FILL_LEVELS 0x40
24
+
#define SSPP_CMN_STATUS 0x44
25
+
#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48
26
+
#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c
27
+
#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50
28
+
#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54
29
+
#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58
30
+
#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c
31
+
#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60
32
+
#define SSPP_CMN_UNPACK_LINE_COUNT 0x64
33
+
#define SSPP_CMN_TPG_CONTROL 0x68
34
+
#define SSPP_CMN_TPG_CONFIG 0x6c
35
+
#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70
36
+
#define SSPP_CMN_TPG_RECTANGLE 0x74
37
+
#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78
38
+
#define SSPP_CMN_TPG_RGB_MAPPING 0x7c
39
+
#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80
40
+
41
+
/*RECRegisterset*/
42
+
/*Name Offset*/
43
+
#define SSPP_REC_SRC_FORMAT 0x0
44
+
#define SSPP_REC_SRC_UNPACK_PATTERN 0x4
45
+
#define SSPP_REC_SRC_OP_MODE 0x8
46
+
#define SSPP_REC_SRC_CONSTANT_COLOR 0xc
47
+
#define SSPP_REC_SRC_IMG_SIZE 0x10
48
+
#define SSPP_REC_SRC_SIZE 0x14
49
+
#define SSPP_REC_SRC_XY 0x18
50
+
#define SSPP_REC_OUT_SIZE 0x1c
51
+
#define SSPP_REC_OUT_XY 0x20
52
+
#define SSPP_REC_SW_PIX_EXT_LR 0x24
53
+
#define SSPP_REC_SW_PIX_EXT_TB 0x28
54
+
#define SSPP_REC_SRC_SIZE_ODX 0x30
55
+
#define SSPP_REC_SRC_XY_ODX 0x34
56
+
#define SSPP_REC_OUT_SIZE_ODX 0x38
57
+
#define SSPP_REC_OUT_XY_ODX 0x3c
58
+
#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40
59
+
#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44
60
+
#define SSPP_REC_PRE_DOWN_SCALE 0x48
61
+
#define SSPP_REC_SRC0_ADDR 0x4c
62
+
#define SSPP_REC_SRC1_ADDR 0x50
63
+
#define SSPP_REC_SRC2_ADDR 0x54
64
+
#define SSPP_REC_SRC3_ADDR 0x58
65
+
#define SSPP_REC_SRC_YSTRIDE0 0x5c
66
+
#define SSPP_REC_SRC_YSTRIDE1 0x60
67
+
#define SSPP_REC_CURRENT_SRC0_ADDR 0x64
68
+
#define SSPP_REC_CURRENT_SRC1_ADDR 0x68
69
+
#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c
70
+
#define SSPP_REC_CURRENT_SRC3_ADDR 0x70
71
+
#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74
72
+
#define SSPP_REC_CDP_CNTL 0x78
73
+
#define SSPP_REC_TRAFFIC_SHAPER 0x7c
74
+
#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80
75
+
#define SSPP_REC_PD_MEM_ALLOC 0x84
76
+
#define SSPP_REC_QOS_CLAMP 0x88
77
+
#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c
78
+
#define SSPP_REC_UBWC_STATIC_CTRL 0x90
79
+
#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94
80
+
#define SSPP_REC_UBWC_STATS_ROI 0x98
81
+
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c
82
+
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0
83
+
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4
84
+
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8
85
+
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac
86
+
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0
87
+
#define SSPP_REC_EXCL_REC_CTRL 0xb4
88
+
#define SSPP_REC_EXCL_REC_SIZE 0xb8
89
+
#define SSPP_REC_EXCL_REC_XY 0xbc
90
+
#define SSPP_REC_LINE_INSERTION_CTRL 0xc0
91
+
#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4
92
+
#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8
93
+
#define SSPP_REC_META_ERROR_STATUS 0xcc
94
+
#define SSPP_REC_UBWC_ERROR_STATUS 0xd0
95
+
#define SSPP_REC_FLUSH_CTRL 0xd4
96
+
#define SSPP_REC_INTR_EN 0xd8
97
+
#define SSPP_REC_INTR_STATUS 0xdc
98
+
#define SSPP_REC_INTR_CLEAR 0xe0
99
+
#define SSPP_REC_HSYNC_STATUS 0xe4
100
+
#define SSPP_REC_FP16_CONFIG 0x150
101
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154
102
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158
103
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c
104
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160
105
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164
106
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168
107
+
#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c
108
+
#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170
109
+
#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174
110
+
#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178
111
+
112
+
static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_index rect_index,
113
+
struct dpu_hw_sspp *ctx)
114
+
{
115
+
return (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) ?
116
+
ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base;
117
+
}
118
+
119
+
static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe)
120
+
{
121
+
struct dpu_hw_sspp *ctx = pipe->sspp;
122
+
123
+
if (!ctx)
124
+
return;
125
+
126
+
dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE);
127
+
}
128
+
129
+
static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe,
130
+
const struct msm_format *fmt, u32 flags)
131
+
{
132
+
struct dpu_hw_sspp *ctx = pipe->sspp;
133
+
u32 op_mode_off, unpack_pat_off, format_off;
134
+
u32 ubwc_ctrl_off, ubwc_err_off;
135
+
u32 offset;
136
+
137
+
if (!ctx || !fmt)
138
+
return;
139
+
140
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
141
+
142
+
op_mode_off = offset + SSPP_REC_SRC_OP_MODE;
143
+
unpack_pat_off = offset + SSPP_REC_SRC_UNPACK_PATTERN;
144
+
format_off = offset + SSPP_REC_SRC_FORMAT;
145
+
ubwc_ctrl_off = offset + SSPP_REC_UBWC_STATIC_CTRL;
146
+
ubwc_err_off = offset + SSPP_REC_UBWC_ERROR_STATUS;
147
+
148
+
dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
149
+
unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off);
150
+
}
151
+
152
+
static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx,
153
+
struct dpu_hw_pixel_ext *pe_ext)
154
+
{
155
+
struct dpu_hw_blk_reg_map *c;
156
+
u8 color;
157
+
u32 lr_pe[4], tb_pe[4];
158
+
const u32 bytemask = 0xff;
159
+
u32 offset = ctx->cap->sblk->sspp_rec0_blk.base;
160
+
161
+
if (!ctx || !pe_ext)
162
+
return;
163
+
164
+
c = &ctx->hw;
165
+
/* program SW pixel extension override for all pipes*/
166
+
for (color = 0; color < DPU_MAX_PLANES; color++) {
167
+
/* color 2 has the same set of registers as color 1 */
168
+
if (color == 2)
169
+
continue;
170
+
171
+
lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24) |
172
+
((pe_ext->right_rpt[color] & bytemask) << 16) |
173
+
((pe_ext->left_ftch[color] & bytemask) << 8) |
174
+
(pe_ext->left_rpt[color] & bytemask);
175
+
176
+
tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24) |
177
+
((pe_ext->btm_rpt[color] & bytemask) << 16) |
178
+
((pe_ext->top_ftch[color] & bytemask) << 8) |
179
+
(pe_ext->top_rpt[color] & bytemask);
180
+
}
181
+
182
+
/* color 0 */
183
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]);
184
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]);
185
+
186
+
/* color 1 and color 2 */
187
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]);
188
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]);
189
+
}
190
+
191
+
static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe,
192
+
struct dpu_sw_pipe_cfg *cfg)
193
+
{
194
+
struct dpu_hw_sspp *ctx = pipe->sspp;
195
+
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
196
+
u32 offset;
197
+
198
+
if (!ctx || !cfg)
199
+
return;
200
+
201
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
202
+
203
+
src_size_off = offset + SSPP_REC_SRC_SIZE;
204
+
src_xy_off = offset + SSPP_REC_SRC_XY;
205
+
out_size_off = offset + SSPP_REC_OUT_SIZE;
206
+
out_xy_off = offset + SSPP_REC_OUT_XY;
207
+
208
+
dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
209
+
src_xy_off, out_size_off, out_xy_off);
210
+
}
211
+
212
+
static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe,
213
+
struct dpu_hw_fmt_layout *layout)
214
+
{
215
+
struct dpu_hw_sspp *ctx = pipe->sspp;
216
+
int i;
217
+
u32 offset, ystride0, ystride1;
218
+
219
+
if (!ctx)
220
+
return;
221
+
222
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
223
+
224
+
for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
225
+
DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4,
226
+
layout->plane_addr[i]);
227
+
228
+
ystride0 = (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16);
229
+
ystride1 = (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16);
230
+
231
+
DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0);
232
+
DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1);
233
+
}
234
+
235
+
static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 color)
236
+
{
237
+
struct dpu_hw_sspp *ctx = pipe->sspp;
238
+
u32 const_clr_off;
239
+
u32 offset;
240
+
241
+
if (!ctx)
242
+
return;
243
+
244
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
245
+
const_clr_off = offset + SSPP_REC_SRC_CONSTANT_COLOR;
246
+
247
+
dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
248
+
}
249
+
250
+
static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx,
251
+
struct dpu_hw_qos_cfg *cfg)
252
+
{
253
+
if (!ctx || !cfg)
254
+
return;
255
+
256
+
dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
257
+
}
258
+
259
+
static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx,
260
+
bool danger_safe_en)
261
+
{
262
+
if (!ctx)
263
+
return;
264
+
265
+
dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL);
266
+
}
267
+
268
+
static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe,
269
+
const struct msm_format *fmt,
270
+
bool enable)
271
+
{
272
+
struct dpu_hw_sspp *ctx = pipe->sspp;
273
+
u32 offset = 0;
274
+
275
+
if (!ctx)
276
+
return;
277
+
278
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
279
+
dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable);
280
+
}
281
+
282
+
static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, bool enable)
283
+
{
284
+
static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
285
+
.reg_off = SSPP_CMN_CLK_CTRL,
286
+
.bit_off = 0
287
+
};
288
+
289
+
return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
290
+
}
291
+
292
+
void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
293
+
unsigned long features, const struct dpu_mdss_version *mdss_rev)
294
+
{
295
+
c->ops.setup_format = dpu_hw_sspp_setup_format_v13;
296
+
c->ops.setup_rects = dpu_hw_sspp_setup_rects_v13;
297
+
c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress_v13;
298
+
c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill_v13;
299
+
c->ops.setup_pe = dpu_hw_sspp_setup_pe_config_v13;
300
+
301
+
if (test_bit(DPU_SSPP_QOS, &features)) {
302
+
c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut_v13;
303
+
c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl_v13;
304
+
}
305
+
306
+
if (test_bit(DPU_SSPP_CSC, &features) ||
307
+
test_bit(DPU_SSPP_CSC_10BIT, &features))
308
+
c->ops.setup_csc = dpu_hw_sspp_setup_csc;
309
+
310
+
if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
311
+
test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
312
+
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect_v13;
313
+
314
+
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
315
+
c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
316
+
317
+
if (test_bit(DPU_SSPP_CDP, &features))
318
+
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp_v13;
319
+
320
+
c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl_v13;
321
+
}
+18
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+18
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
···
81
81
#define QOS_CREQ_LUT_0 0x14
82
82
#define QOS_CREQ_LUT_1 0x18
83
83
84
+
/* CMN_QOS_LUT */
85
+
#define SSPP_CMN_QOS_CTRL 0x28
86
+
#define SSPP_CMN_DANGER_LUT 0x2c
87
+
#define SSPP_CMN_SAFE_LUT 0x30
88
+
#define SSPP_CMN_CREQ_LUT_0 0x34
89
+
#define SSPP_CMN_CREQ_LUT_1 0x38
90
+
84
91
/* QOS_QOS_CTRL */
85
92
#define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
86
93
#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
···
479
472
}
480
473
481
474
DPU_REG_WRITE(c, offset + QOS_QOS_CTRL,
475
+
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
476
+
}
477
+
478
+
void dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
479
+
const struct dpu_hw_qos_cfg *cfg)
480
+
{
481
+
DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
482
+
DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
483
+
DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
484
+
DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
485
+
DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
482
486
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
483
487
}
484
488
+3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
···
367
367
bool qos_8lvl,
368
368
const struct dpu_hw_qos_cfg *cfg);
369
369
370
+
void dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
371
+
const struct dpu_hw_qos_cfg *cfg);
372
+
370
373
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
371
374
u32 misr_ctrl_offset, u8 input_sel);
372
375