Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
DPU version 13.0.0 introduces structural changes including
register additions, removals, and relocations.
Refactor SSPP-related code to be compatible with DPU 13.0.0
modifications.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698710/
Link: https://lore.kernel.org/r/20260115092749.533-10-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Yuanjie Yang
and committed by
Dmitry Baryshkov
cc4b81f1
b78956dc
+111
-41
+59
-41
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+59
-41
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
···
147
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static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
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{
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struct dpu_hw_sspp *ctx = pipe->sspp;
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-
u32 mode_mask;
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if (!ctx)
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return;
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+
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+
dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
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+
}
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+
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+
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
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struct dpu_hw_sspp *ctx, u32 op_mode_off)
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+
{
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u32 mode_mask;
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if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
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/**
···
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*/
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mode_mask = 0;
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} else {
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-
mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
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+
mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
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mode_mask |= pipe->multirect_index;
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if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
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mode_mask |= BIT(2);
···
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mode_mask &= ~BIT(2);
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}
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-
DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
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DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
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}
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-
static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
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void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
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u32 mask, u8 en)
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{
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const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
···
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DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
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}
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-
static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
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+
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
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u32 mask, u8 en)
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{
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const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
···
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const struct msm_format *fmt, u32 flags)
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{
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struct dpu_hw_sspp *ctx = pipe->sspp;
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-
struct dpu_hw_blk_reg_map *c;
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u32 chroma_samp, unpack, src_format;
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u32 opmode = 0;
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u32 fast_clear = 0;
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u32 op_mode_off, unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_error_off;
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if (!ctx || !fmt)
···
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ubwc_error_off = SSPP_UBWC_ERROR_STATUS;
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}
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}
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+
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dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
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unpack_pat_off, format_off,
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ubwc_ctrl_off, ubwc_error_off);
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}
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void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
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u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
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u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
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u32 ubwc_error_off)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 chroma_samp, unpack, src_format;
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u32 opmode;
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u32 fast_clear;
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c = &ctx->hw;
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opmode = DPU_REG_READ(c, op_mode_off);
···
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/* update scaler opmode, if appropriate */
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if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
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-
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
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+
dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
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MSM_FORMAT_IS_YUV(fmt));
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else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
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-
_sspp_setup_csc10_opmode(ctx,
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dpu_hw_sspp_setup_csc10_opmode(ctx,
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VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
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MSM_FORMAT_IS_YUV(fmt));
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···
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tot_req_pixels[3]);
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}
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-
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
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+
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
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struct dpu_hw_scaler3_cfg *scaler3_cfg,
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const struct msm_format *format)
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{
···
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struct dpu_sw_pipe_cfg *cfg)
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{
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struct dpu_hw_sspp *ctx = pipe->sspp;
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-
struct dpu_hw_blk_reg_map *c;
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u32 src_size, src_xy, dst_size, dst_xy;
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u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
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if (!ctx || !cfg)
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return;
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-
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c = &ctx->hw;
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if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
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pipe->multirect_index == DPU_SSPP_RECT_0) {
···
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out_xy_off = SSPP_OUT_XY_REC1;
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}
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-
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/* src and dest rect programming */
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src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
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src_size = (drm_rect_height(&cfg->src_rect) << 16) |
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drm_rect_width(&cfg->src_rect);
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dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
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dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
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drm_rect_width(&cfg->dst_rect);
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-
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/* rectangle register programming */
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DPU_REG_WRITE(c, src_size_off, src_size);
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DPU_REG_WRITE(c, src_xy_off, src_xy);
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DPU_REG_WRITE(c, out_size_off, dst_size);
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DPU_REG_WRITE(c, out_xy_off, dst_xy);
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dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
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src_xy_off, out_size_off, out_xy_off);
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}
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static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
···
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DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
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}
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-
static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
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void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
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const struct dpu_csc_cfg *data)
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{
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u32 offset;
···
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static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
540
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{
541
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struct dpu_hw_sspp *ctx = pipe->sspp;
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struct dpu_hw_fmt_layout cfg;
540
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u32 const_clr_off;
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541
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if (!ctx)
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return;
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+
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if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
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pipe->multirect_index == DPU_SSPP_RECT_0)
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const_clr_off = SSPP_SRC_CONSTANT_COLOR;
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else
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const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
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dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
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}
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+
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void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
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u32 color, struct dpu_hw_sspp *ctx,
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u32 const_clr_off)
557
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{
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struct dpu_hw_fmt_layout cfg;
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/* cleanup source addresses */
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memset(&cfg, 0, sizeof(cfg));
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ctx->ops.setup_sourceaddress(pipe, &cfg);
550
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-
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
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-
pipe->multirect_index == DPU_SSPP_RECT_0)
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DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
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-
else
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DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
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color);
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DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
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}
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static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
···
577
565
cfg);
578
566
}
579
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+
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
569
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bool danger_safe_en, u32 ctrl_off)
570
+
{
571
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DPU_REG_WRITE(&ctx->hw, ctrl_off,
572
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danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
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}
574
+
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static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
581
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bool danger_safe_en)
582
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{
583
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if (!ctx)
584
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return;
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-
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
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-
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
581
+
dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
588
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}
589
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static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
···
645
627
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
646
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629
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
648
-
c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
630
+
c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
649
631
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if (test_bit(DPU_SSPP_CDP, &features))
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c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
+52
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+52
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
···
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int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
333
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struct dentry *entry);
334
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+
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
336
+
u32 mask, u8 en);
337
+
338
+
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
339
+
u32 mask, u8 en);
340
+
341
+
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
342
+
struct dpu_hw_scaler3_cfg *scaler3_cfg,
343
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const struct msm_format *format);
344
+
345
+
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
346
+
const struct dpu_csc_cfg *data);
347
+
348
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void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
349
+
struct dpu_hw_sspp *ctx,
350
+
u32 op_mode_off);
351
+
352
+
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
353
+
u32 flags, struct dpu_hw_sspp *ctx,
354
+
u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
355
+
u32 ubwc_ctrl_off, u32 ubwc_err_off);
356
+
357
+
static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
358
+
struct dpu_hw_sspp *ctx, u32 src_size_off,
359
+
u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
360
+
{
361
+
struct dpu_hw_blk_reg_map *c;
362
+
u32 src_size, src_xy, dst_size, dst_xy;
363
+
364
+
c = &ctx->hw;
365
+
366
+
/* src and dest rect programming */
367
+
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
368
+
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
369
+
drm_rect_width(&cfg->src_rect);
370
+
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
371
+
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
372
+
drm_rect_width(&cfg->dst_rect);
373
+
374
+
/* rectangle register programming */
375
+
DPU_REG_WRITE(c, src_size_off, src_size);
376
+
DPU_REG_WRITE(c, src_xy_off, src_xy);
377
+
DPU_REG_WRITE(c, out_size_off, dst_size);
378
+
DPU_REG_WRITE(c, out_xy_off, dst_xy);
379
+
}
380
+
381
+
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
382
+
u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
383
+
384
+
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
385
+
bool danger_safe_en, u32 ctrl_off);
386
+
335
387
#endif /*_DPU_HW_SSPP_H */
336
388